JPH11354442A - Semiconductor thin film and semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor thin-film which is superior in crystallinity and to provide a high-performance semiconductor device, wherein a fast logic circuit is configured using it. SOLUTION: After an amorphous semiconductor thin-film is crystallized using a catalyzer element, a heating process is performed in an atmosphere comprising an halogen element for removing the catalyzer element. The crystalline semiconductor thin-film thus obtained represents almost (110) orientation, with continuity to almost all the crystal lattices in a grain boundary. Here, it is desirable that, with an orientation ratio of 0.9 or more, most crystal lattices have continuity at arbitrary grain boundaries. The grain boundaries contribute much to the improved movement characteristic of a carrier, resulting in a high- performance semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a semiconductor thin film formed on a substrate having an insulating surface and a semiconductor device using the same as an active layer. In particular, the present invention relates to a configuration in which a material containing silicon as a main component is used as a semiconductor thin film.

[0002] In this specification, "semiconductor device"
Refers to all devices that function using semiconductors,
The following are included in the category of the semiconductor device. (1) A single element such as a thin film transistor (TFT). (2) A semiconductor circuit using the single element of (1). (3) An electro-optical device composed of (1) and (2). (4) An electronic device including (2) and (3).

[0003]

2. Description of the Related Art In recent years, a technique of forming a thin film transistor (TFT) by using a semiconductor thin film (having a thickness of several hundred to several thousand degrees) formed on a substrate having an insulating surface has attracted attention. Thin film transistors are widely applied to electronic devices such as ICs and electro-optical devices, and are particularly rapidly developed as switching elements for image display devices.

For example, in a liquid crystal display device, a pixel matrix circuit for individually controlling pixel regions arranged in a matrix, a driving circuit for controlling the pixel matrix circuit, and a logic circuit (processor circuit) for processing an external data signal Attempts have been made to apply TFTs to any electric circuit such as a semiconductor device and a memory circuit.

At present, a TFT using an amorphous silicon film (amorphous silicon film) as an active layer has been put into practical use. In the circuit,
A TFT using a crystalline silicon film (polysilicon film, polycrystalline silicon film, etc.) is required.

For example, as a method of forming a crystalline silicon film on a glass substrate, there are known techniques described in Japanese Patent Application Laid-Open Nos. 7-130652 and 8-78329 by the present applicant. The techniques described in these publications use a catalyst element that promotes crystallization of an amorphous silicon film, thereby providing 500
It is possible to form a crystalline silicon film having excellent crystallinity by heat treatment at about 600 ° C. for about 4 hours.

[0007] In particular, the technique described in Japanese Patent Application Laid-Open No. 8-78329 is to perform the crystal growth substantially parallel to the substrate surface by applying the above-mentioned technique, and the inventors have found that the formed crystallized region is particularly laterally oriented. It is called the growth area (or lateral growth area).

However, even if a driving circuit is formed using such TFTs, the required performance is still not sufficiently satisfied. In particular, it is impossible at present to configure a high-speed logic circuit that requires an extremely high-speed operation from megahertz to gigahertz with a conventional TFT.

[0009]

The present inventors have repeated various thoughts and errors in order to improve the crystallinity of a crystalline silicon film having a crystal grain boundary (called a polycrystalline silicon film). . Semi-amorphous semiconductor (JP-A-57-160
No. 121, etc.) and mono-domain semiconductors (JP-A-8-139019)
Publication).

[0010] The concept common to the semiconductor films described in the above-mentioned publication is that the grain boundaries are substantially rendered harmless. That is, the biggest problem was to substantially eliminate crystal grain boundaries and to smoothly move carriers (electrons or holes).

However, it can be said that the semiconductor film described in the above publication is insufficient for performing the high-speed operation required by the logic circuit. That is, in order to realize a system-on-panel with a built-in logic circuit, it is required to develop a completely new material that has never existed before.

The present invention meets such a demand, and a semiconductor thin film for realizing an extremely high-performance semiconductor device capable of forming a high-speed logic circuit which cannot be manufactured by a conventional TFT. The task is to provide.
Another object is to provide a semiconductor device using such a semiconductor thin film.

[0013]

According to an aspect of the present invention, there is provided a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the plane orientation is substantially {110} orientation, and It is characterized in that almost any crystal lattice has continuity at an arbitrary crystal grain boundary.

Another aspect of the present invention is a semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals,
The plane orientation is approximately {110} orientation, and most of the lattice fringes observed so as to cross any crystal grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. It is characterized by the following.

The present invention is a technique for realizing a semiconductor thin film having the above configuration. A semiconductor device manufactured using such a semiconductor thin film has the following characteristics.

(1) At least the channel forming region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, and the plane orientation of the semiconductor thin film is approximately {110}.
It is oriented and most crystal lattices have continuity at an arbitrary grain boundary. (2) at least a channel forming region is constituted by a semiconductor thin film made of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals;
The plane orientation of the semiconductor thin film is approximately {110} orientation,
Most of the lattice fringes observed so as to cross an arbitrary grain boundary are linearly continuous between different crystal grains forming the grain boundary.

The configuration of the present invention as described above will be described in detail with the embodiments described below.

[0018]

[Embodiment 1] In this embodiment, a process of manufacturing a semiconductor thin film according to the present invention and a semiconductor device (specifically, a TFT) using the semiconductor thin film as an active layer will be described. After the description of the manufacturing process, knowledge obtained from the viewpoint of the crystal structure and the electrical characteristics of the TFT of the present invention will be described.

First, a quartz substrate 801 is prepared as a substrate having an insulating surface. A silicon substrate on which a thermal oxide film is formed can be used instead of the quartz substrate. Alternatively, a method may be employed in which an amorphous silicon film is formed once on a quartz substrate and then completely thermally oxidized to form an insulating film. further,
A quartz substrate, a ceramics substrate, or a silicon substrate on which a silicon nitride film is formed as an insulating film may be used.

Reference numeral 802 denotes an amorphous silicon film, which is adjusted so that the final film thickness (thickness in consideration of film reduction after thermal oxidation) is 10 to 75 nm (preferably 15 to 45 nm). It is important to thoroughly control the impurity concentration in the film when forming the film.

In this embodiment, typical impurities in the amorphous silicon film 802 are C (carbon), N (nitrogen),
The concentration of O (oxygen) and S (sulfur) is 5 × 10 ¹⁸ atom
It is controlled to be less than s / cm ³ (preferably 1 × 10 ¹⁸ atoms / cm ³ or less). If each impurity is present at a concentration higher than this, it will have an adverse effect on crystallization, and may cause deterioration of the film quality after crystallization.

Here, the impurity concentration in the amorphous silicon film formed under the conditions of the present embodiment was determined by SIMS (secondary ion mass spectrometry).
FIG. 23 shows the results of the examination. The sample used was an amorphous silicon film having a thickness of 0.5 μm formed on a silicon wafer. As a result, as shown in FIG. 23, it was confirmed that all the elements of C, N, and O were within the above concentration range. However, in this specification, the element concentration in the film is S
It is defined as the minimum value in the IMS measurement result.

In order to keep any of the elements C, N and O within the above concentration range, the reduced pressure heat CV used in this embodiment is used.
The D furnace is regularly dry-cleaned to clean the film forming chamber. Dry cleaning is 200 ~ 400
A 100-300 sccm ClF ₃ (chlorine fluoride) gas may be flowed into a furnace heated to about ° C., and the film formation chamber may be cleaned with fluorine generated by thermal decomposition.

According to the knowledge of the present inventors, the furnace temperature
300 ° C and the flow rate of ClF ₃ (chlorine fluoride) gas is 300s
In the case of ccm 2, it is possible to completely remove deposits (mainly composed mainly of silicon) having a thickness of about 2 μm in 4 hours.

It should be noted that the hydrogen concentration in the amorphous silicon film 802 is also a very important parameter, and a film with good crystallinity can be obtained by keeping the hydrogen content low. for that reason,
The amorphous silicon film 802 is preferably formed by a low pressure thermal CVD method. Note that the plasma CVD method can be used by optimizing the film formation conditions.

Next, a crystallization step of the amorphous silicon film 802 is performed. As a means of crystallization, JP-A-7-13 by the present inventor
The technique described in Japanese Patent Publication No. 0652 is used. Either of the means of Embodiment 1 and Embodiment 2 of the publication may be used, but in the present invention, it is preferable to use the technical contents described in Embodiment 2 (detailed in JP-A-8-78329).

According to the technique described in Japanese Patent Application Laid-Open No. 8-78329, first, a mask insulating film 803 for selecting a region to be added with a catalytic element is formed. The mask insulating film 803 has a plurality of openings for adding a catalyst element. The position of the crystal region can be determined by the position of the opening.

Then, a solution containing nickel (Ni) as a catalyst element for promoting crystallization of the amorphous silicon film is applied by a spin coating method to form a Ni-containing layer 804. In addition, as a catalyst element, in addition to nickel, cobalt (Co), iron (Fe), palladium (Pd), platinum (Pt), copper (Cu), gold (Au), and germanium (G
e) etc. can be used. (FIG. 8A)

In addition, in the step of adding the catalyst element, an ion implantation method using a resist mask or a plasma doping method can be used. In this case, the reduction of the occupied area of the addition region and the control of the growth distance of the lateral growth region are facilitated, so that this is an effective technique when configuring a miniaturized circuit.

Next, when the step of adding the catalyst element is completed,
After releasing hydrogen at 450 ° C for about 1 hour, heat treatment is performed in an inert atmosphere, a hydrogen atmosphere, or an oxygen atmosphere at a temperature of 500 to 700 ° C (typically 550 to 650 ° C) for 4 to 24 hours. The crystalline silicon film 802 is crystallized. In this embodiment, heat treatment is performed at 570 ° C. for 14 hours in a nitrogen atmosphere.

At this time, the crystallization of the amorphous silicon film 802 proceeds preferentially from the nucleus generated in the region 805 to which nickel has been added, and the crystal region 806 grown almost parallel to the substrate surface of the substrate 801 is formed. It is formed. The present inventors call this crystal region 306 a lateral growth region. Since the individual crystals are aggregated in a relatively uniform state in the lateral growth region, there is an advantage that the overall crystallinity is excellent. (FIG. 8 (B))

When the technique described in the first embodiment of Japanese Patent Application Laid-Open No. Hei 7-130652 is used, a region which can be microscopically called a lateral growth region is formed. However,
Since nucleation occurs unevenly in the plane, there is a difficulty in controllability of crystal grain boundaries.

After the heat treatment for crystallization is completed, the mask insulating film 803 is removed and patterning is performed, and an island-shaped semiconductor layer (active layer) 807 including only the lateral growth region 806 is formed.
To form

Next, a gate insulating film 808 made of an insulating film containing silicon is formed. The thickness of the gate insulating film 808 may be adjusted in the range of 20 to 250 nm in consideration of the increase due to the subsequent thermal oxidation step. As a film formation method, a known gas phase method (a plasma CVD method, a sputtering method, or the like) may be used.

Next, as shown in FIG. 8C, a heat treatment (a catalyst element gettering process) for removing or reducing the catalyst element (nickel) is performed. In this heat treatment, a halogen element is contained in the treatment atmosphere, and the gettering effect of the metal element by the halogen element is used.

In order to sufficiently obtain the gettering effect by the halogen element, it is preferable to perform the above-mentioned heat treatment at a temperature exceeding 700 ° C. Below this temperature, the decomposition of the halogen compound in the processing atmosphere becomes difficult, and the gettering effect may not be obtained.

Therefore, in this embodiment, this heat treatment is performed
The reaction is carried out at a temperature higher than 800C, preferably 800 to 1000C (typically 950C), and the treatment time is 0.1 to 6 hours, typically 0.5 to 1 hour.

In this embodiment, hydrogen chloride (HCl) is 0.5 to 10% by volume relative to the oxygen atmosphere (in this embodiment, 3 to 10% by volume).
Volume%) in an atmosphere containing
An example in which heat treatment is performed at 30 ° C. for 30 minutes will be described. If the HCl concentration is higher than the above-mentioned concentration, the surface of the active layer 807 is not preferably formed because the surface thereof has irregularities of about the film thickness.

The compound containing a halogen element is HC
Although the example using 1 gas was shown, as other gas,
Typically, HF, NF ₃ , HBr, Cl ₂ , ClF ₃ ,
One or more compounds selected from compounds containing halogen such as BCl ₃ , F ₂ and Br ₂ can be used.

In this step, it is considered that nickel in the active layer 807 is gettered by the action of chlorine, becomes volatile nickel chloride, escapes to the atmosphere, and is removed. By this step, the concentration of nickel in active layer 807 is reduced to 5 × 10 ¹⁷ atoms / cm ³ or less.

The value of 5 × 10 ¹⁷ atoms / cm ³ corresponds to SI
It is the detection lower limit of MS (mass secondary ion analysis). As a result of analyzing a TFT manufactured by the present inventors, 1 × 10 ¹⁸ atoms /
cm ³ or less (preferably 5 × 10 ¹⁷ atoms / cm ³ or less)
The effect of nickel on the FT characteristics was not confirmed.
However, the impurity concentration in this specification is defined by the minimum value of the measurement result of the SIMS analysis.

The heat treatment causes a thermal oxidation reaction to proceed at the interface between the active layer 807 and the gate insulating film 808, and the thickness of the gate insulating film 808 increases by the amount of the thermal oxide film.
When the thermal oxide film is formed in this manner, a semiconductor / insulating film interface having very few interface states can be obtained. Also,
There is also an effect of preventing poor formation (edge thinning) of a thermal oxide film at the end of the active layer.

Further, it is also effective to improve the film quality of the gate insulating film 808 by performing a heat treatment at 950 ° C. for about 1 hour in a nitrogen atmosphere after the heat treatment in the halogen atmosphere.

According to SIMS analysis, the active layer 807 contains 1 × 10 10 halogen elements used for gettering.
It has been confirmed that it remains at a concentration of ¹⁵ to 1 × 10 ²⁰ atoms / cm ³ . At that time, it has been confirmed by SIMS analysis that the halogen element described above is distributed at a high concentration between the active layer 807 and the thermal oxide film formed by the heat treatment.

As a result of SIMS analysis of other elements, typical impurities C (carbon), N (nitrogen), O (oxygen) and S (sulfur) were all 5 × 10 ¹⁸ atoms.
It was confirmed to be less than s / cm ³ (typically 1 × 10 ¹⁸ atoms / cm ³ or less).

Next, a metal film mainly composed of aluminum (not shown) is formed, and a gate electrode prototype 809 is formed by patterning. In this embodiment, an aluminum film containing 2 wt% of scandium is used. In addition,
Alternatively, a tantalum film, a conductive silicon film, or the like can be used. (FIG. 8 (D))

Here, the technique described in JP-A-7-135318 by the present inventors is used. This publication discloses a technique for forming a source / drain region and a low-concentration impurity region in a self-aligned manner by using an oxide film formed by anodic oxidation.

First, anodizing is performed in a 3% oxalic acid aqueous solution while leaving a resist mask (not shown) used for patterning the aluminum film, to form a porous anodic oxide film 810.

The thickness of the porous anodic oxide film 810 increases in proportion to time. Further, since the resist mask remains on the upper surface, it is formed only on the side surface of the prototype 809 of the gate electrode. In the technique described in Japanese Patent Application Laid-Open No. Hei 7-135318, this film thickness later becomes the length of the low-concentration impurity region (also called the LDD region). In this embodiment, the anodic oxidation treatment is performed under the condition that the film thickness becomes 700 nm.

Next, after removing a resist mask (not shown), anodizing is performed in an electrolytic solution obtained by mixing 3% tartaric acid with an ethylene glycol solution. In this process, a dense nonporous anodic oxide film 811 is formed. Since the electrolytic solution also penetrates inside the porous anodic oxide film, it is also formed inside the porous anodic oxide film.

The thickness of the non-porous anodic oxide film 811 is determined according to the applied voltage. In this embodiment, the anodic oxidation treatment is performed at an applied voltage of 80 V so as to form a film having a thickness of about 100 nm.

The aluminum film 812 remaining after the above-described two anodic oxidation treatments substantially functions as a gate electrode.

When the state shown in FIG. 8E is obtained,
Next, the gate insulating film 808 is etched by a dry etching method using the gate electrode 812 and the porous anodic oxide film 810 as a mask. Then, the porous anodic oxide film 81
Remove 0. Gate insulating film 813 thus formed
Are exposed by the thickness of the porous anodic oxide film 810. (FIG. 9A)

Next, a step of adding an impurity element imparting one conductivity is performed. As an impurity element, P (phosphorus) or As (arsenic) may be used for N type, and B (boron) may be used for P type.

In this embodiment, the first impurity addition is performed at a high accelerating voltage to form n ⁻ regions 814 and 815. At this time, since the accelerating voltage is as high as about 80 keV, the impurity element is added not only on the surface of the active layer but also below the end of the exposed gate insulating film. The n ⁻ regions 814 and 815 are adjusted so that the impurity concentration becomes 1 × 10 ¹⁸ to 1 × 10 ¹⁹ atoms / cm ³ . (FIG. 9 (B))

Further, the second impurity addition is performed at a low acceleration voltage to form n ⁺ regions 816 and 817. At this time, since the acceleration voltage is as low as about 10 keV, the gate insulating film functions as a mask. Also, the n ⁺ regions 816 and 817 are adjusted so that the sheet resistance becomes 500Ω or less (preferably 300Ω or less). (FIG. 9 (C))

The impurity region formed in the above steps has n
^{The +} region becomes the source region 816 and the drain region 817, and the n ⁻ region becomes the low concentration impurity region 818. Also,
The region immediately below the gate electrode is not doped with an impurity element, and becomes a substantially intrinsic channel forming region 819.

The low-concentration impurity region 818 has an effect of relaxing a high electric field applied between the channel forming region 819 and the drain region 817, and is also called an LDD (lightly doped drain) region.

When the active layer is completed as described above, the impurity element is activated by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, an interlayer insulating film 820 is formed to a thickness of 500 nm. As the interlayer insulating film 820, a silicon oxide film, a silicon nitride film, a silicon oxynitride film, an organic resin film, or a stacked film thereof can be used.

As the organic resin film, polyimide,
Acrylic, polyamide, polyimide amide and the like are used. The advantages of the organic resin film are that the film formation method is simple, the film thickness can be easily increased, the parasitic capacitance can be reduced because the relative dielectric constant is low, and the flatness is excellent. .

Next, after forming a contact hole, a source electrode 821 and a drain electrode 822 are formed. Finally, the entire substrate is heated in a hydrogen atmosphere at 350 ° C. for 1 to 2 hours to hydrogenate the entire device, thereby terminating dangling bonds (unpaired bonds) in the film (especially in the active layer).

Through the above steps, a TFT having a structure as shown in FIG. 9D can be manufactured. The features of the TFT thus obtained will be described below.

[Knowledge on Crystal Structure of Active Layer] The active layer formed according to the above-mentioned manufacturing process is a crystal in which a plurality of rod-shaped or flat rod-shaped crystals are microscopically arranged substantially parallel to each other with regularity in a specific direction. Having a structure. This can be easily confirmed by observation with a TEM (transmission electron microscope).

Here, FIG. 1 shows an HR-TEM photograph in which the grain boundary between rod-shaped or flat rod-shaped crystals is magnified 8 million times. In this specification, a crystal grain boundary is defined as a grain boundary formed at a boundary where rod-shaped or flat rod-shaped crystals are in contact. Therefore, for example, it is considered separately from a grain boundary in a macro meaning such that the lateral growth region is formed by collision.

By the way, the above-mentioned HR-TEM (high-resolution transmission electron microscopy) means that a sample is irradiated with an electron beam perpendicularly, and the atomic / molecular arrangement is made utilizing the interference of transmitted electrons and elastic scattered electrons. It is a technique to evaluate.

In the HR-TEM, the arrangement state of the crystal lattice can be observed as lattice fringes. Therefore, by observing the crystal grain boundaries, it is possible to estimate the bonding state between atoms at the crystal grain boundaries. Although the lattice fringes appear as white and black fringes, they are differences in contrast and do not indicate the positions of atoms.

FIG. 1A is a typical TEM photograph of the crystalline silicon film obtained by the present invention, in which two different crystal grains are in contact at a crystal grain boundary seen from the upper left to the lower right of the photograph. Have been. At this time, the two crystal grains were roughly {110} oriented, although the crystal axes contained some deviation.

As will be described later, as a result of examining a plurality of crystal grains, it has been confirmed by X-ray diffraction and electron beam diffraction that almost all of the crystal grains have a substantially {110} orientation.

It should be noted that there should be (011) plane and (101) plane among many observations, but these equivalent planes are collectively expressed as {110} plane. This will be briefly described with reference to FIG.

FIG. 2A is an example schematically showing a crystal grain having a {110} crystal plane (the crystal axis is <110>). The {110} crystal plane includes a <111> axis, a <100> axis, and the like.

The notation method as shown in FIG. 2A is an example of collective exponential notation. When this is expressed in strict exponential notation, it becomes as shown in FIGS. 2 (B) and 2 (C). For example, the crystal axis [11
0] and the crystal axis [01-1] are both equivalent, and <1
10>.

The format is expressed as [01-1] for the convenience of the format, but the -1 (-) is used instead of the logical symbol indicating inversion.

As described above, various approaches can be taken when discussing the strict crystal orientation (crystal axis). Therefore, for the sake of simplicity, the following descriptions are all represented by collective exponential notation. Of course,
Similar physical properties are obtained on all equivalent crystal planes.

As shown in FIG. 1A, lattice fringes corresponding to the {111} plane and the {100} plane are observed in the plane. Note that the lattice fringe corresponding to the {111} plane indicates a lattice fringe such that a {111} plane appears in a cross section when a crystal grain is cut along the lattice fringe. The plane to which the grid pattern corresponds can be easily confirmed from the interval between the grid patterns. In the case of FIG.
The interval between the lattice fringes corresponding to the 1 ° plane is about 0.3 nm.

Note that the crystal grains on the upper side of FIG.
While a plurality of lattice fringes can be observed diagonally, only one lattice fringe can be seen in the lower crystal grain. It is considered that the reason is influenced by the irradiation direction of the electron beam during the TEM observation. That is, the upper crystal grain is irradiated with an electron beam perpendicular to the crystal plane, so that a plurality of in-plane lattice fringes can be seen, but the lower crystal grain is slightly inclined with respect to the upper crystal, so that the electron beam is inclined. Does not hit vertically, and only a specific plaid is visible.

Here, attention is paid to the lattice fringe corresponding to the {111} plane. As is clear from FIG. 1A, the lattice fringes corresponding to the {111} plane of the upper crystal grain (two of which are visible in the figure but one of them) correspond to the {111} plane of the lower crystal grain. Are parallel to each other.

The lattice fringes of two different crystal grains are connected so as to cross the crystal grain boundaries regardless of the existence of the crystal grain boundaries. That is, it can be confirmed that most of the lattice fringes observed so as to cross the crystal grain boundary are linearly continuous despite the lattice fringes of different crystal grains. This is the same at any grain boundary, and 90% or more (typically, 95% or more) of the lattice fringes maintain continuity at the grain boundary.

Such a crystal structure is the most significant feature of the crystalline silicon film of the present invention, and is a crystal structure that realizes the crystal grain boundaries determined by the present inventors.

Such a crystal structure (accurately, a structure of a crystal grain boundary) indicates that two different crystal grains are bonded to each other with extremely high consistency at the crystal grain boundary. That is, the crystal lattice is continuously connected at the crystal grain boundary, and it is very difficult to form a trap level due to a crystal defect or the like. In other words, it can be said that the crystal lattice has continuity at the crystal grain boundaries.

An HR-TEM photograph of a conventional high-temperature polysilicon film is shown in FIG. 1B for reference. FIG. 1 (B)
In the case of, as described later, the crystal plane has no regularity, and {110}
The orientation was not plane-based. However, here, for comparison with FIG. 1A, crystal grains in which lattice fringes corresponding to the {111} plane appear were observed.

Only one lattice fringe in FIG. 1B can be seen in both the upper and lower crystal grains. The reason is as described above. In addition, as a result of measuring the intervals of the lattice fringes by the same method as the above, it can be confirmed that the lattice fringes seen in the upper and lower crystal grains are lattice fringes corresponding to the {111} plane as shown in FIG. Was.

However, as shown in FIG. 1B, the lattice fringes were not parallel to each other, and it was found that the lattice structure was clearly different from the crystal structure shown in FIG. 1A.

Further, as shown by arrows in the figure, many portions where lattice fringes are broken can be confirmed at the crystal grain boundaries. In such a portion, dangling bonds (which can be called crystal defects) are present, and there is a high possibility that the movement of carriers is inhibited as a trap level.

As described above, in the crystalline silicon film of the present invention, the lattice has continuity even at the crystal grain boundaries, and such crystal defects could hardly be confirmed. From this point, it is proved that the crystalline silicon film of the present invention is a semiconductor film which is clearly different from the conventional high-temperature polysilicon.

Next, FIG. 3 shows the result obtained by examining the crystalline silicon film of the present invention by electron beam diffraction. Here, FIG.
3A shows a typical electron diffraction pattern of the crystalline silicon film of the present invention, and FIG. 3B shows a typical electron diffraction pattern of a conventional high-temperature polysilicon film as a reference.

In FIGS. 3A and 3B, the measurement is performed with the diameter of the electron beam irradiation spot set to 1.35 μm.
It may be considered that information of a region that is sufficiently macroscopic compared to the checkerboard level is picked up.

FIG. 3C shows the single crystal silicon of {1}.
It is an electron beam diffraction pattern at the time of irradiating an electron beam perpendicularly to a 10-degree plane. Usually, the electron diffraction pattern is compared with the observation result to estimate the orientation of the observation sample.

In the case of FIG. 3A, diffraction spots corresponding to the <110> incidence as shown in FIG. 3C appear relatively clearly, and the crystal axis is the <110> axis (the crystal plane is $ 1
10 ° plane).

Each spot has a slightly concentric spread, which is expected to have a certain degree of rotation angle distribution around the crystal axis. The extent of the spread is within 5 ° when estimated from the pattern.

In some cases, diffraction spots were partially invisible during many observations (even in FIG. 3A, some diffraction spots were not visible). Probably, although the orientation is roughly {110} orientation, the diffraction pattern is invisible because the crystal axis is slightly shifted.

The present inventors have found that almost always {11
Considering the fact that a 1｝ plane is included, probably <11
1) It is speculated that the deviation of the rotation angle around the axis may cause such a phenomenon.

On the other hand, in the case of the electron diffraction pattern shown in FIG. 3B, no clear regularity is observed in the diffraction spots, and it can be confirmed that the diffraction spots are almost randomly oriented. That is, $ 1
It is expected that crystals having a plane orientation other than the 10 ° plane will be randomly mixed.

As shown by these results, the characteristics of the crystalline silicon film of the present invention are that almost all the crystal grains are substantially oriented in the {110} plane, and that the lattice is continuous at the crystal grain boundaries. It is in. This feature is not present in the conventional polysilicon film.

Almost all of the crystal grains are approximately {110}
The reason for the orientation in the plane is described in Japanese Patent Laid-Open No. 7-321339 by the present inventors.
It is presumed as follows from the contents described in the above-mentioned publication.

When the amorphous silicon film is crystallized, the growth direction of a rod-like or flat rod-like crystal (sometimes called a needle-like or columnar crystal) that grows substantially parallel to the substrate may be the <111> axis. Confirmed by TEM photograph. This situation is schematically shown in FIG.

When crystallizing an amorphous silicon film using Ni as a catalyst element, <111> is mediated by NiSi ₂ precipitates.
The crystal grows along the axial direction. This is NiSi ₂ and Si
It is considered that the {111} planes have good structural consistency in the crystal planes.

Since the inside of the grown rod-shaped or flat rod-shaped crystal can be regarded as substantially a single crystal, FIG.
Described as Si (crystal silicon).

At this time, various planes can be formed on the side surfaces (planes parallel to the growth direction) of the rod-shaped or flat rod-shaped crystal grown along the <111> axis direction. It is a 110-degree plane. This is probably because the {110} plane has the highest atomic density among several planes that can be formed on the side surface.

For these reasons, as described in the present invention, $ 11
In the crystal grains grown with the 1} plane at the top (crystal grains grown along the <111> axis direction), the {110} plane appears on the surface (meaning the observation plane).

The present inventors performed X-ray diffraction in accordance with the method described in JP-A-7-321339, and calculated the orientation ratio of the crystalline silicon film of the present invention. In this publication, the orientation ratio is defined by a calculation method as shown in the following Expression 1.

[0102]

(Equation 1)

Here, the orientation of the semiconductor thin film of the present invention is expressed by X
FIG. 24 shows an example of the result measured by the line diffraction. Note that X
Although a peak corresponding to the (220) plane appears in the line diffraction pattern, it is needless to say that the peak is equivalent to the {110} plane. As a result of this measurement, the {110} plane is the main orientation, and the orientation ratio is 0.7 or more (typically 0.9 or more).
Turned out to be.

As described above, it can be seen that the crystalline silicon film of the present invention and the conventional polysilicon film have completely different crystal structures (crystal structures). From this point, it can be said that the crystalline silicon film of the present invention is a completely new semiconductor film.

In forming the semiconductor thin film of the present invention, the annealing step at a temperature higher than the crystallization temperature (in the case of this embodiment, the step shown in FIG. 8C) is important for reducing defects in crystal grains. Plays a role. This will be described.

FIG. 21A is a TEM photograph magnifying the crystalline silicon film by 250,000 times at the time when the crystallization step shown in FIG. 8B is completed. (The portion appears due to the difference in contrast), and a defect that looks like a zigzag as shown by an arrow is confirmed.

Such defects are mainly stacking faults in which the stacking order of atoms on the silicon crystal lattice plane is different from each other, but there are also cases such as dislocations. FIG. 21 (A) shows $ 11.
It is considered to be a stacking fault having a defect plane parallel to the 1｝ plane. This can be inferred from the fact that the zigzag-shaped defect is bent at an angle of about 70 °.

On the other hand, as shown in FIG. 21B, in the crystalline silicon film of the present invention viewed at the same magnification, almost no defects caused by stacking faults or dislocations were found in the crystal grains. It can be confirmed that the crystallinity is high. This tendency can be said for the entire film surface. Although it is difficult at present to reduce the number of defects, it can be reduced to a level that can be regarded as substantially zero.

That is, in the crystalline silicon film shown in FIG. 21B, defects in crystal grains are reduced to almost negligible level, and the crystal grain boundaries cannot be a barrier to carrier movement due to high continuity. Therefore, it can be regarded as a single crystal or substantially a single crystal.

As described above, in the crystalline silicon film shown in the photographs of FIGS. 21A and 21B, the grain boundaries have almost the same continuity, but the number of defects in the crystal grains is large. There is a difference.
The reason that the crystalline silicon film of the present invention exhibits much higher electrical characteristics than the crystalline silicon film shown in FIG. 21A is largely due to the difference in the number of defects.

As described above, FIG.
It can be understood that the steps shown in FIG. The present applicant has considered the following model for the phenomenon caused by this process.

First, in the state shown in FIG. 21A, a catalytic element (typically, nickel) is segregated in a defect (mainly, stacking fault) in a crystal grain. That is, it is considered that there are many Si—Ni—Si bonds.

However, when the Ni present in the defect is removed by performing the catalytic element gettering process,
The Si-Ni bond breaks. Therefore, the remaining bonds of silicon immediately form Si-Si bonds and are stabilized. Thus, the defect disappears.

It is of course known that thermal annealing at a high temperature eliminates defects in the crystalline silicon film. However, in the present invention, the bond with nickel is broken and many dangling bonds are generated. It can be assumed that the coupling is performed more smoothly.

At the same time, excess silicon atoms generated when the crystalline silicon film is thermally oxidized move to the defects,
It is considered that this greatly contributes to the formation of -Si bonds. This concept is known as the reason that there are few defects in the crystal grains of the high-temperature polysilicon film.

Further, the present applicant has found that by performing a heat treatment at a temperature exceeding the crystallization temperature (typically 700 to 1100 ° C.), the crystalline silicon film is fixed to the underlayer and the adhesion is enhanced. We are considering a model where defects disappear in the process.

There is a difference of about 10 times in the thermal expansion coefficient between the crystalline silicon film and the silicon oxide film serving as the base film. Therefore,
At the stage where the amorphous silicon film is transformed into a crystalline silicon film (FIG. 21A), a very large stress is applied to the crystalline silicon film when the crystalline silicon film is cooled.

This will be described with reference to FIG. FIG. 22A shows a thermal history applied to the crystalline silicon film after the crystallization step. First, the crystalline silicon film crystallized at the temperature (t ₁ ) is cooled to room temperature after a cooling period (a).

Here, FIG. 22B shows a crystalline silicon film in the cooling period (a), 1050 is a quartz substrate, and 1051 is a crystalline silicon film. At this time, the interface 10 between the crystalline silicon film 1051 and the quartz substrate 1050 is
The adhesion at 52 is not so high, and it is considered that this causes a large number of intragranular defects.

That is, the crystalline silicon film 1051 pulled by the difference in thermal expansion coefficient is very easy to move on the quartz substrate 1050, and a defect 1053 such as a stacking fault or a dislocation is easily generated by a force such as a tensile stress. Conceivable.

FIG. 21 shows the crystalline silicon film thus obtained.
The state shown in FIG. Then, as shown in FIG. 22A, a gettering step of the catalytic element is performed at the temperature (t ₂ ), and as a result, the defects in the crystalline silicon film disappear for the above-mentioned reason.

What is important here is that at the same time as the step of gettering the catalytic element is performed, the crystalline silicon film is fixed to the quartz substrate, and the adhesion to the quartz substrate is enhanced. That is,
It is considered that this gettering step also serves as a step of fixing the crystalline silicon film and the quartz substrate (base).

When the gettering + fixing step is completed in this way, the substrate is cooled down to room temperature after a cooling period (b). The difference from the cooling period (a) after the crystallization step is that the interface 1055 between the quartz substrate 1050 and the annealed crystalline silicon film 1054 is in a state of extremely high adhesion. (FIG. 22 (C))

When the adhesion is high, the quartz substrate 1050
However, since the crystalline silicon film 1054 is completely fixed, even if stress is applied to the crystalline silicon film during the cooling of the crystalline silicon film, no defect occurs. That is, it is possible to prevent a defect from occurring again.

Although the process of lowering the temperature to room temperature after the crystallization step is taken as an example in FIG. 22A, the gettering + fixing step can be performed after the crystallization is completed by raising the temperature. Even through such a process, the crystalline silicon film of the present invention can be obtained.

The thus-obtained crystalline silicon film of the present invention (FIG. 21B) is much more remarkable than the crystalline silicon film obtained by merely crystallization (FIG. 21A). It has the characteristic of a small number.

The difference in the number of defects was determined by electron spin resonance analysis (El
ectron Spin Resonance (ESR) appears as a difference in spin density. At present, it has been found that the spin density of the crystalline silicon film of the present invention is at least 5 × 10 ¹⁷ spins / cm ³ or less (preferably 3 × 10 ¹⁷ spins / cm ³ or less). However, since this measured value is close to the detection limit of the existing measuring device, the actual spin density is expected to be lower.

The crystalline silicon film of the present invention having the above-described crystal structure and characteristics is made of continuous grain silicon (Cont.
It is called in continuous grain silicon (CGS).

[Knowledge Regarding Electrical Characteristics of TFT] A TFT manufactured by using a crystalline silicon film as an active layer as described above is shown in FIG.
The electrical characteristics shown in FIG. FIG. 4 shows an Id-Vg curve (Id-Vg characteristic) of an N-channel TFT in which the abscissa plots the gate voltage (Vg) and the ordinate plots the logarithm of the drain voltage (Id). In addition, the measurement of the electrical characteristics was performed using a commercially available device (manufactured by Hewlett-Packard Company, model number 4145B)
This was performed using

In FIG. 4, reference numeral 401 denotes the electrical characteristics of a TFT using the active layer obtained in the above-described process, and reference numeral 402 denotes the electrical characteristics of a conventional TFT. Here, a TFT in which heat treatment (gettering process) after forming a gate insulating film in Example 1 is not performed is described as a conventional TFT.

When comparing the characteristics of both transistors, the characteristic indicated by 401 is 2 to 2 even at the same gate voltage.
It can be confirmed that a large on-current flows by almost four orders of magnitude. Note that the ON current refers to a drain current that flows when the TFT is in an ON state (the gate voltage is in a range of about 0 to 5 V in FIG. 4).

It can also be confirmed that the characteristic indicated by 401 has a superior sub-threshold characteristic. The sub-threshold characteristic is a parameter indicating the steepness of the switching operation of the TFT. The steeper the rise of the Id-Vg curve when the TFT switches on or off, the better the sub-threshold characteristic.

The typical electrical characteristics of the TFT obtained by the present invention are as follows. (1) The subthreshold coefficient, which is a parameter indicating the switching performance of the TFT (the agility of switching on / off operation), is 60 to 60 for both the N-type TFT and the P-type TFT.
100mV / decade (typically 60-85mV / decade). Note that this data value is almost equivalent to that of an insulated gate field effect transistor (IGFET) using single crystal silicon. (2) The field effect mobility (μ _FE ), which is a parameter indicating the operation speed of the TFT, is 200 to 650 cm ² for an N-type TFT.
/ Vs (typically 250 to 300 cm ² / Vs), 10 for P-type TFT
It is as large as 0 to 300 cm ² / Vs (typically 150 to 200 cm ² / Vs). (3) The threshold voltage (V _th ), which is a parameter of the drive voltage of the TFT, is -0.5 to 1.5 V for the N-type TFT,
It is as small as -1.5 to 0.5 V for P-type TFT. This means that power consumption can be reduced by driving with a small power supply voltage.

As described above, the TFT obtained by the present invention has extremely excellent switching characteristics and high-speed operation characteristics.

(Characteristics of a circuit constituted by the TFT of the present invention)
Next, the frequency characteristics of a ring oscillator manufactured by the present inventors using the TFT obtained in the present invention will be described. The ring oscillator is a circuit in which inverter circuits having a CMOS structure are connected in an odd-numbered stage ring shape, and is used to determine a delay time per one stage of the inverter circuit. The configuration of the ring oscillator used in the experiment is as follows. Number of steps: 9 Steps Thickness of gate insulating film of TFT: 30 nm and 50 nm Gate length of TFT: 0.6 μm

FIG. 5 shows the results of measuring the oscillation frequency of the ring oscillator at a power supply voltage of 5 V with a spectrum analyzer. In FIG. 5, the horizontal axis represents the power supply voltage (V _DD ) and the vertical axis represents the oscillation frequency (f _osc ). As shown in FIG. 5, an oscillation frequency of 1 GHz or more is realized when a TFT having a gate insulating film of 30 nm is used.

FIG. 6 shows an output spectrum of the spectrum analyzer when an oscillation frequency of 1.04 GHz is obtained. The horizontal axis indicates the frequency from 1 to 1.1 GHz, and the vertical axis indicates the voltage (output amplitude) measured on a log scale. As apparent from FIG. 6, a peak of the output spectrum appears at about 1.04 GHz. Note that the tail of the output spectrum is due to the resolution of the apparatus and does not affect the experimental results.

Further, a shift register, which is one of the TEGs of the LSI circuit, was actually manufactured, and the operating frequency was confirmed.
As a result, the thickness of the gate insulating film was 30 nm, and the gate length was 0.6 μm.
m, a power supply voltage of 5 V, and an output pulse having an operation frequency of 100 MHz was obtained in a shift register circuit having 50 stages.

The surprising data of the ring oscillator and the shift register as described above indicate that the TFT of the present invention has a performance comparable to or surpasses that of an IGFET using single crystal silicon.

The following data is available as evidence to support this. The data shown in FIG. 7 shows the power supply voltage (V _DD ) on the horizontal axis,
The vertical axis is a graph in which the delay time (τ _pd ) per stage of an inverter with F / O = 1 (fan-out ratio is 1) is taken (Innovation of logic LSI technology, Kenji Maeguchi et al., P108,
Science Forum Inc., 1995).

The various curves (indicated by dotted lines) in the figure are data obtained when IGFETs using single crystal silicon are manufactured according to various design rules, and indicate so-called scaling rules.

When the relationship between the delay time of the inverter and the power supply voltage obtained by using the above-described ring oscillator is applied to this figure, a curve shown by a solid line in FIG. 7 is obtained. It should be noted that the channel length is 0.6 μm and the thickness of the gate insulating film is 3 μm more than that of an inverter made of an IGFET having a channel length of 0.5 μm and a gate insulating film thickness (t _OX ) of 11 nm.
The point is that an inverter made of a 0 nm TFT has better performance.

This means that the TFT obtained by the present inventor has an IG
It clearly shows that it has better performance than FET. For example, even if the thickness of the gate insulating film constituting the TFT is set to be three times or more the thickness of the IGFET, the same or higher performance can be obtained. That is, the TFT of the present invention has the same characteristics as the IGFET having the operation performance.
It can be said that it has an excellent dielectric strength voltage.

At the same time, higher performance can be realized if the TFT of the present invention is miniaturized according to the scaling rule. For example, a ring oscillator of 0.2 μ
9 GHz according to the scaling rule
Is expected to be realized (operating frequency f
Is inversely proportional to the square of the channel length L).

As described above, the TFT of the present invention has extremely excellent characteristics, and a semiconductor circuit formed using the TFT has a completely new TFT capable of realizing a high-speed operation of 10 GHz or more.
It was confirmed to be FT.

[Knowledge on Relationship between TFT Characteristics and CGS] The excellent TFT characteristics and circuit characteristics as described above
This is largely due to the fact that a semiconductor thin film having continuity in a crystal lattice at a crystal grain boundary is used as an active layer of T. The reason is discussed below.

The continuity of the crystal lattice at the crystal grain boundaries is caused by the fact that the crystal grain boundaries are grain boundaries called “planar grain boundaries”. The definition of a planar grain boundary herein is:
`` Characterization of High-Efficiency Cast-Si Sola
r Cell Wafers by MBIC Measurement; Ryuichi Shimok
awa and Yutaka Hayashi, Japanese Journal of Applie
d Physics vol.27, No.5, pp.751-758, 1988 ”.

[0148] According to the above-mentioned article, the plane grain boundaries have a size of $ 11.
1} twin grain boundaries, {111} stacking faults, {221} twin grain boundaries, {221} twist grain boundaries, and the like. This planar grain boundary is characterized by being electrically inactive. That is,
Even though it is a crystal grain boundary, it does not function as a trap that hinders carrier movement, and thus can be regarded as substantially absent.

In particular, {111} twin grain boundaries are also called {3} corresponding grain boundaries, and {221} twin grain boundaries are also called # 9 corresponding grain boundaries. The Σ value is a parameter serving as a guideline indicating the degree of consistency of the corresponding grain boundaries, and it is known that the smaller the Σ value, the better the grain boundaries of consistency.

As a result of the applicant's detailed observation of the semiconductor thin film of the present invention by TEM, it was found that most of the crystal grain boundaries (90% or more,
(Typically 95% or more) is the corresponding grain boundary of Σ3, that is, 対 応 11
It was found to be 1｝ twin grain boundaries.

In a grain boundary formed between two crystal grains, when the plane orientation of both crystals is {110},
Assuming that the angle formed by the lattice fringes corresponding to the {111} plane is θ,
It is known that when θ = 70.5 °, the corresponding grain boundary becomes Σ3.

Therefore, in the crystal grain boundary shown in the TEM photograph of FIG. 1A, each lattice fringe of adjacent crystal grains is continuous at an angle of about 70 °, and this crystal grain boundary is {111} double. It can easily be inferred that it is a grain boundary.

When θ = 38.9 °, a corresponding grain boundary of Σ9 was found, but such other crystal grain boundaries also existed.

Such a corresponding grain boundary is formed only between crystal grains having the same plane orientation. That is, the semiconductor thin film of the present invention can form such a corresponding grain boundary over a wide range only because the plane orientation is substantially {110}. This feature is not possible with other polysilicon films having irregular surface orientations.

FIG. 25A shows a TEM photograph (dark field image) of the semiconductor thin film of the present invention at a magnification of 15,000. Although there are a region that looks white and a region that looks black, a portion that looks the same color indicates that the orientation is the same.

It should be noted that FIG. 25 (A) shows that in such a wide range of dark-field images, white-looking regions are continuously arranged at a considerable rate. This means that crystal grains having the same orientation exist with a certain degree of orientation, and adjacent crystal grains have almost the same orientation.

On the other hand, a conventional high-temperature polysilicon film is
FIG. 25B shows a TEM photograph (dark field image) magnified 1000 times.
Shown in In the conventional high-temperature polysilicon film, portions having the same plane orientation are only scattered, and a directional group as shown in FIG. 25A cannot be confirmed. This is probably because the orientation between adjacent crystal grains is completely irregular.

Further, the present applicant has repeated observation and measurement over many areas other than the measurement points shown in FIG.
It has been confirmed that the continuity of the crystal lattice at the crystal grain boundary is maintained in a wide area sufficient to produce the crystal.

[Embodiment 2] In Embodiment 1, an example in which a silicon film is used as a semiconductor film has been described, but Si _x Ge _1-x (0 <X
It is also effective to use a silicon film containing 1 to 10% of germanium as shown by <1, preferably 0.9 ≦ X ≦ 0.99).

When such a compound semiconductor film is used, N
The threshold voltage can be reduced when fabricating TFTs and P-type TFTs. In addition, the field-effect mobility (called mobility) can be increased.

[Embodiment 3] In the embodiment 1, since no impurity is intentionally added to the active layer, the channel forming region becomes intrinsic or substantially intrinsic. The term “substantially intrinsic” means that the activation energy of the silicon film is almost 1/2 (the Fermi level is located almost at the center of the forbidden body), that the impurity concentration is lower than the spin density, That no impurity is added.

However, the TFT of the present invention can use a known channel doping technique. The channel doping technique is a technique of adding an impurity to at least a channel formation region for controlling a threshold.

Since the present invention originally has a very small threshold value, the concentration for adding impurities may be very small. It is very preferable that a small amount of the additive be used because the threshold value can be controlled without lowering the carrier mobility.

[Embodiment 4] In this embodiment, a structure for obtaining the gettering effect by the phosphorus element in addition to the gettering effect by the halogen element shown in Embodiment 1 will be described. FIG. 10 is used for the description.

First, the process up to the gettering process using the halogen element is performed in accordance with the steps of the first embodiment to obtain the state shown in FIG. Next, a gate electrode 11 made of tantalum or a material mainly containing tantalum is formed.

Next, anodized film 12 is formed by anodizing the surface of gate electrode 11. The anodic oxide film 12 functions as a protective film. (FIG. 10A)

Next, gate insulating film 808 is etched by dry etching using gate electrode 11 as a mask. Then, in this state, the impurity regions 13 and 14 are formed by adding phosphorus or arsenic ions by ion implantation. (FIG. 10B)

Next, after forming a thick silicon nitride film, etch back is performed by dry etching to form a sidewall 15. Then, after forming the sidewalls 15, the source region 16 and the drain region 17 are formed by adding phosphorus or arsenic ions again. (FIG. 10
(C))

Note that the second phosphorus element is not added under the sidewall 15 for the second time, so that a pair of low-concentration impurity regions 18 containing the phosphorus element at a lower concentration than the source region and the drain region are formed. Below the gate electrode 11 is a channel forming region 19 to which intrinsic or substantially intrinsic or a small amount of impurity is added for controlling a threshold value.

When the state shown in FIG. 10C is obtained in this manner, the temperature at 450 to 650 ° C. (typically 600 ° C.) is 8 to 2 ° C.
Heat treatment is performed for 4 hours (typically 12 hours).

This heat treatment is a step for the purpose of gettering the catalyst element (nickel in this case) with the phosphorus element. At the same time, the activation of the impurities and the recovery of the ion-implanted damage to the active layer are performed. .

In this step, the nickel remaining in the channel formation region 19 is moved to the source / drain regions 16 and 17 by performing the heat treatment, gettered there and inactivated. That is, nickel remaining inside the channel formation region 19 can be removed.

Since the source / drain regions 16 and 17 function as electrodes if they have conductivity, there is no possibility that the presence or absence of nickel will affect the electrical characteristics. Therefore, it can function as a gettering site.

When the state shown in FIG. 10D is obtained as described above, the interlayer insulating film 20, the source electrode 21, and the drain electrode 22 are formed in the same manner as in Embodiment 1, and the thin film transistor shown in FIG. Is completed.

Although tantalum is used as the gate electrode in this embodiment, a crystalline silicon film having conductivity may be used. The method for forming the low-concentration impurity region is not limited to the method of this embodiment.

The most important structure in this embodiment is that gettering is performed by moving the catalyst element remaining in the channel formation region to the source region and the drain region. This is an invention which focuses on the gettering effect of a metal element by phosphorus or arsenic.

In this embodiment, an example of an N-type TFT has been described. However, in the case of a P-type TFT, since a gettering effect cannot be obtained only by a boron element, both a phosphorus element and a boron element are added to a source / drain region. Need to be added.

[Embodiment 5] In this embodiment, an example in which the present invention is applied to a thin film transistor having a structure different from that of Embodiment 1 will be described. FIG. 11 is used for the description.

First, a gate electrode 32 is formed on a quartz substrate 31. For the gate electrode 32, it is necessary to use an electrode having high heat resistance such as tantalum or silicon so as to withstand the subsequent thermal oxidation step.

Next, a gate insulating film 33 is formed so as to cover the gate electrode 32. An amorphous silicon film to be an active layer later is formed to a thickness of 50 nm thereon. Then, after forming a mask insulating film 35 having an opening as in the first embodiment, a nickel-containing layer 36 is formed. (FIG. 11
(A))

When the state shown in FIG. 11A is obtained, a heat treatment for crystallization is performed to obtain a crystalline silicon film 37 which is a lateral growth region. (FIG. 11B)

Next, the mask insulating film 35 is removed and heat treatment is performed in an atmosphere containing a halogen element. The conditions may be in accordance with the first embodiment. By this step, nickel is gettered from inside the crystalline silicon film 37 and is removed into the gas phase. (FIG. 11 (C))

After the gettering process is completed, the active layer 3 consisting of only the lateral growth region is formed by patterning.
8, and a channel stopper 39 made of a silicon nitride film is formed thereon. (FIG. 11D)

When the state of FIG. 11D is obtained, an N-type crystalline silicon film is formed and patterned to form a source region 40 and a drain region 41. further,
A source electrode 42 and a drain electrode 43 are formed.

Finally, the entire device is subjected to a heat treatment in a hydrogen atmosphere to complete an inverted staggered TFT having a structure as shown in FIG. Note that the structure shown in this embodiment is an example of an inverted staggered TFT, and is not limited to the structure of this embodiment. In addition, other bottom gate type TFT
It is also possible to apply to.

[Embodiment 6] In this embodiment, an example is shown in which a TFT according to the present invention is formed on a substrate having an insulating surface, and a pixel matrix circuit and peripheral circuits are monolithically constructed.
2 to 14. In this embodiment, a CMOS circuit which is a basic circuit is shown as an example of a peripheral circuit such as a driver circuit or a logic circuit.

First, a 75-nm-thick amorphous silicon film 52 and a mask insulating film 53 are formed on a quartz substrate 51, and a nickel-containing layer 54 is formed by spin coating. These steps are as described in the first embodiment. (FIG. 12 (A))

Next, after dehydrogenation at 450 ° C. for about 1 hour,
Perform heat treatment at 590 ° C for 8 hours in a nitrogen atmosphere.
The crystalline regions 55 to 58 are obtained. 55 and 56 are nickel added regions, and 57 and 58 are lateral growth regions.
(FIG. 12 (B))

After the heat treatment for crystallization is completed, the mask insulating film 53 is removed and patterning is performed, and an island-like semiconductor layer (active layer) 59 consisting only of the lateral growth regions 57 and 58 is formed.
To 61 are formed. (FIG. 12 (C))

Here, 59 is an active layer of an N-type TFT forming a CMOS circuit, and 60 is a P-type TFT forming a CMOS circuit.
An active layer of FT, 61 is an N which constitutes a pixel matrix circuit
It is an active layer of a type TFT (pixel TFT).

After forming the active layers 59 to 61, a gate insulating film 62 made of an insulating film containing silicon is formed thereon.
Then, a catalyst element gettering process is performed.
The conditions of this step may be in accordance with the first embodiment. (FIG. 12
(D))

Next, a metal film (not shown) containing aluminum as a main component is formed, and the gate electrode prototypes 63 to 65 are formed by patterning. 2 wt% in this embodiment
An aluminum film containing scandium is used.
(FIG. 13A)

Next, in the same manner as in Example 1, the porous anodic oxide films 66 to 68 were formed by the technique described in JP-A-7-135318.
Non-porous anodic oxide films 69-71, gate electrodes 72-74
To form (FIG. 13 (B))

After the state shown in FIG. 13B is obtained, the gate electrodes 72 to 74 and the porous anodic oxide film 6 are formed.
The gate insulating film 62 is etched using 6 to 68 as a mask. Then, the porous anodic oxide films 66 to 68 are removed to obtain the state shown in FIG. In FIG. 13C, reference numerals 75 to 77 denote the processed gate insulating films.

Next, an impurity ion for imparting N-type is added in two portions in the same procedure as in Example 1. First, the first doping is performed at a high accelerating voltage to form an n ⁻ region, and then the second doping is performed at a low accelerating voltage.
Form a ⁺ region.

Through the above steps, a source region 78, a drain region 79, a low-concentration impurity region 80, and a channel forming region 81 of an N-type TFT constituting a CMOS circuit are formed. In addition, a source region 82, a drain region 83, a low-concentration impurity region 84, and a channel forming region 85 of an N-type TFT constituting the pixel TFT are defined. (FIG. 13D)

Note that, in the state shown in FIG.
The active layer of the P-type TFT constituting the S circuit has the same configuration as the active layer of the N-type TFT.

Next, a resist mask 86 is provided to cover the N-type TFT, and an impurity ion for imparting P-type (boron is used in this embodiment) is added.

This step is also performed in two steps, similarly to the above-described impurity doping step. However, since it is necessary to invert the N-type to the P-type, the concentration of the B ion is about several times as high as the above-mentioned P ion addition concentration. (Boron) ions are added.

The P-type TF constituting the CMOS circuit in this manner
A source region 87, a drain region 88, a low concentration impurity region 89, and a channel forming region 90 of T are formed. (Figure 1
4 (A))

When the active layer is completed as described above, activation of impurity ions is performed by a combination of furnace annealing, laser annealing, lamp annealing and the like. At the same time, the damage of the active layer in the addition step is also repaired.

Next, a stacked film of a silicon oxide film and a silicon nitride film is formed as an interlayer insulating film 91, and after forming a contact hole, a source electrode 92 to 94, a drain electrode 95,
Forming 96 forms the state shown in FIG.

In this embodiment, since the drain electrode 96 of the pixel TFT is used as the lower electrode of the storage capacitor, it is processed into a shape corresponding to the lower electrode.

Next, a silicon nitride film 97 having a thickness of 10 to 50 nm is formed, and a capacitor electrode 9 for forming an auxiliary capacitor is formed thereon.
8 is formed to a thickness of 100 nm. In this embodiment, the capacitance electrode 9 is used.
A titanium film is used as 8, and an auxiliary capacitance is formed between the titanium film and the drain electrode 96.

The above-mentioned silicon nitride film 97 has a high relative dielectric constant and is therefore suitable as a dielectric. Further, as the capacitor electrode 98, an aluminum film, a chromium film, or the like may be used instead of the titanium film.

Since this embodiment is an example of manufacturing an active matrix substrate (TFT side substrate) of a reflection type liquid crystal display device, it is possible to freely use below a pixel electrode to be formed later unlike a transmission type ( You don't have to worry about the aperture ratio). Therefore, it is possible to form the auxiliary capacitance as described above.

Next, a second interlayer insulating film 99 made of an organic resin film is formed to a thickness of 0.5 to 3 μm. Then, a conductive film is formed on the interlayer insulating film 99, and the pixel electrode 100 is formed by patterning. Since this embodiment is a reflection type example, a material containing aluminum as a main component is used as a conductive film forming the pixel electrode 100, and the pixel electrode 100 has a function as a reflection film.

Next, the entire substrate was heated at 350 ° C. in a hydrogen atmosphere for 1 hour.
Dangling bonds (unpaired bonds) in the film (especially in the active layer) by heating the device for about 2 hours and hydrogenating the entire device
To compensate. Through the above steps, a CMOS circuit and a pixel matrix circuit can be manufactured over the same substrate.

[Embodiment 7] In this embodiment, an example in which a TFT structure different from that of Embodiment 6 is adopted will be described. First, FIG. 15A shows an example in which a sidewall is used in forming a low-concentration impurity region.

In this case, a nonporous anodic oxide film is formed in the state shown in FIG. 13A, and the gate insulating film is etched using the gate electrode and the anodic oxide film as a mask. In that state, impurities are added for forming the n ⁻ region and the p ⁻ region.

Next, the side walls 1001 to 1003
Is formed by an etch-back method, and then an impurity is added for forming an n ⁺ region and ap ⁺ region. In such a process, low-concentration impurity regions (n ⁻ region and p ⁻ region) are formed below the sidewalls 1001 to 1003.

In FIG. 15A, metal silicides 1004 to 1006 are formed using a known salicide technique. As a metal for silicidation, titanium, tantalum, tungsten, molybdenum, or the like can be used.

The structure shown in FIG. 15B is characterized in that gate electrodes 1007 to 1009 are formed of a crystalline silicon film having one conductivity. Normally, N-type conductivity is provided, but a dual-gate TFT in which conductivity differs between an N-type TFT and a P-type TFT can also be used.

Further, the salicide structure is applied to the structure shown in FIG. 15B, but in this case, the gate electrode 1
Metal silicide 1010 on the upper surface of 007-1009
1012 is formed.

The structure shown in this embodiment is designed so as to be suitable for a TFT having a high operation speed. Especially,
The salicide structure is a very effective technique for realizing an operating frequency on the order of several GHz.

[Embodiment 8] In this embodiment, an example in which an auxiliary capacitor is formed with a different configuration from that of Embodiment 6 will be described.

First, in FIG. 16A, a drain region 1020 of the active layer is formed large, and a part thereof is used as a lower electrode of an auxiliary capacitor. In this case, a gate insulating film 1021 is provided over the drain region 1020, and a capacitor electrode 1022 is formed thereover. This capacitance electrode 102
2 is formed of the same material as the gate electrode.

At this time, a portion of the drain region 1020 which forms an auxiliary capacitance may have conductivity by adding an impurity in advance, or may be formed by applying a constant voltage to the capacitance electrode 1022. Layers may be used.

FIG. 16A shows an example of a reflection type liquid crystal display device. Therefore, an auxiliary capacitance can be formed by making the most of the back side of the pixel electrode. Therefore, a very large capacity can be secured. Of course, the present invention can be applied to a transmissive liquid crystal display device. In this case, however, care must be taken because if the area occupied by the auxiliary capacitor is increased, the aperture ratio is reduced.

Next, FIG. 17B shows an example of a transmission type liquid crystal display device. In the configuration of FIG.
23 is a lower electrode of the storage capacitor, and the silicon nitride film 1
024, a black mask 1025 is formed, and an auxiliary capacitance is formed between the drain electrode 1023 and the black mask 1025.

As described above, the structure of FIG. 16B is characterized in that the black mask 1025 also serves as the upper electrode of the auxiliary capacitance.

Reference numeral 1026 denotes a pixel electrode, which is of a transmission type and uses a transparent conductive film (for example, an ITO film).

In the structure as shown in FIG. 16B, an aperture ratio can be increased by forming an auxiliary capacitor which easily occupies a large area on the TFT. Further, since a silicon nitride film having a high dielectric constant can be used with a thickness of about 25 nm, it is possible to secure a very large capacity with a small area.

[Embodiment 9] In this embodiment, the structure of a pixel TFT forming a pixel matrix circuit will be described.
FIG. 26A shows a cross-sectional structure of the pixel TFT of this embodiment. In FIG. 26A, reference numeral 3001 denotes an active layer;
Reference numeral 2 denotes a source line, 3003 denotes a gate line, 3004 denotes a drain electrode, 3005 denotes a black mask, and 3006 denotes a contact hole for connecting the drain electrode 3004 and the pixel electrode 3007.

This embodiment is characterized in that an auxiliary capacitance is formed between the drain electrode 3004 and the black mask 3005 above the pixel TFT.

FIG. 26B is a cross-sectional view of FIG. 26A taken along the broken line indicated by AA ′. Note that the same reference numerals are used in FIGS. 26A and 26B.

As described above, the drain electrode 3005 is formed so as to overlap the gate line 3003,
A storage capacitor is formed between the storage capacitor 8 and the black mask 3005 opposed to the storage capacitor 8. Note that in this embodiment, a three-layer structure in which a titanium film is interposed between aluminum films is used as the drain electrode 3005.

In this embodiment, after forming the drain electrode 3005, an interlayer insulating film having a three-layer structure of a silicon nitride film / a silicon oxide film / an acrylic film is formed, and a black mask 3005 is formed thereon.

At this time, before the formation of the black mask 3005, an opening is formed by removing only the acrylic film in a region to be a storage capacitor later. Then, only the silicon oxide film and the silicon nitride film remain at the bottom of the opening, and the insulating layer having the two-layer structure functions as the dielectric 3008 of the auxiliary capacitor.

[Embodiment 10] This embodiment shows an example in which a liquid crystal panel is constructed by utilizing the present invention. FIG. 17 is a simplified view of a cross section of an active matrix type liquid crystal panel. A CMOS circuit is shown in a region forming a driver circuit or a logic circuit, and a pixel TFT is shown in a region forming a pixel matrix circuit. I have.

Since the structure (TFT structure) of the CMOS circuit and the pixel matrix circuit has already been described in Examples 6 to 9, only the necessary parts will be described in this embodiment.

First, the state shown in FIG. 14C is obtained according to the manufacturing process shown in the sixth embodiment. It is to be noted that the change of the pixel TFT to have a multi-gate structure is at the discretion of the practitioner.

Then, an alignment film 1030 is formed in preparation for the active matrix substrate. Next, a counter substrate is prepared. The counter substrate includes a glass substrate 1031, a transparent conductive film 1032, and an alignment film 1033. Note that a black mask and a color filter are formed on the counter substrate side as necessary, but are omitted here.

The thus prepared active matrix substrate and the counter substrate are bonded by a known cell assembling process. Then, a liquid crystal material 1034 is sealed between the two substrates to complete a liquid crystal panel as shown in FIG.

The liquid crystal material 1034 has a liquid crystal operation mode (E
CB mode, guest host mode, etc.).

FIG. 18 shows a simplified appearance of an active matrix substrate as shown in FIG. In FIG. 18, reference numeral 1040 denotes a quartz substrate; 1041, a pixel matrix circuit; 1042, a source driver circuit;
43 is a gate driver circuit, and 1044 is a logic circuit.

The logic circuit 1044 is a TFT in a broad sense.
However, in order to distinguish them from circuits conventionally called pixel matrix circuits and driver circuits, other signal processing circuits (memory,
D / A converter, pulse generator, etc.).

An FPC (Flexible Print Circuit) terminal is attached as an external terminal to the liquid crystal panel thus formed. Generally, a liquid crystal panel is a liquid crystal panel with an FPC attached.

Applicants actually have a 2.6 inch diagonal, 1280 ×
A liquid crystal module with 1024 pixels and a pixel size of 45 μm × 32 μm is manufactured. The aperture ratio is 63% and the contrast ratio is
300: 1 is achieved.

[Embodiment 11] The present invention is not limited to the liquid crystal display device described in Embodiment 10, but may be applied to other electro-optical devices such as an active matrix type EL (electroluminescence) display device and EC (electrochromics) display device. It is also possible to make a device.

[Embodiment 12] In this embodiment, FIG. 19 shows an example of an electronic device (applied product) using an electro-optical device using the present invention. Examples of applied products using the present invention include a video camera, a still camera, a projector, a head-mounted display, a car navigation, a personal computer, and a portable information terminal (mobile computer, mobile phone, etc.).

FIG. 19A shows a mobile phone,
01, audio output unit 2002, audio input unit 2003, display device 2004, operation switch 2005, antenna 200
6. The present invention can be applied to the display device 2004.

FIG. 19B shows a video camera, which includes a main body 2101, a display device 2102, an audio input unit 2103, an operation switch 2104, a battery 2105, and an image receiving unit 21.
06. The present invention can be applied to the display device 2102.

FIG. 19C shows a mobile computer (mobile computer), which comprises a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, and a display device 2205. The present invention relates to a display device 220.
5 is applicable.

FIG. 19D shows a head mounted display, which comprises a main body 2301, a display device 2302, and a band 2303. The present invention can be applied to the display device 2302.

FIG. 19E shows a rear type projector, in which a main body 2401, a light source 2402, a display device 2403,
Polarizing beam splitter 2404, reflector 240
5, 2406 and a screen 2407. The invention can be applied to the display device 2403.

FIG. 19F shows a front type projector, which includes a main body 2501, a light source 2502, and a display device 250.
3. It comprises an optical system 2504 and a screen 2505. The invention can be applied to the display device 2503.

As described above, the applicable range of the present invention is extremely wide, and it can be applied to display media in all fields. Further, since the TFT of the present invention can also constitute a semiconductor circuit such as an IC or an LSI, any application is possible as long as the TFT requires such a semiconductor circuit.

[0249]

According to the invention disclosed in this specification, a semiconductor thin film having substantially the same crystallinity as a single crystal semiconductor can be realized. IGFETs (MOFETs) fabricated on a single crystal by using such a semiconductor thin film
(SFET) can be realized with a TFT having high performance comparable to or surpassing SFET.

A semiconductor circuit and an electro-optical device using the above-described TFT and an electronic device having the same have extremely high performance and are extremely excellent in functionality, portability and reliability. It will be.

[Brief description of the drawings]

FIG. 1 is an HR-TEM photograph in which a crystal grain boundary of a semiconductor thin film is enlarged.

FIG. 2 is a diagram schematically illustrating a crystal orientation relationship.

FIG. 3 is a photograph and a schematic diagram showing an electron beam diffraction pattern.

FIG. 4 is a graph showing electric characteristics of a thin film transistor.

FIG. 5 is a diagram illustrating frequency characteristics of a ring oscillator.

FIG. 6 is a photograph showing an output spectrum of a ring oscillator.

FIG. 7 is a diagram showing a scaling rule.

FIG. 8 illustrates a manufacturing process of a thin film transistor.

FIG. 9 illustrates a manufacturing process of a thin film transistor.

FIG. 10 illustrates a manufacturing process of a thin film transistor.

FIG. 11 illustrates a manufacturing process of a thin film transistor.

FIG. 12 illustrates a manufacturing process of an active matrix substrate.

FIG. 13 illustrates a manufacturing process of an active matrix substrate.

FIG. 14 illustrates a manufacturing process of an active matrix substrate.

FIG. 15 illustrates a structure of an active matrix substrate.

FIG. 16 illustrates a structure of an active matrix substrate.

FIG. 17 illustrates a cross section of a liquid crystal display device.

FIG. 18 is a diagram of the active matrix substrate as viewed from above.

FIG. 19 illustrates an example of an electronic device (applied product).

FIG. 20 is a diagram schematically showing a state of crystal growth.

FIG. 21 is a TEM photograph showing crystal grains of a crystalline silicon film.

FIG. 22 is a diagram illustrating a model related to generation and disappearance of a defect.

FIG. 23 is a diagram showing a concentration distribution of C, N, and O.

FIG. 24 is a view showing a result of X-ray diffraction.

FIG. 25 is a TEM photograph showing a dark field image of a semiconductor thin film.

FIG. 26 is a diagram showing an upper surface and a cross-sectional structure of a pixel TFT.

 ──────────────────────────────────────────────────続 き Continuing from the front page (72) Yasushi Ogata, 398 Hase, Hase, Atsugi, Kanagawa Prefecture Inside the Semi-Conductor Energy Laboratory Co., Ltd.

Claims (20)

[Claims] 1. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, the plane orientation being substantially {110} oriented, and the continuity of most crystal lattices at an arbitrary crystal grain boundary. A semiconductor thin film, comprising: 2. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the plane orientation is substantially {110} -oriented and lattice fringes observed so as to cross any crystal grain boundary. Most of which are linearly continuous between different crystal grains forming the crystal grain boundary. 3. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the {110} orientation ratio is 0.9 or more, and continuous at almost any crystal lattice at an arbitrary crystal grain boundary. A semiconductor thin film having properties. 4. A semiconductor thin film comprising an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the {110} orientation ratio is 0.9 or more and is observed so as to cross any crystal grain boundary. Most of the plaids
A semiconductor thin film characterized by being linearly continuous between different crystal grains forming the crystal grain boundary. 5. The semiconductor thin film according to claim 1, wherein specific regularity due to {110} orientation is observed in the electron diffraction pattern. 6. A plurality of rod-shaped or flat rod-shaped crystals, each of which is a crystal grown substantially along a <111> axis direction with a substantially {111} plane at the top. 4. The semiconductor thin film according to claim 1. 7. The semiconductor thin film according to claim 1, wherein the plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 8. The concentration of C, N, O, S present in the film is 5%.
2. The composition according to claim 1, wherein the density is less than × 10 ¹⁸ atoms / cm ^3.
The semiconductor thin film according to claim 4. 9. The film contains Ni, Co, Fe, Pd, Pt,
5. The semiconductor thin film according to claim 1, wherein one or more elements selected from Cu, Au, and Ge exist at a concentration of 5 × 10 ¹⁷ atoms / cm ³ or less. 10. The semiconductor thin film according to claim 1, comprising silicon or an element containing silicon as a main component. 11. An insulating gate type semiconductor device in which at least a channel forming region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the plane orientation of the semiconductor thin film is substantially {110} -oriented. And
A semiconductor device characterized in that almost any crystal lattice has continuity at an arbitrary crystal grain boundary. 12. An insulating gate type semiconductor device in which at least a channel forming region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein the plane orientation of the semiconductor thin film is substantially {110} -oriented. And
In addition, a semiconductor device is characterized in that most of the lattice fringes observed so as to cross any crystal grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. 13. An insulating gate type semiconductor device wherein at least a channel forming region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein said semiconductor thin film has a {110} orientation ratio of 0.1. 9. A semiconductor device, wherein the number is 9 or more and most crystal lattices have continuity at an arbitrary crystal grain boundary. 14. An insulating gate type semiconductor device in which at least a channel forming region is composed of a semiconductor thin film composed of an aggregate of a plurality of rod-shaped or flat rod-shaped crystals, wherein said semiconductor thin film has a {110} orientation ratio of 0.1. A semiconductor which is not less than 9 and most of the lattice fringes observed so as to cross any crystal grain boundary are linearly continuous between different crystal grains forming the crystal grain boundary. apparatus. 15. The semiconductor device according to claim 11, wherein specific regularity due to {110} orientation is observed in an electron diffraction pattern of the semiconductor thin film. 16. A plurality of rod-shaped or flat rod-shaped crystals, each of which is a crystal grown substantially along a <111> axis direction with a substantially {111} plane at the head.
The semiconductor device according to claim 1. 17. The semiconductor device according to claim 11, wherein the plurality of rod-shaped or flat rod-shaped crystals are arranged substantially parallel to each other with a specific direction. 18. C, N, O, S present in a semiconductor thin film
The semiconductor device according to claim 11, wherein the concentration of is less than 5 × 10 ¹⁸ atoms / cm ³ . 19. A semiconductor thin film comprising Ni, Co, Fe, P
15. The method according to claim 11, wherein one or more elements selected from d, Pt, Cu, Au, and Ge are present at a concentration of 5 × 10 ¹⁷ atoms / cm ³ or less. Semiconductor device. 20. The semiconductor device according to claim 11, wherein the semiconductor thin film is made of silicon or an element containing silicon as a main component.