JPH11345845A - Semiconductor device manufacturing method and semiconductor test apparatus - Google Patents

Abstract

(57) Abstract: A process for forming a plurality of chips on a wafer that requires a high-frequency terminal and a DC terminal (DC signal terminal and DC power supply terminal) as terminals used for a test in a wafer state. With regard to the method of manufacturing a semiconductor device having a high frequency terminal, the high frequency probe head does not hinder the use of the DC probe even when the high frequency terminals are arranged in the chip and the required number of DC terminals are arranged. So that a sufficient test can be performed for each chip. A high-frequency terminal used for testing a chip is provided.
13 are arranged in the chip 2, and the DC terminals 15 to 34 used for the test of the chip 2 are collectively arranged in the DC terminal formation region 14 remote from the chip 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming a plurality of chips on a wafer which require a high-frequency terminal and a DC terminal (DC signal terminal and DC power supply terminal) as terminals used for a test in a wafer state. The present invention relates to a method of manufacturing a semiconductor device having a step of performing the same, and a semiconductor test apparatus used in the method of manufacturing a semiconductor device.

[0002]

2. Description of the Related Art Conventionally, in the case of a chip requiring a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state, for example, a communication chip, a high-frequency terminal and a DC terminals were arranged.

[0003]

In such a chip, a high-frequency probe head is used for a high-frequency terminal and a direct-current probe is used for a direct-current terminal during a test in a wafer state. In order to prevent the high frequency probe head from obstructing the use of the DC probe,
It may be necessary to limit the number of DC terminals,
There was a problem that a sufficient test could not be performed for each chip.

Since the position of the high-frequency terminal affects the high-frequency characteristics, the high-frequency terminal must be arranged at a predetermined position in the chip. However, the direct-current terminal does not affect the high-frequency characteristics. Since there is no provision, there is a great degree of freedom in the arrangement position.

SUMMARY OF THE INVENTION In view of the above, the present invention relates to a method of manufacturing a semiconductor device including a step of forming, on a wafer, a plurality of chips that require a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state. Therefore, even if the high-frequency terminals are arranged in the chip and the necessary number of DC terminals are arranged, the high-frequency probe head will not interfere with the use of the DC probe, It is a first object of the present invention to provide a method of manufacturing a semiconductor device capable of performing a complicated test.

Further, the present invention is a semiconductor test apparatus having a high frequency probe head and a direct current probe for testing a plurality of chips formed on a wafer chip by chip. However, it is necessary to move each chip to another chip each time it is tested, but if the DC probe needs to be kept in contact with a fixed position outside the chip formation area until testing of all chips is completed, it is sufficient. A second object of the present invention is to provide a semiconductor test apparatus which can be used and can be simplified in configuration as a semiconductor test apparatus used in such a case.

[0007]

SUMMARY OF THE INVENTION A first aspect of the present invention is an invention of a method of manufacturing a semiconductor device, and requires a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state. Forming a plurality of chips on a wafer, and testing the plurality of chips formed on the wafer for each chip.
DC terminals used for testing each chip are arranged collectively for each chip in a region away from each chip.

According to the first aspect, the DC terminals used for testing each chip are arranged collectively for each chip in a region away from each chip, so that the high-frequency terminals are provided in each chip. Even if the arrangement and the required number of DC terminals are arranged, the high frequency probe head does not hinder the use of the DC probe.

In a second aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of chips which require high-frequency terminals and DC terminals as terminals used for a test in a wafer state are mounted on a wafer. In a method of manufacturing a semiconductor device having a step of forming a plurality of chips and a step of testing a plurality of chips formed on a wafer one chip at a time, DC terminals used for testing each chip are arranged in another chip. It is to do.

According to the second aspect, the DC terminals used for testing each chip are arranged in another chip. Therefore, the high-frequency terminals are arranged in each chip, and the required number of terminals are arranged. High frequency probe /
The head does not hinder the use of the DC probe.

In a third aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of chips requiring a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state are mounted on a wafer. In a method of manufacturing a semiconductor device having a step of forming a plurality of chips and a step of testing a plurality of chips formed on a wafer one chip at a time, DC terminals used for testing each chip are arranged in each chip. Is electrically connected to each of a plurality of chips.

According to the third aspect of the present invention, the DC terminals used for testing each chip are arranged in each chip and are electrically connected to each of a plurality of chips. The DC probe only needs to be brought into contact with the DC terminal of the non-test target chip that is electrically connected to the DC terminal of the test target chip. Therefore, even if the high-frequency terminals are arranged in each chip and the necessary number of DC terminals are arranged, the high-frequency probe head does not hinder the use of the DC probes.

According to a fourth aspect of the present invention, there is provided a method of manufacturing a semiconductor device, wherein a plurality of chips each requiring a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state are mounted on the wafer. In a method of manufacturing a semiconductor device having a step of forming a plurality of chips and a step of testing a plurality of chips formed on a wafer one chip at a time, DC terminals used for testing each chip are shared by all chips. The DC terminals are arranged outside the chip forming area.

According to the fourth aspect of the present invention, the DC terminals used for testing each chip are arranged outside the chip forming area as DC terminals shared by all the chips. The high frequency probe head does not hinder the use of the DC probe even if the DC terminals are arranged within the DC probe.

According to a fifth aspect of the present invention, there is provided a semiconductor testing apparatus, comprising a high frequency probe head and a DC probe, for testing a plurality of chips formed on a wafer one chip at a time. In the semiconductor test apparatus, the high frequency probe head is movably held so as to be able to contact a predetermined position of each chip, and the direct current probe can be brought into contact with a fixed position outside the chip forming area. As described above.

For example, when testing each chip formed on a wafer according to the fourth invention one chip at a time, it is necessary to move the high frequency probe head to another chip each time each chip is tested. It is not necessary to move the DC probe every time each chip is tested; it is sufficient to place it in a fixed position until testing of all chips is completed, and a mechanism to move the DC probe to the position of all chips is required And not. The fifth invention can be used when testing each chip of such a wafer.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The first to fourth embodiments of the method of manufacturing a semiconductor device according to the present invention and an embodiment of a semiconductor test apparatus according to the present invention will be described below with reference to FIGS. I do.

FIG. 1 is a view for explaining a first embodiment (an embodiment of the first invention) of a method for manufacturing a semiconductor device according to the present invention. 3 is a schematic plan view showing a part of a wafer surface on which chips are formed.

In FIG. 1, 1 is a wafer, 2 is a communication chip formed on the wafer 1, and 3 to 13 are high frequency terminals used for testing the chip 2, 3, 5, 6, 8, 10 , 1
1, 13 are ground terminals, and 4, 7, 9, and 12 are signal terminals.

Reference numeral 14 denotes a DC terminal forming area provided corresponding to the chip 2, and reference numerals 15 to 34 denote DC terminals used for testing the chip 2.

Reference numerals 35 to 37 denote high frequency probe heads arranged on the wafer 1 corresponding to the high frequency terminals 3 to 13 for testing the chip 2.

That is, in the first embodiment of the method of manufacturing a semiconductor device according to the present invention, DC terminals used for testing each chip are collectively arranged in a region apart from each chip. For example, the DC terminals 15 to 34 used for the test of the chip 2 are collectively arranged in the DC terminal formation region 14 remote from the chip 2.

Therefore, even if the high-frequency terminals 3 to 13 used for testing the chip 2 are arranged in the chip 2 and the DC terminals 15 to 34 required for the test of the chip 2 are arranged, Since the high frequency probe heads 35 to 37 do not hinder the use of the DC probe, the chip 2
Can be sufficiently tested.

Second Embodiment of Method of Manufacturing Semiconductor Device of the Present Invention FIG. 2 FIG. 2 illustrates a second embodiment of the method of manufacturing a semiconductor device of the present invention (an embodiment of the second invention). 3 is a schematic plan view showing a part of a wafer surface on which chips are formed.

In FIG. 2, reference numeral 38 denotes a wafer; 39 to 41, communication chips formed on the wafer 38; and 42 to 52, high frequency terminals used for testing the chip 40;
4, 45, 47, 49, 50 and 52 are ground terminals,
3, 46, 48 and 51 are signal terminals.

Reference numerals 53 to 63 denote high frequency terminals used for testing the chip 41, and reference numerals 53, 55, 56, 58,
60, 61, 63 are ground terminals, 54, 57, 59, 6
2 is a signal terminal.

Reference numerals 64 to 76 denote DC terminals used for testing the chip 39, and reference numerals 77 to 89 denote DC terminals used for testing the chip 40.

Numerals 90 to 92 correspond to the high frequency terminals 42 to 52 for testing the chip 40.
8 is a high-frequency probe head disposed on

That is, in the second embodiment of the method of manufacturing a semiconductor device according to the present invention, a DC terminal used for testing each chip is arranged in another chip. DC terminals 77 to 89 used for
Are arranged in the adjacent chip 41.

Therefore, the high-frequency terminals 42 to 52 used for testing the chip 40 are arranged in the chip 40 and the DC terminals 77 to 8 required for the test of the chip 40 are provided.
Even when the chip 9 is arranged in the chip 41, the chip 40 can be sufficiently tested because the high-frequency probe heads 90 to 92 do not hinder the use of the DC probe when the chip 40 is tested. it can.

Third Embodiment of the Method of Manufacturing a Semiconductor Device of the Present Invention FIG. 3 FIG. 3 illustrates a third embodiment of the method of manufacturing a semiconductor device of the present invention (an embodiment of the third invention). 3 is a schematic plan view showing a part of a wafer surface on which chips are formed.

In FIG. 3, 94 is a wafer, 95 and 96 are communication chips formed on the wafer 94, and 97 to 107 are high frequency terminals used for testing the chip 95.
99, 100, 102, 104, 105 and 107 are ground terminals, and 98, 101, 103 and 106 are signal terminals.

Reference numerals 108 to 118 denote high frequency terminals used for testing the chip 96.
1, 113, 115, 116 and 118 are ground terminals,
09, 112, 114 and 117 are signal terminals.

Reference numerals 119 and 120 denote DC terminals used for testing the chip 95. Reference numerals 121 and 122 denote DC terminals used for testing the chip 96.
121 is connected by a wiring 123,
Reference numeral 22 is connected by a wiring 124.

Further, 125 to 127 are high frequency probe heads arranged on the wafer 94 for testing the chip 95, and 128 and 129 are direct current probes arranged on the wafer 94 for testing the chip 95. It is.

That is, in the third embodiment of the method of manufacturing a semiconductor device according to the present invention, DC terminals used for testing each chip are arranged in each chip and electrically connected to each of a plurality of chips. For example, the DC terminal 119 disposed in the chip 95 and the DC terminal 121 disposed in the chip 96 are connected by a wiring 123, and the DC terminal 120 disposed in the chip 95 and the DC terminal 120 disposed in the chip 96. The DC terminal 122 is connected by a wiring 124.

As a result, when testing the chip 95,
The direct current probe 128 can be electrically connected to the direct current terminal 119 via the wiring 123 by contacting the direct current terminal 121 with the direct current terminal 121.
Is connected to the DC terminal 122 so that the wiring 12
4 can be electrically connected to the DC terminal 120.

Therefore, the high-frequency terminals 97 to 107 used for testing the chip 95 are arranged in the chip 95, and the necessary number of DC terminals 119 and 120 are connected to the chip 95.
When the chip 95 is tested, the probe heads 125 to 127 for high frequency use
Since the use of the chip 29 is not hindered, the chip 95 can be sufficiently tested.

Fourth Embodiment of the Method of Manufacturing a Semiconductor Device of the Present Invention FIG. 4 FIG. 4 illustrates a fourth embodiment (an embodiment of the fourth invention) of a method of manufacturing a semiconductor device of the present invention. 4 is a schematic plan view. In FIG. 4, reference numeral 131 denotes a wafer, and 132 denotes a chip forming area in which a plurality of communication chips are formed.

Reference numeral 133 denotes a DC terminal forming area in which DC terminals shared by all chips formed in the chip forming area 132 are formed. Note that the chip formation region 13
In each chip formed in No. 2, a high-frequency terminal used for testing each chip is arranged.

As described above, in the fourth embodiment of the method of manufacturing a semiconductor device according to the present invention, the DC terminals used for testing each chip are outside the chip forming region 132 as DC terminals shared by all chips. DC terminal formation region 133
It is said to be placed in.

Therefore, even if the high-frequency terminals used for testing each chip are arranged in each chip, and the number of DC terminals necessary for testing each chip is arranged, the high-frequency Since it does not hinder the use of the probe, sufficient testing can be performed for each chip, and the number of DC terminals per chip can be reduced. it can.

One Embodiment of the Semiconductor Test Apparatus of the Present Invention
FIG. 5 is a schematic front view showing a main part of an embodiment of the semiconductor test apparatus of the present invention. In FIG. 5, reference numeral 134 denotes a stage for holding the wafer 131 shown in FIG. The head 136 is a high-frequency probe head holding member that movably holds the high-frequency signal probe head 135 so that it can contact the high-frequency terminal of each chip.

Reference numeral 137 denotes a DC probe, and 138 denotes a DC probe holding member for holding the DC probe 137 in a fixed position so as to be able to contact the DC terminal in the DC terminal forming region 133.

For example, when testing each chip formed on the wafer 131 shown in FIG. 4 one chip at a time, it is necessary to move the high frequency probe head to the next chip every time each chip is tested. It is not necessary to move the DC probe every time each chip is tested, and it suffices that the DC probe be brought into contact with the DC terminals in the DC terminal formation region 133 until the testing of all chips is completed.

One embodiment of the semiconductor test apparatus of the present invention is as follows.
It can be used when testing each chip formed on the wafer 131 as shown in FIG. 4 one chip at a time, and a mechanism for moving the DC probe 137 to the next chip every time each chip is tested. Therefore, the configuration of the semiconductor test apparatus for testing the wafer 131 as shown in FIG. 4 can be simplified.

[0047]

According to the first aspect of the present invention, according to the first aspect of the present invention, a DC terminal used for testing each chip is provided in an area away from each chip. Since the high-frequency terminals are arranged in each chip, and the necessary number of DC terminals are arranged in each chip, the high-frequency probe head will not interfere with the use of DC probes even if the required number of DC terminals are arranged. Therefore, sufficient testing can be performed for each chip.

According to the second aspect of the present invention, according to the second aspect of the present invention, the DC terminal used for testing each chip is arranged in another chip. High-frequency terminals are placed in each chip, and even if the required number of DC terminals are
Since the head does not hinder the use of the DC probe, a sufficient test can be performed for each chip.

According to the third aspect of the present invention, according to the third aspect of the present invention, DC terminals used for testing each chip are arranged in each chip, and a plurality of chips are provided for each chip. The high-frequency probe head is placed in each chip, and even if the required number of DC terminals are placed, the high-frequency probe head may interfere with the use of the DC probe. Therefore, sufficient testing can be performed for each chip.

According to the fourth aspect of the present invention, according to the fourth aspect of the present invention, a DC terminal used for testing each chip is a DC terminal shared by all chips. Since the high-frequency terminals are placed inside each chip, and the required number of direct-current terminals are arranged, the high-frequency probe head will not interfere with the use of the direct-current probe. Therefore, a sufficient test can be performed for each chip, and the number of DC terminals per chip can be reduced, so that the chip can be reduced in size.

According to a fifth aspect of the present invention, a high frequency probe head is required to be moved to another chip every time each chip is tested. The probe can be used when it is sufficient that the probe is kept in contact with a fixed position outside the chip forming area until the test of all chips is completed. Can be planned.

[Brief description of the drawings]

FIG. 1 is a schematic plan view for explaining a first embodiment of a method for manufacturing a semiconductor device of the present invention.

FIG. 2 is a schematic plan view for explaining a second embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 3 is a schematic plan view for explaining a third embodiment of the method for manufacturing a semiconductor device according to the present invention.

FIG. 4 is a schematic plan view for explaining a fourth embodiment of a method for manufacturing a semiconductor device according to the present invention.

FIG. 5 is a schematic front view showing a main part of one embodiment of the semiconductor test apparatus of the present invention.

[Explanation of symbols]

 (Fig. 1) 3 to 13 High frequency terminal 15 to 34 DC terminal (Fig. 2) 42 to 63 High frequency terminal 64 to 89 DC terminal (Fig. 3) 97 to 118 High frequency terminal 119 to 122 DC terminal

Claims (5)

[Claims] 1. A step of forming, on a wafer, a plurality of chips that require high-frequency terminals and DC terminals as terminals to be used for a test in a wafer state, and forming the chips on the wafer into one chip A DC terminal used for testing each chip, wherein the DC terminals used for testing each chip are collectively arranged for each chip in a region apart from each chip. Production method. 2. A step of forming, on a wafer, a plurality of chips requiring high-frequency terminals and DC terminals as terminals to be used in a test in a wafer state, and connecting the plurality of chips formed on the wafer to one chip A method of manufacturing a semiconductor device, comprising: performing a test for each chip; wherein a DC terminal used for testing each chip is arranged in another chip. 3. A step of forming a plurality of chips on a wafer which require a high-frequency terminal and a DC terminal as terminals to be used for a test in a wafer state, and combining the plurality of chips formed on the wafer into one chip A method of manufacturing a semiconductor device having a step of testing each chip, wherein a DC terminal used for testing each chip is arranged in each chip and electrically connected to each of a plurality of chips. Device manufacturing method. 4. A step of forming, on a wafer, a plurality of chips that require a high-frequency terminal and a DC terminal as terminals used for a test in a wafer state; and forming the plurality of chips formed on the wafer into one chip. A method of manufacturing a semiconductor device having a step of testing each chip, wherein a DC terminal used for testing each chip is arranged outside a chip forming region as a DC terminal shared by all chips. Device manufacturing method. 5. A semiconductor test apparatus having a high-frequency probe head and a direct-current probe, and tests a plurality of chips formed on a wafer chip by chip. A semiconductor, wherein the semiconductor device is held movably so that it can be brought into contact with a predetermined position, and the DC probe is held at a fixed position so that it can be brought into contact with a fixed position outside a chip forming region. Testing equipment.