JPH11340367A - Multilayer wiring board and method of manufacturing the same - Google Patents
Multilayer wiring board and method of manufacturing the sameInfo
- Publication number
- JPH11340367A JPH11340367A JP10149381A JP14938198A JPH11340367A JP H11340367 A JPH11340367 A JP H11340367A JP 10149381 A JP10149381 A JP 10149381A JP 14938198 A JP14938198 A JP 14938198A JP H11340367 A JPH11340367 A JP H11340367A
- Authority
- JP
- Japan
- Prior art keywords
- wiring circuit
- circuit layer
- wiring board
- insulating
- wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
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Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【課題】フリップチップ実装に好適な微細な回路形成が
可能であり、また、コネクタや金具類、電池等の部材を
接続したり、大電流を印加することも可能な種々の配線
回路層を備えた多層配線基板を提供する。
【解決手段】少なくとも熱硬化性樹脂を含む絶縁材料か
らなる絶縁層２ａ〜２ｄを積層してなる絶縁基板２と、
絶縁基板２の表面および／または内部に形成された配線
回路層３と、配線回路層３間を電気的に接続するための
ビアホール導体４を具備する多層配線基板１において、
少なくとも１つの絶縁層２ａ〜２ｄ内に、金属箔等から
なる厚さの異なる複数の配線回路層３ａ〜３ｄを形成す
るとともに、それらの配線回路層３のうち、少なくとも
絶縁基板２表面に形成された配線回路層３ａ、３ｂ、３
ｃは絶縁基板２表面に埋設し、その断面形状が埋設側の
辺が露出側の辺よりも長い略逆台形形状とする。
(57) [Summary] A variety of circuits capable of forming a fine circuit suitable for flip chip mounting, connecting members such as connectors, metal fittings, batteries, and applying a large current. The present invention provides a multilayer wiring board provided with the above wiring circuit layer. An insulating substrate (2) formed by laminating insulating layers (2a to 2d) made of an insulating material containing at least a thermosetting resin;
In the multilayer wiring board 1 including the wiring circuit layer 3 formed on the surface and / or inside of the insulating substrate 2 and the via-hole conductor 4 for electrically connecting between the wiring circuit layers 3,
A plurality of wiring circuit layers 3a to 3d having different thicknesses made of metal foil or the like are formed in at least one of the insulating layers 2a to 2d, and at least one of the wiring circuit layers 3 is formed on the surface of the insulating substrate 2. Wiring circuit layers 3a, 3b, 3
c is buried in the surface of the insulating substrate 2 and has a substantially inverted trapezoidal cross section whose buried side is longer than the exposed side.
Description
【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION
【０００１】[0001]
【発明の属する技術分野】本発明は、有機樹脂を含有す
る絶縁基板に対して複数層の配線回路層が形成され、半
導体素子搭載用基板等に適した多層配線基板および多層
配線基板の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board having a plurality of wiring circuit layers formed on an insulating substrate containing an organic resin and suitable for a substrate for mounting a semiconductor element, and a method for manufacturing a multilayer wiring board. It is about.
【０００２】[0002]
【従来技術】電子機器は常に小型化を求める傾向にある
が、近年携帯情報端末の発達や、コンピューターを持ち
運んで操作する、いわゆるモバイルコンピューティング
の普及によってさらに小型、薄型、軽量化が要求されて
いる。2. Description of the Related Art In recent years, there has been a demand for miniaturization of electronic devices. However, in recent years, with the development of portable information terminals and the spread of so-called mobile computing in which a computer is carried and operated, a further reduction in size, thickness, and weight is required. I have.
【０００３】携帯情報端末やコンピューターの小型化の
ためには半導体の実装方法の変更が特に有効である。従
来から、ワイヤーボンディング法と呼ばれる金線やアル
ミニウム線を使用してシリコンチップと配線基板とを接
続する従来法に代えて、最近では、配線基板に直接シリ
コンチップを接続するフリップチップが多用されつつあ
り、これにより、半導体素子を搭載した配線基板の薄型
化が可能になるだけでなく、高周波信号を取扱う半導体
素子に対しても適した構造となるために、コンピュータ
の性能を大幅に向上させることができる。For miniaturization of portable information terminals and computers, it is particularly effective to change the semiconductor mounting method. In recent years, instead of the conventional method of connecting a silicon chip to a wiring board using a gold wire or an aluminum wire, which is called a wire bonding method, flip chips for directly connecting a silicon chip to a wiring board have been increasingly used. Yes, this not only makes it possible to reduce the thickness of the wiring board on which the semiconductor elements are mounted, but also makes the structure suitable for semiconductor elements that handle high-frequency signals. Can be.
【０００４】一方、半導体素子を実装する配線基板とし
て、セラミックスや熱硬化性樹脂を絶縁基板とし、メタ
ライズ配線回路層や、金属箔からなる配線回路層を形成
したものが知られ、最近では、高密度配線化のために、
配線回路層を多層に形成した、いわゆる多層配線基板が
多用されている。On the other hand, as a wiring board on which a semiconductor element is mounted, there is known a wiring board formed by using a ceramics or thermosetting resin as an insulating substrate and forming a metallized wiring circuit layer or a wiring circuit layer made of metal foil. For high density wiring,
A so-called multilayer wiring board in which wiring circuit layers are formed in multiple layers is often used.
【０００５】その中で、セラミック基板は、硬くて脆い
性質を有することから、欠けや割れ等が発生しやすく、
また焼成による収縮によって変形や寸法のばらつきなど
のが発生しやすく、平坦度が要求されるフリップチップ
に十分に対応できないことから、熱硬化性樹脂を含有す
る絶縁基板を用いた高密度多層配線化が望まれている。[0005] Among them, the ceramic substrate is hard and brittle, so that chipping and cracking are liable to occur.
Deformation and dimensional variation are likely to occur due to shrinkage due to firing, and it is not possible to respond sufficiently to flip chips that require flatness, so high-density multilayer wiring using an insulating substrate containing thermosetting resin Is desired.
【０００６】熱硬化性樹脂を含有する絶縁基板を用いた
配線基板としては、一般には、銅箔などの金属箔を絶縁
基板上に貼り、次いで金属箔の不要部分をエッチング除
去して配線回路層が形成されており、さらには、配線基
板に貫通孔を形成し、その孔の内壁に金属メッキを施し
たスルーホール導体を形成することにより表裏間の配線
回路層を接続する構造が知られている。As a wiring board using an insulating board containing a thermosetting resin, generally, a metal foil such as a copper foil is stuck on the insulating board, and then unnecessary portions of the metal foil are removed by etching. In addition, a structure is known in which a through-hole is formed in a wiring board, and a through-hole conductor plated with metal is formed on the inner wall of the hole to connect a wiring circuit layer between the front and back surfaces. I have.
【０００７】[0007]
【発明が解決しようとする課題】フリップチップ実装を
行なうためには、実装される配線基板側の配線密度を高
めることが必要であるが、ＩＣチップにおける配線は
０．２μｍ以下にまで微細となる一方、配線基板では未
だ５０μｍ程度の配線が一般的であり、最近になって、
そのような高性能ＩＣチップの性能向上に適合し得るた
めに、配線幅が５０μｍ以下、特に３０μｍ以下の線幅
の配線の形成が可能な多層配線基板の開発が現在、続け
られている。In order to perform flip-chip mounting, it is necessary to increase the wiring density on the wiring board side on which the chip is mounted. However, the wiring in an IC chip is as fine as 0.2 μm or less. On the other hand, wiring of about 50 μm is still common in wiring boards, and recently,
In order to be able to adapt to the performance improvement of such a high-performance IC chip, the development of a multilayer wiring board capable of forming a wiring having a wiring width of 50 μm or less, particularly 30 μm or less is currently being continued.
【０００８】線幅が３０μｍ以下の配線回路層を銅箔な
どの金属箔によって形成する場合、用いる金属箔の厚み
が１０μｍ以下と薄く、金属の結晶粒子が小さく、さら
にはマット面（絶縁層との接触側面）の表面粗さが小さ
いことが望まれる。これは、金属箔側面のエッチング
（サイドエッチング) をできるだけ小さくし、また、結
晶面によるエッチングの異方性の影響を無くし、さらに
は、前記接触側の表面粗さが大きいと突起部分が、金属
箔のエッチング時に十分に除去されず、回路の間に残留
することを防ぐためである。When the wiring circuit layer having a line width of 30 μm or less is formed of a metal foil such as a copper foil, the thickness of the metal foil used is as thin as 10 μm or less, the crystal grains of the metal are small, and the matte surface (the insulating layer and the It is desired that the surface roughness of the contact side surface is small. This minimizes the etching (side etching) on the side surface of the metal foil, eliminates the influence of the anisotropy of the etching due to the crystal plane, and furthermore, if the surface roughness on the contact side is large, the protruding portion may cause This is to prevent the foil from being removed sufficiently during etching and remaining between circuits.
【０００９】ところが、上記のように、金属箔の厚みが
薄く、且つ結晶粒径が小さく、さらにマット面（粗化
面) の表面粗さを小さくすると、必然的に金属箔の絶縁
層に対する接着強度が低くなる。このため、金属箔から
なる配線回路層の一部にコネクタなどの金具を取り付け
る場合、その取付部分において金属箔が絶縁層から剥が
れる等の問題が生じることから、このような金属箔は厚
いことが望まれる。However, as described above, when the thickness of the metal foil is small, the crystal grain size is small, and the surface roughness of the mat surface (roughened surface) is reduced, the adhesion of the metal foil to the insulating layer is inevitable. Strength is reduced. For this reason, when attaching a bracket such as a connector to a part of the wiring circuit layer made of a metal foil, there is a problem that the metal foil is peeled off from the insulating layer at the attachment portion. desired.
【００１０】また、最近では、モーター等駆動回路の制
御系やバッテリーの制御系等において、大電流を流す場
合があり、このような回路においては、配線回路層の厚
みを厚くすることが必要とされる。Recently, a large current may flow in a control system of a drive circuit such as a motor or a control system of a battery. In such a circuit, it is necessary to increase the thickness of a wiring circuit layer. Is done.
【００１１】しかし、従来の金属箔を用いた配線基板に
おいては、まず、絶縁基板の全面に一枚の銅箔を張り合
わせ、樹脂を硬化させた後にエッチングして配線回路層
を形成するために、絶縁基板の同一平面内において、単
一の金属箔の配線回路層しか形成できないために、上記
のような要求を満たすためには、配線回路層の機能に応
じて個別の配線基板を作製する必要があり、その結果、
全体としての回路基板が大型化してしまうという問題が
あった。However, in a conventional wiring board using a metal foil, first, a single piece of copper foil is adhered to the entire surface of the insulating substrate, the resin is cured, and then etched to form a wiring circuit layer. Since only a single metal foil wiring circuit layer can be formed on the same plane of the insulating substrate, it is necessary to manufacture individual wiring substrates according to the function of the wiring circuit layer to meet the above requirements And as a result,
There is a problem that the circuit board as a whole becomes large.
【００１２】従って、本発明は、微細な回路形成、特に
フリップチップ実装が可能であり、また、コネクタや金
具類、電池等の部材を接続したり、大電流を印加するこ
とも可能な種々の配線回路層を備えた多層配線基板を提
供することを目的とするものである。また、本発明は、
上記種々の配線回路層を容易に作製することのできる多
層配線基板の製造方法を提供することを目的とするもの
である。Therefore, the present invention enables various circuits capable of forming a fine circuit, especially flip-chip mounting, and connecting members such as connectors, metal fittings, and batteries, and applying a large current. It is an object of the present invention to provide a multilayer wiring board having a wiring circuit layer. Also, the present invention
It is an object of the present invention to provide a method for manufacturing a multilayer wiring board in which the various wiring circuit layers can be easily manufactured.
【００１３】[0013]
【課題を解決するための手段】本発明者は、回路の高密
度配線化と、配線回路層の絶縁層への密着性を高めるた
めの改善について検討を重ねた結果、複数層の配線回路
層を具備する多層配線基板において、同一平面内の配線
回路層に、厚さの異なる複数種の配線回路層を設けるこ
とにより、半導体素子のフリップチップ実装に適した配
線回路層や、コネクタなどの部材を接続した場合におい
ても優れた密着性を有する配線回路層、あるいは大電流
を流すこともできる配線回路層などを具備し、高密度に
回路設計が可能な配線基板が得られることを見いだし、
本発明に至った。The inventor of the present invention has repeatedly studied a high-density wiring of a circuit and an improvement for improving the adhesion of the wiring circuit layer to the insulating layer. By providing a plurality of types of wiring circuit layers having different thicknesses on a wiring circuit layer in the same plane on a multilayer wiring substrate having a wiring circuit layer suitable for flip-chip mounting of a semiconductor element, a member such as a connector, etc. It is found that a wiring board that has a wiring circuit layer having excellent adhesion even when it is connected, or a wiring circuit layer that can flow a large current, etc., and that can be designed with high density circuit can be obtained.
The present invention has been reached.
【００１４】即ち、本発明の多層配線基板は、少なくと
も熱硬化性樹脂を含む絶縁材料からなる絶縁層を積層し
てなる絶縁基板と、該絶縁基板の表面および／または内
部に形成された配線回路層と、前記配線回路層間を電気
的に接続するためのビアホール導体を具備する多層配線
基板において、少なくとも１層の絶縁層内に、厚さの異
なる複数の配線回路層が形成されてなることを特徴とす
るものである。That is, the multilayer wiring board of the present invention comprises an insulating substrate formed by laminating insulating layers made of an insulating material containing at least a thermosetting resin, and a wiring circuit formed on the surface and / or inside the insulating substrate. In a multilayer wiring board including a layer and a via-hole conductor for electrically connecting the wiring circuit layers, a plurality of wiring circuit layers having different thicknesses are formed in at least one insulating layer. It is a feature.
【００１５】また、上記配線基板においては、前記厚さ
の異なる複数の配線回路層が、前記絶縁基板の表面およ
び／または前記絶縁基板の内部に形成されてなるもので
ある。In the above-mentioned wiring board, the plurality of wiring circuit layers having different thicknesses are formed on the surface of the insulating substrate and / or inside the insulating substrate.
【００１６】なお、前記配線回路層は金属箔からなるこ
とが望ましく、また配線回路層の厚みは、半導体素子ま
たは半導体素子が収納されたパッケージが実装される配
線回路層は１８μｍ以下、金具取り付け部、コネクタ取
り付け部、他の基板の金具との接触部となる配線回路層
が１２μｍ以上、１０Ａ以上の大電流が印加される配線
回路層が３５μｍ以上の厚さを有していることがそれぞ
れ望ましい。Preferably, the wiring circuit layer is made of metal foil, and the thickness of the wiring circuit layer is 18 μm or less for a semiconductor element or a wiring circuit layer on which a package containing a semiconductor element is mounted. It is preferable that the wiring circuit layer serving as a connector mounting portion or a contact portion with a metal fitting of another substrate has a thickness of 35 μm or more to which a large current of 12 μm or more and 10 A or more is applied. .
【００１７】また、配線回路層の密着性を高める上で、
前記配線回路層が、前記絶縁基板表面に埋設されている
とともに、配線回路層の断面形状が、埋設側の辺が露出
側の辺よりも長い略逆台形形状からなることが望まし
い。In order to enhance the adhesion of the wiring circuit layer,
It is preferable that the wiring circuit layer is buried on the surface of the insulating substrate, and that a cross-sectional shape of the wiring circuit layer has a substantially inverted trapezoidal shape in which a buried side is longer than an exposed side.
【００１８】また、本発明の上記多層配線基板の製造方
法としては、複数の転写シートの表面に、それぞれ厚さ
の異なる複数の配線回路層を形成する工程と、少なくと
も熱硬化性樹脂を含む未硬化または半硬化状態の絶縁シ
ートの表面に、前記転写シートの配線回路層を順次、加
圧転写させる工程と、前記絶縁シートを前記熱硬化性樹
脂が完全硬化するに十分な温度で加熱する工程とを具備
することを特徴とするものであって、前記配線回路層が
金属箔からなることが望ましい。The method of manufacturing a multilayer wiring board according to the present invention includes a step of forming a plurality of wiring circuit layers having different thicknesses on the surfaces of a plurality of transfer sheets, and a method including at least a thermosetting resin. A step of sequentially transferring the wiring circuit layer of the transfer sheet to the surface of the cured or semi-cured insulating sheet under pressure, and a step of heating the insulating sheet at a temperature sufficient to completely cure the thermosetting resin. Wherein the wiring circuit layer is preferably made of metal foil.
【００１９】また、密着性向上のために、前記転写シー
トの表面の配線回路層が、転写シート全面に形成された
金属層をエッチング処理して断面形状が台形状を有し、
且つ表面が平均表面粗さ２００ｎｍ以上に粗化処理され
てなることが望ましい。Further, in order to improve the adhesion, the wiring circuit layer on the surface of the transfer sheet has a trapezoidal cross section by etching a metal layer formed on the entire surface of the transfer sheet,
Moreover, it is desirable that the surface is roughened to an average surface roughness of 200 nm or more.
【００２０】[0020]
【発明の実施の形態】本発明の多層配線基板の概略断面
図を図１に示した。図１によれば、本発明の多層配線基
板１は、少なくとも熱硬化性樹脂を含む絶縁材料からな
る絶縁層２ａ〜２ｄを積層してなる絶縁基板２の表面、
あるいはその内部に配線回路層３が被着形成されてい
る。また、絶縁基板２の内部には、異なる層の配線回路
層間を接続するためにビアホール導体４が設けられてい
る。FIG. 1 is a schematic sectional view of a multilayer wiring board according to the present invention. According to FIG. 1, a multilayer wiring board 1 of the present invention has a surface of an insulating substrate 2 formed by laminating insulating layers 2a to 2d made of an insulating material containing at least a thermosetting resin.
Alternatively, the wiring circuit layer 3 is formed on the inside thereof. In addition, via-hole conductors 4 are provided inside the insulating substrate 2 to connect different wiring circuit layers.
【００２１】本発明においては、図１に示すように、同
一平面内に形成された配線回路層３において、少なくと
も１つの同一平面内に、厚さの異なる複数の配線回路層
３ａ，３ｂ、３ｃ、３ｄが形成されてなることが大きな
特徴である。本発明によれば、この厚さの異なる複数の
配線回路層３ａ〜３ｄは、いずれも銅、銀、アルミニウ
ム等の金属又は金属箔、特に金属箔からなることが望ま
しい。In the present invention, as shown in FIG. 1, a plurality of wiring circuit layers 3a, 3b, 3c having different thicknesses are formed on at least one same plane in a wiring circuit layer 3 formed on the same plane. The main feature is that 3d is formed. According to the present invention, it is desirable that each of the plurality of wiring circuit layers 3a to 3d having a different thickness be made of a metal such as copper, silver, or aluminum or a metal foil, particularly a metal foil.
【００２２】例えば、図１の配線基板においては、４種
類の厚みの配線回路層３ａ，３ｂ，３ｃ、３ｄ（厚みは
３ａ＜３ｂ＜３ｃ＜３ｄの順）が形成されており、かか
る配線回路層３ａ〜３ｄは、その機能に応じて使い分け
られている。For example, in the wiring board of FIG. 1, wiring circuit layers 3a, 3b, 3c and 3d having four kinds of thicknesses (thicknesses in the order of 3a <3b <3c <3d) are formed. The layers 3a to 3d are properly used according to their functions.
【００２３】具体的には、図１に示すように、半導体素
子５をフリップチップ実装する配線回路層３としては、
厚みが薄く高密度配線パターン化されることが要求され
るために、最も厚みの薄い配線回路層３ａによって形成
する。この半導体素子５または半導体素子５が収納され
たパッケージが実装される配線回路層３ａの厚みは１８
μｍ以下、特に１２μｍ以下、最適には９〜１２μｍで
あることが望ましい。Specifically, as shown in FIG. 1, the wiring circuit layer 3 on which the semiconductor element 5 is flip-chip mounted includes:
Since it is required to form a thin and high-density wiring pattern, it is formed by the thinnest wiring circuit layer 3a. The thickness of the wiring element layer 3a on which the semiconductor element 5 or the package containing the semiconductor element 5 is mounted is 18
It is desirable that it is not more than 12 μm, especially not more than 12 μm, most preferably 9 to 12 μm.
【００２４】この厚みが１８μｍを超えると、半導体素
子または半導体素子が収納されたパッケージとの接続に
必要な微細配線が得られないからである。If the thickness exceeds 18 μm, fine wiring required for connection with a semiconductor element or a package containing the semiconductor element cannot be obtained.
【００２５】また、金具６などの部材をロウ付けなどに
より取り付ける部分には、強度が要求されるために比較
的厚さの大きい配線回路層３ｃによって形成する。この
金具取り付け部、コネクタ取り付け部、他の基板の金具
との接触部となる配線回路層３ｃの厚みは１２μｍ以
上、特に１８μｍ以上の厚さを有していることが望まし
い。この厚みが１２μｍよりも薄いと、十分なピール強
度が得られないからである。Further, a portion to which a member such as the metal fitting 6 is attached by brazing or the like is formed of the wiring circuit layer 3c having a relatively large thickness because of the required strength. It is desirable that the thickness of the wiring circuit layer 3c serving as a contact portion with the metal fitting mounting portion, the connector mounting portion, and the metal fitting of another substrate has a thickness of 12 μm or more, particularly 18 μm or more. If the thickness is smaller than 12 μm, sufficient peel strength cannot be obtained.
【００２６】さらに、大電流が流される場合、配線回路
層の厚みは厚いことが要求され、例えば、絶縁基板２内
の配線回路層３においては、配線回路層３ｄによって形
成される。特に、１０Ａ以上の大電流が印加される配線
回路層３ｄの厚さは３５μｍ以上、特に５０μｍ以上で
あることが望ましい。但し、５０μｍよりも厚くなる場
合には、この配線回路層を積層によって絶縁基板２内部
に設けると、積層時の配線回路層の隅に空隙が形成され
る場合があり、積層不良を来す虞があるため、配線回路
層形成部の絶縁基板を一部切り取ることが望ましい。Further, when a large current flows, the wiring circuit layer is required to have a large thickness. For example, the wiring circuit layer 3 in the insulating substrate 2 is formed by the wiring circuit layer 3d. In particular, the thickness of the wiring circuit layer 3d to which a large current of 10 A or more is applied is desirably 35 μm or more, particularly preferably 50 μm or more. However, when the wiring circuit layer is thicker than 50 μm, if this wiring circuit layer is provided inside the insulating substrate 2 by lamination, voids may be formed at the corners of the wiring circuit layer at the time of lamination, which may result in lamination failure. Therefore, it is desirable to partially cut out the insulating substrate in the wiring circuit layer forming portion.
【００２７】なお、上記のような特殊な機能が要求され
る配線回路層以外の一般的な配線回路層は配線回路層３
ｂによって形成される。この一般的な配線回路層３ｂの
厚さは、１５〜２５μｍが適当である。A general wiring circuit layer other than the wiring circuit layer requiring the special function as described above is a wiring circuit layer 3.
b. An appropriate thickness of the general wiring circuit layer 3b is 15 to 25 μm.
【００２８】また、本発明によれば、図１に示すよう
に、絶縁基板２の表面に形成された配線回路層３ａ、３
ｂ、３ｃは、その厚さに拘らず、いずれの配線回路層も
絶縁基板２の表面に埋設されており、その断面形状は、
図２に示すように、埋設側の辺ｗ１が露出側の辺ｗ２よ
りも長い略逆台形形状からなる。また、基板内部の配線
回路層も同様な断面形状からなることが望ましい。According to the present invention, as shown in FIG. 1, the wiring circuit layers 3a, 3a formed on the surface of the insulating substrate 2 are formed.
Regarding b and 3c, any wiring circuit layer is buried in the surface of the insulating substrate 2 irrespective of its thickness.
As shown in FIG. 2, the buried side w1 has a substantially inverted trapezoidal shape longer than the exposed side w2. Further, it is desirable that the wiring circuit layer inside the substrate also has a similar cross-sectional shape.
【００２９】そして、この略逆台形形状の上辺と横辺と
の形成角θが４５°〜８０°、特に、５０°〜７５°の
鋭角を形成していることが望ましい。上記形成角θが８
０°より大きいと配線側面を粗化するのが困難となり絶
縁基板２と表面の配線回路層３の密着強度が低下する
他、後述の転写シート上の回路パターンをプリプレグに
圧着する際、埋設するのが難しくなり、４５°より小さ
いと絶縁基板２と表面の配線回路層３との密着力が不足
する恐れがあるためである。It is desirable that the formation angle θ between the upper side and the horizontal side of the substantially inverted trapezoidal shape forms an acute angle of 45 ° to 80 °, particularly 50 ° to 75 °. The formation angle θ is 8
If it is larger than 0 °, it is difficult to roughen the wiring side surface, and the adhesion strength between the insulating substrate 2 and the wiring circuit layer 3 on the surface is reduced. In addition, when a circuit pattern on a transfer sheet to be described later is crimped to a prepreg, it is embedded. This is because if the angle is smaller than 45 °, the adhesion between the insulating substrate 2 and the wiring circuit layer 3 on the surface may be insufficient.
【００３０】また、配線回路層３のうち、少なくとも基
板表面に形成される配線回路層は、図２に示すように、
絶縁基板２と接触する面が、２００ｎｍ以上、特に４０
０ｎｍ以上の表面粗さ（Ｒａ）に粗面化されていること
が望ましく、このように粗面化することにより絶縁基板
２と間のアンカーリングによって配線回路層３の絶縁基
板２への密着性を高めることができる。なお、上記表面
粗さが２００ｎｍより小さいと絶縁基板２と配線回路層
３との密着強度が不足する恐れがあり、特に、図１にお
いて、金具取り付け部、コネクタ取り付け部、他の基板
の金具との接触部となる配線回路層３ｃにおいては、金
具、コネクタ等の配線基板への取り付け信頼性を損ねる
虞がある。Further, among the wiring circuit layers 3, at least the wiring circuit layers formed on the substrate surface are as shown in FIG.
The surface in contact with the insulating substrate 2 is 200 nm or more, particularly 40 nm
It is desirable that the surface is roughened to have a surface roughness (Ra) of 0 nm or more, and by such roughening, the adhesion of the wiring circuit layer 3 to the insulating substrate 2 is achieved by anchoring between the insulating substrate 2 and the substrate. Can be increased. If the surface roughness is smaller than 200 nm, the adhesion strength between the insulating substrate 2 and the wiring circuit layer 3 may be insufficient. In particular, in FIG. In the wiring circuit layer 3c serving as a contact portion, there is a possibility that the reliability of attachment of a metal fitting, a connector, or the like to a wiring board may be impaired.
【００３１】図１に示したような本発明の配線基板にお
いては、絶縁基板２は、少なくとも熱硬化性樹脂を含有
するものであるが、含有される熱硬化性樹脂としては、
絶縁材料としての電気的特性、耐熱性、および機械的強
度を有する熱硬化性樹脂であれば特に限定されるもので
なく、例えば、アラミド樹脂、フェノール樹脂、エポキ
シ樹脂、イミド樹脂、フッ素樹脂、フェニレンエーテル
樹脂、ビスマイレイドトリアジン樹脂、ユリア樹脂、メ
ラミン樹脂、シリコーン樹脂、ウレタン樹脂、不飽和ポ
リエステル樹脂、アリル樹脂等が、単独またはそれらの
２種以上の組み合わせ等によって構成される。In the wiring board of the present invention as shown in FIG. 1, the insulating substrate 2 contains at least a thermosetting resin.
It is not particularly limited as long as it is a thermosetting resin having electrical properties, heat resistance, and mechanical strength as an insulating material. For example, aramid resin, phenol resin, epoxy resin, imide resin, fluorine resin, phenylene An ether resin, a bismaleide triazine resin, a urea resin, a melamine resin, a silicone resin, a urethane resin, an unsaturated polyester resin, an allyl resin, or the like may be used alone or in combination of two or more thereof.
【００３２】また、上記の絶縁基板２中には、絶縁基板
あるいは配線基板全体の強度を高めるために、前記有機
樹脂に対してフィラーを複合化させることもできる。有
機樹脂と複合化されるフィラーとしては、ＳｉＯ2 、Ａ
ｌ2 Ｏ3 、ＺｒＯ2 、ＴｉＯ2 、ＡｌＮ、ＳｉＣ、Ｂａ
ＴｉＯ3 、ＳｒＴｉＯ3 、ゼオライト、ＣａＴｉＯ3、
ほう酸アルミニウム等の無機質フィラーが好適に用いら
れる。また、ガラスやアラミド樹脂からなる不織布、織
布などに上記樹脂を含浸させて用いてもよい。In the insulating substrate 2, a filler may be compounded with the organic resin in order to increase the strength of the entire insulating substrate or wiring substrate. As the filler to be combined with the organic resin, SiO 2 , A
l 2 O 3 , ZrO 2 , TiO 2 , AlN, SiC, Ba
TiO 3 , SrTiO 3 , zeolite, CaTiO 3 ,
An inorganic filler such as aluminum borate is preferably used. Further, a nonwoven fabric or a woven fabric made of glass or aramid resin may be used by impregnating the above resin.
【００３３】有機樹脂とフィラーとは、体積比率で３
０：７０〜７０：３０の比率で複合化されるのが適当で
ある。The organic resin and the filler have a volume ratio of 3
It is appropriate that the composite is formed in a ratio of 0:70 to 70:30.
【００３４】また、配線回路層間を接続するビアホール
導体４は、銅粉末、銀粉末、銀被覆銅粉末、銅銀合金な
どの、平均粒径が０．５〜５０μｍの金属粉末を充填し
て形成されたものであることが望ましい。このような金
属粉末の充填によれば、後述する通り、ビアホール導体
を任意の層間に形成することができるために、高密度配
線化を図る上で非常に有効である。The via-hole conductor 4 connecting the wiring circuit layers is formed by filling a metal powder having an average particle size of 0.5 to 50 μm, such as copper powder, silver powder, silver-coated copper powder, and copper-silver alloy. It is desirable that it is done. According to such filling of the metal powder, as will be described later, a via-hole conductor can be formed between any layers, which is very effective in achieving high-density wiring.
【００３５】また、配線回路層３は、銅、アルミニウ
ム、金、銀の群から選ばれる少なくとも１種、または２
種以上の合金からなることが望ましく、特に、銅、また
は銅を含む合金が最も望ましい。また、場合によって
は、導体組成物として回路の抵抗調整のためにＮｉ−Ｃ
ｒ合金などの高抵抗の金属を混合、または合金化しても
よい。The wiring circuit layer 3 is made of at least one selected from the group consisting of copper, aluminum, gold, and silver;
It is desirable to be composed of more than one kind of alloy, and particularly copper or an alloy containing copper is most desirable. In some cases, the conductor composition may be Ni-C
A high resistance metal such as an r alloy may be mixed or alloyed.
【００３６】上記ビアホール導体および配線回路層に
は、低抵抗化のために、前記低抵抗金属よりも低融点の
金属、例えば、半田、錫などの低融点金属を導体組成物
中の金属成分中に７０重量％以下の割合で含んでもよ
い。In the via-hole conductor and the wiring circuit layer, a metal having a lower melting point than the low-resistance metal, for example, a low-melting metal such as solder or tin is added to the metal component in the conductor composition to reduce the resistance. To 70% by weight or less.
【００３７】なお、本発明の多層配線基板によれば、必
要に応じて、上記のようにして作製された配線基板の表
面に、さらに微細で高密度の配線回路層を形成すること
を目的として、例えば、この配線基板をコア基板とし、
その表面にビルドアップ法により感光性樹脂からなる絶
縁層と、メッキなどの薄膜形成法により形成された配線
回路層やビアホール導体を順次積層して、高密度の配線
基板を作製することもできる。According to the multilayer wiring board of the present invention, if necessary, a finer and higher-density wiring circuit layer is formed on the surface of the wiring board manufactured as described above. For example, this wiring board is used as a core board,
An insulating layer made of a photosensitive resin by a build-up method, and a wiring circuit layer and a via-hole conductor formed by a thin-film forming method such as plating can be sequentially laminated on the surface to produce a high-density wiring board.
【００３８】次に、本発明の多層配線基板の製造工程を
図面をもとに説明する。図３は、本発明の多層配線基板
の製造工程を説明するための図である。Next, the manufacturing process of the multilayer wiring board of the present invention will be described with reference to the drawings. FIG. 3 is a diagram for explaining a manufacturing process of the multilayer wiring board of the present invention.
【００３９】図３によれば、まず、図３（ａ）に示すよ
うに、熱硬化性樹脂を含む未硬化または軟質（Ｂステー
ジ状態）の第１の絶縁シート１１を作製する。また、こ
の絶縁シート１１には、図３（ｂ）に示すように、所望
により厚み方向に貫通するスルーホール１２を形成し、
そのスルーホール内に前述したような金属粉末と、適宜
有機樹脂、ビヒクル等を添加し混合した導体ペーストを
スクリーン印刷や吸引処理しながら充填して、ビアホー
ル導体１３を形成する。According to FIG. 3, first, as shown in FIG. 3A, an uncured or soft (B-stage) first insulating sheet 11 containing a thermosetting resin is prepared. In addition, as shown in FIG. 3B, a through hole 12 is formed in the insulating sheet 11 so as to penetrate in the thickness direction as desired.
The via-hole conductor 13 is formed by filling the through-hole with a conductive paste obtained by adding and mixing the above-described metal powder, an organic resin, a vehicle, and the like as appropriate, while performing screen printing or suction processing.
【００４０】次に、全面に所定の厚さｔ1 を有する金属
箔を接着した転写シートを、フォトレジストなどの方法
で加工して、図３（ｃ）に示すような、配線回路層１５
ａを表面に形成した転写シート１６ａを作製する。Next, a transfer sheet having a metal foil having a predetermined thickness t 1 adhered to the entire surface is processed by a method such as a photoresist to form a wiring circuit layer 15 as shown in FIG.
A transfer sheet 16a having a formed on the surface is prepared.
【００４１】そして、図３（ｄ）に示すように、絶縁シ
ート１１に配線回路層１５ａが対面するように転写シー
ト１６ａを積層し、圧力１０〜５００ｋｇ／ｃｍ2 程度
の圧力で印加して、絶縁シート１１の表面に配線回路層
１５ａを埋設させた後、図３（ｅ）に示すように、転写
シート１６ａを剥離することにより、配線回路層１５ａ
を絶縁シート１１に転写させる。Then, as shown in FIG. 3 (d), a transfer sheet 16a is laminated on the insulating sheet 11 so that the wiring circuit layer 15a faces, and a pressure of about 10 to 500 kg / cm 2 is applied. After the wiring circuit layer 15a is embedded on the surface of the insulating sheet 11, the transfer sheet 16a is peeled off as shown in FIG.
Is transferred to the insulating sheet 11.
【００４２】次に、図３（ｃ）〜図３（ｅ）と同様に、
厚さｔ2 の金属箔を加工して、配線回路層１５ｂを表面
に形成した転写シートを作製し、これを前記配線回路層
１５ａが形成された絶縁シート１１に積層、圧力印加
後、転写シートを剥離して、絶縁シート１１の表面に配
線回路層１５ｂを転写させる。Next, as in FIGS. 3 (c) to 3 (e),
And processing the metal foil having a thickness of t 2, the wiring circuit layer 15b to prepare a transfer sheet formed on the surface, laminating it to the insulating sheet 11, wherein the wiring circuit layer 15a is formed, after the pressure applied, the transfer sheet Then, the wiring circuit layer 15b is transferred to the surface of the insulating sheet 11.
【００４３】この図３（ｃ）〜（ｅ）の工程を、必要に
応じ繰り返し、図３（ｆ）に示すような絶縁シート１１
の表面に、厚みの異なる複数種の配線回路層１５ａ、１
５ｂ、１５ｃを形成することができる。The steps shown in FIGS. 3 (c) to 3 (e) are repeated as necessary, and the insulating sheet 11 shown in FIG.
A plurality of types of wiring circuit layers 15a, 1
5b and 15c can be formed.
【００４４】そして、上記図３（ａ）〜図３（ｅ）の工
程と同様にして、また、必要に応じして厚さの異なる複
数種の配線回路層１５ａ，１５ｂ，１５ｃを形成した、
複数の絶縁シート１７、１８を積層圧着する。Then, a plurality of types of wiring circuit layers 15a, 15b, and 15c having different thicknesses were formed in the same manner as in the steps of FIGS.
A plurality of insulating sheets 17 and 18 are laminated and pressed.
【００４５】その後、この積層物を絶縁シート中の熱硬
化性樹脂が硬化するに十分な温度に加熱して一括して完
全硬化させることにより、本発明の多層配線基板を形成
することができる。Thereafter, the laminate is heated to a temperature sufficient to cure the thermosetting resin in the insulating sheet and is completely cured at a time, whereby the multilayer wiring board of the present invention can be formed.
【００４６】なお、上記の製造方法において、用いられ
る熱硬化性樹脂を含有する絶縁シートは、前述した熱硬
化性有機樹脂、または熱硬化性有機樹脂とフィラーなど
の組成物を混練機や３本ロールなどの手段によって十分
に混合し、これを圧延法、押し出し法、射出法、ドクタ
ーブレード法などによってシート状に成形する。また、
所望により熱処理して熱硬化性樹脂を半硬化させる。半
硬化には、樹脂が完全硬化するに十分な温度よりもやや
低い温度に加熱する。In the above-mentioned production method, the insulating sheet containing the thermosetting resin to be used may be a thermosetting organic resin or a composition of the thermosetting organic resin and a filler, such as a kneading machine or a three-piece type. The mixture is sufficiently mixed by means of a roll or the like, and is formed into a sheet by a rolling method, an extrusion method, an injection method, a doctor blade method, or the like. Also,
The thermosetting resin is semi-cured by heat treatment if desired. For semi-curing, the resin is heated to a temperature slightly lower than a temperature sufficient to completely cure the resin.
【００４７】また、絶縁シートへのスルーホール（ビア
ホール）の形成は、ドリル、パンチング、サンドブラス
ト、あるいは炭酸ガスレーザ、ＹＡＧレーザ、及びエキ
シマレーザ等の照射による加工など公知の方法が採用さ
れる。これらの絶縁シートは、前述した種々の絶縁材料
の中でも、パンチング又はレーザーによる加工の容易性
の点から、エポキシ樹脂、イミド樹脂およびフェニレン
エーテル樹脂のうちの少なくとも１種と、シリカ、ガラ
ス繊維およびアラミド不織布のうちの少なくとも１種と
の複合体からなることが最も望ましい。For forming a through hole (via hole) in the insulating sheet, a known method such as drilling, punching, sandblasting, or processing by irradiation with a carbon dioxide laser, a YAG laser, an excimer laser, or the like is employed. These insulating sheets are made of at least one of epoxy resin, imide resin and phenylene ether resin, silica, glass fiber and aramid from the viewpoint of ease of processing by punching or laser among the various insulating materials described above. Most desirably, it comprises a composite with at least one of the nonwoven fabrics.
【００４８】上記の製造方法によれば、絶縁シート１１
の表面に転写する配線回路層１５ａ、１５ｂ，１５ｃの
断面形状を前記図２に示したように所定の略台形形状と
することにより、配線回路層１５を絶縁シート１１表面
に圧接した際に、絶縁シート１１における配線回路層１
５の周辺部の変形が抑制される結果、その圧力が配線回
路層１５の略逆台形の横辺、底辺にわたって、絶縁シー
トと圧接される結果、配線回路層１５の断面が矩形（長
方形）の場合に比較して、配線回路層１５の絶縁シート
１１への密着性を大幅に向上させることができる。According to the above manufacturing method, the insulating sheet 11
By making the cross-sectional shape of the wiring circuit layers 15a, 15b, and 15c transferred to the surface of the substrate into a predetermined substantially trapezoidal shape as shown in FIG. Wiring circuit layer 1 in insulating sheet 11
As a result, deformation of the peripheral portion of the wiring circuit 5 is suppressed, and the pressure is pressed against the insulating sheet over the substantially inverted trapezoidal side and bottom sides of the wiring circuit layer 15, so that the cross section of the wiring circuit layer 15 is rectangular (rectangular). Compared with the case, the adhesion of the wiring circuit layer 15 to the insulating sheet 11 can be greatly improved.
【００４９】転写シート表面に形成される配線回路層の
断面を前述したような略台形形状、特に形成角θが４５
°〜８０°の略台形形状とするには、例えば、転写シー
ト表面に張りつけた金属箔の表面に回路パターンのレジ
スト層を付設した後、エッチング法により非レジスト領
域をエッチング除去する際に、エッチング速度を２〜５
０μｍ／分にすればよい。The cross section of the wiring circuit layer formed on the surface of the transfer sheet has a substantially trapezoidal shape as described above, and particularly, the formation angle θ is 45.
In order to form a substantially trapezoidal shape of about 80 ° to 80 °, for example, after a resist layer of a circuit pattern is attached to the surface of a metal foil attached to the transfer sheet surface, etching is performed when etching a non-resist area by etching. Speed 2-5
It may be 0 μm / min.
【００５０】また、本発明によれば、絶縁シート１１に
転写される配線回路層１５の絶縁シート１１側の表面粗
さを２００ｎｍ以上とするには、転写シート表面に形成
された配線回路層１５の表面を、例えばギ酸あるいはＮ
ａＣｌＯ2 、ＮａＯＨ、Ｎａ3 ＰＯ4 の混合液等で表面
処理する。この表面粗さは、粗化速度で制御でき、１μ
ｍ／分以上の粗化速度で良好に粗化できる。According to the present invention, in order to set the surface roughness of the wiring circuit layer 15 transferred to the insulating sheet 11 on the insulating sheet 11 side to 200 nm or more, the wiring circuit layer 15 formed on the transfer sheet surface is required. The surface of for example with formic acid or N
The surface is treated with a mixed solution of aClO 2 , NaOH, Na 3 PO 4 or the like. The surface roughness can be controlled by the roughening speed,
It can be satisfactorily roughened at a roughening rate of m / min or more.
【００５１】[0051]
【実施例】（１）ガラス繊維の織布にポリフェニレンエ
ーテルを含浸して作製した１００μｍのプリプレグに、
炭酸ガスレーザーで直径０．１ｍｍのビアホールを形成
し、そのホール内に銀をメッキした銅粉末（平均粒径６
μｍ）を含む銅ペーストを充填してビアホール導体を形
成した。EXAMPLES (1) A 100 μm prepreg prepared by impregnating a woven glass fiber fabric with polyphenylene ether was used.
A via hole having a diameter of 0.1 mm is formed with a carbon dioxide laser, and silver is plated in the via hole.
μm) to form a via-hole conductor.
【００５２】（２）一方、ポリエチレンテレフタレート
（ＰＥＴ）樹脂からなる転写シートの表面に接着剤を塗
布し、厚さ９μｍ、表面粗さ０．６μｍの銅箔を一面に
接着した。そして、フォトレジスト（ドライフィルム）
を塗布し露光現像を行った後、これを塩化第二鉄溶液中
に浸漬して非パターン部をエッチング除去して配線回路
層を形成した。なお、作製した配線回路層は、線幅が２
０μｍ、配線と配線との間隔が２０μｍの微細なパター
ンである。(2) On the other hand, an adhesive was applied to the surface of a transfer sheet made of polyethylene terephthalate (PET) resin, and a copper foil having a thickness of 9 μm and a surface roughness of 0.6 μm was adhered to one surface. And photoresist (dry film)
Was applied and exposed and developed, and then immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. The manufactured wiring circuit layer has a line width of 2
This is a fine pattern having a thickness of 0 μm and a distance between wirings of 20 μm.
【００５３】（３）また、ポリエチレンテレフタレート
（ＰＥＴ）樹脂からなる別の転写シートの表面に接着剤
を塗布し、厚さ１８μｍ、表面粗さ０．８μｍの銅箔を
一面に接着した。そして、フォトレジスト（ドライフィ
ルム）を塗布し露光現像を行った後、これを塩化第二鉄
溶液中に浸漬して非パターン部をエッチング除去して配
線回路層を形成した。なお、作製した配線回路層は、線
幅が５０μｍ、配線と配線との間隔が５０μｍのパター
ンである。(3) An adhesive was applied to the surface of another transfer sheet made of polyethylene terephthalate (PET) resin, and a copper foil having a thickness of 18 μm and a surface roughness of 0.8 μm was adhered to one surface. Then, after applying a photoresist (dry film) and performing exposure and development, it was immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. The manufactured wiring circuit layer has a pattern in which the line width is 50 μm and the distance between the wirings is 50 μm.
【００５４】（４）さらに、ポリエチレンテレフタレー
ト（ＰＥＴ）樹脂からなるさらに別の転写シートの表面
に接着剤を塗布し、厚さ５０μｍ、表面粗さ１．２μｍ
の銅箔を一面に接着した。そして、フォトレジスト（ド
ライフィルム）を塗布し露光現像を行った後、これを塩
化第二鉄溶液中に浸漬して非パターン部をエッチング除
去して配線回路層を形成した。なお、作製した配線回路
層は、線幅が２００μｍ、配線と配線との間隔が２００
μｍのパターンである。なお、上記配線回路層の形成に
あたっては、エッチング速度を４０μｍ／分に設定し、
形成角θが６５°〜７５°の略台形形状となっているこ
とを確認した。(4) An adhesive is further applied to the surface of another transfer sheet made of polyethylene terephthalate (PET) resin to have a thickness of 50 μm and a surface roughness of 1.2 μm.
Was adhered to one surface. Then, after applying a photoresist (dry film) and performing exposure and development, it was immersed in a ferric chloride solution to remove non-pattern portions by etching to form a wiring circuit layer. Note that the manufactured wiring circuit layer has a line width of 200 μm and an interval between the wirings of 200 μm.
This is a μm pattern. In forming the wiring circuit layer, the etching rate was set to 40 μm / min.
It was confirmed that the formation angle θ was in a substantially trapezoidal shape of 65 ° to 75 °.
【００５５】（５）そして、（１）で作製したプリプレ
グに対して、（２）転写シートを、位置決めして３０ｋ
ｇ／ｃｍ2 の圧力を加えて圧着した後、転写フィルムを
剥離して、配線回路層をプリプレグに転写し、同様に、
（３）（４）で作製した配線回路層を順次転写させた。(5) Then, (2) the transfer sheet is positioned with respect to the prepreg prepared in
After applying pressure of g / cm 2 , the transfer film was peeled off, and the wiring circuit layer was transferred to a prepreg.
(3) The wiring circuit layers produced in (4) were sequentially transferred.
【００５６】（６）この厚さの異なる複数種の金属箔か
らなる配線回路層が形成されたプリプレグを中心に、そ
の上下面に（５）のようにして配線回路層が転写された
プリプレグを上下各２層づつ積層し３０ｋｇ／ｃｍ2 の
圧力で圧着し、２００℃で１時間加熱して完全硬化させ
て多層配線基板を作製した。(6) A prepreg on which a wiring circuit layer is transferred as shown in (5) above and below the prepreg on which a wiring circuit layer made of a plurality of types of metal foils having different thicknesses is formed. The upper and lower two layers were laminated, pressure-bonded at a pressure of 30 kg / cm 2 , heated at 200 ° C. for 1 hour and completely cured to produce a multilayer wiring board.
【００５７】得られた多層配線基板に対して、断面にお
ける配線回路層やビアホール導体の形成付近を観察した
結果、ビアホール導体と配線回路層とは良好な接続状態
であり、各配線間の導通テストを行った結果、配線の断
線も認められなかった。得られた多層配線基板を湿度８
５％、温度８５℃の高温多湿雰囲気に１００時間放置し
たが、目視で判別できる程度の変化は生じていなかっ
た。As a result of observing the vicinity of the formation of the wiring circuit layer and the via-hole conductor in the cross section of the obtained multilayer wiring board, the via-hole conductor and the wiring circuit layer were in a good connection state. As a result, no disconnection of the wiring was observed. The obtained multilayer wiring board was subjected to a humidity of 8
It was left in a hot and humid atmosphere of 5% and a temperature of 85 ° C. for 100 hours, but no change that could be visually recognized was generated.
【００５８】また、本発明に基づき厚さ１８μｍの銅箔
からなる配線回路層に対して、回路を１ｃｍ幅に加工し
てピール強度（引き剥がし強度）を測定した結果、１．
５ｋｇ／ｃｍ2 であり、高いピール強度を示した。The circuit was processed to a width of 1 cm with respect to the wiring circuit layer made of a copper foil having a thickness of 18 μm according to the present invention, and the peel strength (peeling strength) was measured.
5 kg / cm 2 , showing high peel strength.
【００５９】[0059]
【発明の効果】以上詳述したとおり、本発明によれば、
微細な回路形成、特にフリップチップ接続が可能なレベ
ルの微細な回路を形成可能な微細回路の形成が可能であ
り、かつ、コネクターや金具類、電池等大型の部品を接
続する部位に対して基板と銅箔との十分なピール強度を
確保しする多層配線基板を実現することを目的とするも
のである。さらに、本発明は、一部大電流が必要な回路
の形成も可能することができ、これにより高密度、高精
細、且つ多機能の配線基板を容易に形成できる。As described in detail above, according to the present invention,
It is possible to form a fine circuit, especially a fine circuit that can form a fine circuit of a level that can be flip-chip connected, and a substrate for connecting large parts such as connectors, metal fittings, batteries, etc. It is an object of the present invention to realize a multilayer wiring board that ensures a sufficient peel strength between the wiring board and a copper foil. Further, according to the present invention, it is possible to partially form a circuit that requires a large current, whereby a high-density, high-definition, and multifunctional wiring board can be easily formed.
【図１】本発明の多層配線基板の概略断面図である。FIG. 1 is a schematic sectional view of a multilayer wiring board according to the present invention.
【図２】本発明の多層配線基板における配線回路層の断
面図である。FIG. 2 is a sectional view of a wiring circuit layer in the multilayer wiring board of the present invention.
【図３】本発明の多層配線基板の製造工程を説明するた
めの図である。FIG. 3 is a diagram for explaining a manufacturing process of the multilayer wiring board of the present invention.
１ 多層配線基板 ２ａ〜２ｄ 絶縁層 ２ 絶縁基板 ３、３ａ〜３ｄ 配線回路層 ４ ビアホール導体 ５ 半導体素子 ６ 金具 DESCRIPTION OF SYMBOLS 1 Multilayer wiring board 2a-2d Insulating layer 2 Insulating substrate 3, 3a-3d Wiring circuit layer 4 Via hole conductor 5 Semiconductor element 6 Metal fitting
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.6 識別記号 ＦＩ Ｈ０５Ｋ 3/46 Ｈ０５Ｋ 3/46 Ｅ // Ｈ０５Ｋ 3/20 3/20 Ａ ──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. 6 Identification code FI H05K 3/46 H05K 3/46 E // H05K 3/20 3/20 A
Claims (12)
らなる絶縁層を積層してなる絶縁基板と、該絶縁基板の
表面および／または内部に形成された配線回路層と、前
記配線回路層間を電気的に接続するためのビアホール導
体を具備する多層配線基板において、少なくとも１層の
絶縁層内に、厚さの異なる配線回路層が形成されてなる
ことを特徴とする多層配線基板。An insulating substrate formed by laminating an insulating layer made of an insulating material containing at least a thermosetting resin; a wiring circuit layer formed on the surface and / or inside of the insulating substrate; A multilayer wiring board having via hole conductors for electrical connection, wherein wiring circuit layers having different thicknesses are formed in at least one insulating layer.
記絶縁基板の表面に形成されてなる請求項１記載の多層
配線基板。2. The multilayer wiring board according to claim 1, wherein the plurality of wiring circuit layers having different thicknesses are formed on a surface of the insulating substrate.
記絶縁基板の内部に形成されてなる請求項１記載の多層
配線基板。3. The multilayer wiring board according to claim 1, wherein the plurality of wiring circuit layers having different thicknesses are formed inside the insulating substrate.
記載の多層配線基板。4. The wiring circuit layer is made of a metal foil.
The multilayer wiring board as described in the above.
半導体素子が収納されたパッケージが実装される配線回
路層が１８μｍ以下の厚さを有していることを特徴とす
る請求項１記載の多層配線基板。5. The wiring circuit layer according to claim 1, wherein, among the wiring circuit layers, a wiring circuit layer on which a semiconductor element or a package containing the semiconductor element is mounted has a thickness of 18 μm or less. Multilayer wiring board.
コネクタ取り付け部、他の基板の金具との接触部となる
配線回路層が１２μｍ以上の厚さを有していることを特
徴とする請求項１記載の多層配線基板。6. A metal fitting mounting part in the wiring circuit layer.
2. The multilayer wiring board according to claim 1, wherein a wiring circuit layer serving as a connector mounting portion and a contact portion with a metal fitting of another board has a thickness of 12 μm or more.
流が印加される配線回路層が３５μｍ以上の厚さを有し
ていることを特徴とする請求項１記載の多層配線基板。7. The multilayer wiring board according to claim 1, wherein, among the wiring circuit layers, a wiring circuit layer to which a large current of 10 A or more is applied has a thickness of 35 μm or more.
に形成された配線回路層が前記絶縁基板表面に埋設され
ており、その断面形状が、埋設側の辺が露出側の辺より
も長い略逆台形形状からなる請求項１記載の多層配線基
板。8. A wiring circuit layer formed on the surface of the insulating substrate among the wiring circuit layers is buried in the surface of the insulating substrate, and the cross-sectional shape of the wiring circuit layer is such that the buried side is smaller than the exposed side. 2. The multilayer wiring board according to claim 1, wherein the multilayer wiring board has a long inverted trapezoidal shape.
末の充填によって形成されてなることを特徴とする請求
項１記載の多層配線基板。9. The multilayer wiring board according to claim 1, wherein said via-hole conductor is formed by filling at least a metal powder.
さの異なる複数の配線回路層を形成する工程と、少なく
とも熱硬化性樹脂を含む未硬化または半硬化状態の絶縁
シートの表面に、前記転写シートの配線回路層を順次、
加圧転写させる工程と、前記絶縁シートを前記熱硬化性
樹脂が完全硬化するに十分な温度で加熱する工程とを具
備することを特徴とする多層配線基板の製造方法。10. A step of forming a plurality of wiring circuit layers having different thicknesses on the surface of a plurality of transfer sheets, and forming the plurality of wiring circuit layers on a surface of an uncured or semi-cured insulating sheet containing at least a thermosetting resin. The wiring circuit layers of the transfer sheet are sequentially
A method for manufacturing a multilayer wiring board, comprising: a step of transferring under pressure; and a step of heating the insulating sheet at a temperature sufficient to completely cure the thermosetting resin.
１０記載の多層配線基板の製造方法。11. The method according to claim 10, wherein said wiring circuit layer is made of a metal foil.
転写シート全面に形成された金属層をエッチング処理し
て断面形状が台形状を有し、且つ表面が平均表面粗さ２
００ｎｍ以上に粗化処理されてなる請求項１０記載の多
層配線基板の製造方法。12. The wiring circuit layer on the surface of the transfer sheet,
The metal layer formed on the entire surface of the transfer sheet is etched to have a trapezoidal cross section and an average surface roughness of 2
11. The method for manufacturing a multilayer wiring board according to claim 10, wherein the roughening treatment is performed to a thickness of at least 00 nm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14938198A JP3441368B2 (en) | 1998-05-29 | 1998-05-29 | Multilayer wiring board and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14938198A JP3441368B2 (en) | 1998-05-29 | 1998-05-29 | Multilayer wiring board and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11340367A true JPH11340367A (en) | 1999-12-10 |
| JP3441368B2 JP3441368B2 (en) | 2003-09-02 |
Family
ID=15473895
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14938198A Expired - Fee Related JP3441368B2 (en) | 1998-05-29 | 1998-05-29 | Multilayer wiring board and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3441368B2 (en) |
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| JP2002111203A (en) * | 2000-09-28 | 2002-04-12 | Kyocera Corp | Film with metal foil and method for manufacturing multilayer wiring board using the same |
| JP2002204043A (en) * | 2000-10-31 | 2002-07-19 | Kyocera Corp | Wiring board and method of manufacturing the same |
| KR100346388B1 (en) * | 2000-09-18 | 2002-08-01 | 삼성에스디아이 주식회사 | Circuit substrate in batterypack for notebook computer |
| JP2002290033A (en) * | 2001-03-23 | 2002-10-04 | Kyocera Corp | Method for manufacturing multilayer wiring board |
| JP2003101197A (en) * | 2000-02-09 | 2003-04-04 | Matsushita Electric Ind Co Ltd | Wiring board and multilayer wiring board |
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| US7888789B2 (en) | 2000-02-09 | 2011-02-15 | Panasonic Corporation | Transfer material used for producing a wiring substrate |
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| JP2003101197A (en) * | 2000-02-09 | 2003-04-04 | Matsushita Electric Ind Co Ltd | Wiring board and multilayer wiring board |
| US7888789B2 (en) | 2000-02-09 | 2011-02-15 | Panasonic Corporation | Transfer material used for producing a wiring substrate |
| KR100346388B1 (en) * | 2000-09-18 | 2002-08-01 | 삼성에스디아이 주식회사 | Circuit substrate in batterypack for notebook computer |
| JP4570225B2 (en) * | 2000-09-28 | 2010-10-27 | 京セラ株式会社 | Film with metal foil and method for producing multilayer wiring board using the same |
| JP2002111203A (en) * | 2000-09-28 | 2002-04-12 | Kyocera Corp | Film with metal foil and method for manufacturing multilayer wiring board using the same |
| JP4605939B2 (en) * | 2000-10-31 | 2011-01-05 | 京セラ株式会社 | Wiring board manufacturing method |
| JP2002204043A (en) * | 2000-10-31 | 2002-07-19 | Kyocera Corp | Wiring board and method of manufacturing the same |
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| US6663946B2 (en) | 2001-02-28 | 2003-12-16 | Kyocera Corporation | Multi-layer wiring substrate |
| JP2002290033A (en) * | 2001-03-23 | 2002-10-04 | Kyocera Corp | Method for manufacturing multilayer wiring board |
| JP4637389B2 (en) * | 2001-03-23 | 2011-02-23 | 京セラ株式会社 | Manufacturing method of multilayer wiring board |
| US8759953B2 (en) | 2004-02-13 | 2014-06-24 | Murata Manufacturing Co., Ltd. | Electronic component including a shielding metal film disposed on a resin layer |
| JP2006108129A (en) * | 2004-09-30 | 2006-04-20 | Teikoku Tsushin Kogyo Co Ltd | Circuit board manufacturing method and circuit board |
| JP2015050259A (en) * | 2013-08-30 | 2015-03-16 | 京セラ株式会社 | Semiconductor element mounting substrate and semiconductor device comprising the same |
| JP2015053444A (en) * | 2013-09-09 | 2015-03-19 | パナソニックＩｐマネジメント株式会社 | Flexible semiconductor device, manufacturing method thereof and image display device |
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| JP3441368B2 (en) | 2003-09-02 |
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