JPH11296133A - Drive circuit for image display device - Google Patents

Abstract

(57) [Problem] The present invention can easily cope with display modes with different resolutions without newly providing a memory or an arithmetic circuit for creating data and without increasing power consumption. It is another object of the present invention to provide a driving circuit capable of improving the reliability as a display device. A pair of source drivers connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplying a horizontal video signal of the predetermined number of horizontal pixels;
22 and video signal lines 29a, 29 that split the video signal and send the same video signal to each of the source drivers.
b, and a horizontal video signal control circuit 30 that supplies a set of sampling timing signals to each of the pair of source drivers and generates a horizontal video signal having the predetermined number of horizontal pixels in each source driver. is there.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a driving circuit of a display device having a high-resolution display panel used by switching resolutions.

[0002]

2. Description of the Related Art In a display device for a personal computer, the resolution of a display screen is sometimes switched. In the standards of this type of conventional display device, VGA standard, SVGA standard, XGA standard, SXGA standard are used. Standards, UXG
The A standard and the like are widely known as typical ones. The number of pixels constituting one screen of these standards is as follows. VGA standard; horizontal direction: 640 pixels, vertical direction: 480 pixels SVGA standard: horizontal direction: 800 pixels, vertical direction: 600 pixels XGA standard: horizontal direction: 1024 pixels, vertical direction 768 pixels SXGA standard; horizontal direction: 1280 pixels, vertical direction: 1024 pixels UXGA standard; horizontal direction: 1600 pixels, vertical direction: 1200 pixels (VGA, SVGA, XGA, SXG
A and UXGA are both registered trademarks of IBM Corporation. Normally, in each of the above standards, three pixels of red (R), blue (B), and green (G) are arranged in one pixel. .

Therefore, when switching the display in accordance with each standard in this type of display device, it is necessary to enlarge or reduce a character signal or the like on a display screen having a certain display area. As an example of a conventional signal enlarging technology in this type of display device, a technology disclosed in Japanese Patent Application Laid-Open No. 8-129356 or Japanese Patent Application Laid-Open No. 8-166778 is disclosed.
There is known a technique disclosed in Japanese Patent Application Laid-Open Publication No. H10-26095. JP 8
The technology disclosed in Japanese Patent Application Laid-Open No. 129356 discloses a technique in which the resolution of image data is detected by a detection circuit, an enlargement ratio is set by an enlargement circuit based on a ratio with a display panel, and image data for one screen is stored in a frame memory. The image data for two consecutive lines read from the frame memory is complemented by an arithmetic circuit based on the enlargement ratio and sent to a display panel for display. Japanese Patent Application Laid-Open No. 8-166778 discloses a technique in which three rows of original display luminance data to be displayed on three pixels are arranged in a matrix in which display dots composed of three pixels are arranged in a matrix. The image data is expanded by an arithmetic circuit, weighted with a predetermined luminance to form enlarged display luminance data, and this data is output to pixels to enlarge the original image in the row direction of the display panel. However, in the technology disclosed in Japanese Patent Application Laid-Open No. 8-129356 and the technology disclosed in Japanese Patent Application Laid-Open No. 8-166778, data computation, re-sampling, and addition of memory must be performed. The circuit scale becomes large, which hinders downsizing of the entire display device and increases costs.

Next, in consideration of these techniques, the present inventor assumes a display device having a structure shown in FIG. 16 as an example of a display device having a signal enlargement structure that does not require the addition of a memory. The display device shown in FIG. 16 includes a first horizontal driver 2 and a second horizontal driver 2 connected to a source line side, with respect to a thin film transistor type liquid crystal display panel 1 having source lines and gate lines arranged in a matrix. The horizontal driver 3 is connected to a vertical driver 4 connected to the gate wiring side, and a signal processing circuit 5 for controlling the drivers 2, 3, and 4 is provided. Inside the signal processing circuit 5, a sampling circuit 7 to which a video signal as original data is input, a frequency dividing circuit 8 and a signal selecting circuit 9 connected to the sampling circuit 7, and the horizontal drivers 2, 3 A horizontal control circuit 10 for controlling and a vertical control circuit 11 for controlling the vertical driver 4 are provided, and a clock generation circuit 12 is connected to the signal processing circuit 5. The liquid crystal display panel 1 used in this example has a horizontal pixel count of 1024 according to the XGA standard.
And 768 pixels in the vertical direction.

In the display device shown in FIG. 16, when the original data of the VGA standard video signal (clock 27.175 MHz), for example, the signal ABCDE shown at H in FIG. 17 is input to the signal processing circuit 5, this signal is sampled. Circuit 7
The sampling circuit 7 generates conversion data AABCCDEE... Indicated by I in FIG. 17 by a sampling clock of 40.28 MHz, and sends the conversion data I to the frequency dividing circuit 8. That is, since the video signal of the VGA standard has 1H = 640 data, it is necessary to adjust the data by 1.6 times to make 1H = 1024 of the XGA standard.
A sampling clock of 40.28 MHz 1.6 times as large as z is used.

Next, the converted data is divided into an odd number signal and an even number signal by a frequency dividing circuit 8, and the odd number signal ABCE shown by J in FIG. 17 is input to the horizontal driver 2 as an output to the driver.
Are input to the second horizontal driver 3 as an output of the driver. Here, the horizontal control circuit 10 includes a first horizontal driver 2 and a second horizontal driver 3.
16 are controlled so that signals can be alternately input to the source line of the liquid crystal display panel 1 from the liquid crystal display panel 1.
AABCCDEE as shown in the liquid crystal display panel 1 of FIG.
Data can be displayed.

On the other hand, when the original data of the XGA standard video signal is input, the signal is bypassed to the sampling circuit 7 and sent to the frequency dividing circuit 8 as shown by I 'in FIG. If the same frequency division processing is performed, the original X
The video signal of the GA standard can be distributed to the first horizontal driver 2 and the second horizontal driver 3 by the signal selection circuit 9 and synthesized by the liquid crystal display panel 1 to perform the display of the XGA standard.
In other words, by adopting the circuit structure shown in FIG.
The video signal of the standard can be output to the liquid crystal display panel 1, and the video signal of the original data of the XGA standard can be output to the liquid crystal display device 1.
Output.

[0008]

However, in the circuit structure shown in FIG. 16, a circuit for generating a clock having a cycle different from the cycle of the original data is separately required, the circuit scale becomes large, and the size of the display device is reduced. There was a problem that hindered. Furthermore, the power consumption tends to increase because the operating frequency also increases, and there is a problem that when the power consumption of a normal signal processing circuit is 250 mW, it increases to about 400 mW. In addition, the sampling setup time,
Since the hold time is strict, the reliability of the display device is deteriorated, which may lead to deterioration of image quality.

The present invention has been made in view of the above circumstances, and can easily cope with display modes having different resolutions without newly providing a memory or an arithmetic circuit for creating data and without increasing power consumption. It is an object of the present invention to provide a driving circuit capable of improving the reliability of a display device.

[0010]

According to the present invention, one frame is a completed image, and a plurality of divided images constituting one frame are each referred to as one field. In order to solve the above-mentioned problems, the present invention provides a pair of source drivers connected to a display panel in which a predetermined number of horizontal pixels and a number of vertical pixels are respectively set and providing a horizontal video signal of the predetermined number of horizontal pixels; And a video signal line for sending the same video signal to each of the source drivers, and a set of sampling timing signals to each of the pair of source drivers. A horizontal video signal control circuit for generating a horizontal video signal having a small number of pixels and having the predetermined number of horizontal pixels when these horizontal video signals are combined.

By adopting such a structure, the sampling timing signal is adjusted, so that an image can be adjusted to the resolution of the display panel without adding a separate memory and without requiring a separate clock generation circuit. Since signals can be synthesized by both source drivers and sent to the display panel, it contributes to downsizing of the circuit, reduction of power consumption, and improvement in reliability of the display device.

In the present invention, a pair of source drivers which are connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively provided and provide a horizontal video signal of the predetermined number of horizontal pixels; Is copied into two when the number of horizontal pixels is smaller than the predetermined horizontal video signal, and is divided into two when the video signal is the predetermined horizontal video signal, and each of the replicated or divided video signals is A signal selection circuit to be sent to each of the source drivers, and a video signal having the predetermined number of horizontal pixels or a video signal having a smaller number of horizontal pixels than this signal is determined according to a synchronization signal, and the video signal is copied or divided by the signal selection circuit. A resolution discriminating circuit for providing the control signal, a frequency dividing circuit for dividing the video signal into two and supplying the divided video signal to the signal selection circuit, and a set of sampling timing signals It is given to each of the pair of source drivers, and is a horizontal video signal having a smaller number of pixels than the predetermined horizontal pixel number at each source driver. And a horizontal video signal control circuit for generating a horizontal video signal.

With this structure, the sampling timing signal is adjusted according to the conversion ratio between the number of horizontal pixels of the input video signal and the number of horizontal pixels of the display panel.
Even if the number of horizontal pixels of the video signal is larger than the number of horizontal pixels of the display panel, or if the number of horizontal pixels of the video signal is smaller than the number of horizontal pixels of the display panel, the video signal is divided. After that, each signal is adjusted by the sampling timing signal, and in any case, a horizontal video signal corresponding to the number of horizontal pixels of the display panel can be transmitted by the adjusted signal combination. Here, a part of the horizontal video signal having a predetermined number of horizontal pixels is thinned out. However, since the thinned data can be set arbitrarily, any conversion rate can be easily dealt with. . Therefore, the video signal corresponding to the resolution of the display panel can be synthesized by both the source drivers and sent to the display panel without separately adding a memory and without requiring a separate clock generation circuit. This contributes to downsizing of a circuit and reduction in power consumption, and leads to improvement in reliability as a display device.

In the present invention, a source driver which is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplies a horizontal video signal having the predetermined number of horizontal pixels is the same as a source driver which duplicates a video signal. And a set of sampling timing signals are sequentially supplied to the source driver, and the source driver sequentially generates horizontal video signals having a smaller number of pixels than the predetermined number of horizontal pixels. A horizontal video signal control circuit may be provided. Further, a set of sampling timing signals are sequentially supplied to the source driver, and the source driver generates a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels, and sets the position of the thinned data for each field and each line. ,
A horizontal video signal control circuit for switching at any time may be provided.

By performing signal processing in this manner, an output corresponding to the resolution can be obtained without the need for a separate clock generation circuit, which has been required in the past, so that the circuit can be reduced in size and power consumption can be reduced. This contributes to improving the reliability of the display device. Generating a horizontal video signal having a smaller number of pixels than a predetermined number of horizontal pixels means that some data of the signal is thinned out. By sending the signals every time, it is easy to average the thinned signal portions of the entire screen, and a display similar to the original image can be obtained. Such data thinning can be easily dealt with by temporarily stopping the clock signal at the source driver and temporarily stopping the data sampling.

In the present invention, a source driver is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set, and supplies a horizontal video signal of the predetermined number of horizontal pixels. When the signal has a smaller number of horizontal pixels than a predetermined horizontal video signal, the signal is copied into two, and when the video signal is the predetermined horizontal video signal, the signal is divided into two.
A signal selection circuit for sequentially sending each of the duplicated or divided video signals to the source driver, and determining a video signal having the predetermined number of horizontal pixels or a video signal having a smaller number of horizontal pixels than this signal in accordance with a synchronization signal, A resolution discrimination circuit that supplies a control signal indicating whether a video signal is copied or divided to a signal selection circuit, a frequency division circuit that divides a video signal into two and supplies a divided video signal to the signal selection circuit, and a set of sampling timings Signals are sequentially supplied to the source driver, and the source driver sequentially generates horizontal video signals having a smaller number of pixels than the predetermined number of horizontal pixels, and the number of horizontal video signals is equal to the number of horizontal pixels when these horizontal video signals are combined. A horizontal video signal control circuit may be provided.

Further, a set of sampling timing signals is sequentially supplied to the source driver, and the source driver outputs a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels. A horizontal video signal control circuit for generating a horizontal video signal corresponding to the number of pixels for each of field, line, and time may be provided.

Generating a horizontal video signal that is smaller than a predetermined number of horizontal pixels and has a predetermined number of horizontal pixels when united results in thinning out some data of the signal. The thinned data is sequentially displayed. To the device or field by field,
By changing the position of the thinned data for each line or for each time and sending it, it is easy to average the thinned signal portions of the entire screen, and a display similar to the original image can be obtained.

[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Each embodiment of the present invention will be described below in detail, but the present invention is not limited to these embodiments. First Embodiment FIG. 1 shows a first embodiment of a resolution conversion display device according to the present invention. In this example, a resolution conversion display device 19 includes a source wiring and a gate wiring arranged in a matrix and a matrix. Matrix display panel 20 (for example, liquid crystal display panel: LCD) configured by arranging pixel electrodes and thin film transistors in a shape
And a first source driver 21 and a second source driver 22 connected to the source wiring side, a gate driver 23 connected to the gate wiring side, and a signal processing circuit 25 connected thereto. I have. Also,
The display panel 20 used in this embodiment has 1024 horizontal pixels and 768 vertical pixels in conformity with the XGA standard.

In the structure of this embodiment, the first source driver 21 and the second source driver 22
Of the first source driver 21 are connected to the odd-numbered source lines among the source lines arranged in the vertical direction of the display panel 20, and the odd-numbered source lines are connected to the output terminals of the first source driver 21. The first source driver 2 for
1 is input to each of the output terminals of the second source driver 22 to the even-numbered source lines, and the output terminals of the second source driver 22 are connected to the even-numbered source lines of the display panel 20. The two-source driver 22 is configured to be able to input signals. Therefore, the output of the first source driver 21 and the output of the second source driver 22 are combined so that all the horizontal pixels corresponding to the number of horizontal pixels of the display panel 20 can be driven.

The signal processing circuit 25 is configured to receive a video signal from a video signal generator 26 such as a personal computer via a signal line 26a. Frequency dividing circuit 28 and signal selecting circuit (resolution determining circuit) connected to circuit 27
29, a horizontal control circuit (horizontal video signal control circuit) 30 for controlling the source drivers 21 and 22, and a vertical control circuit (vertical video signal control circuit) 31 for controlling the gate driver 23 are provided. Have been.

The signal selection circuit 29 includes a source driver 21,
22 are connected via video signal lines 29a and 29b, respectively, so that the video signal input to the signal selection circuit 29 can be sent to the source drivers 21 and 22, respectively. The horizontal control circuit 30 is connected to the source drivers 21 and 22 via control lines 30a and 30b, respectively, and sends a set of sampling timing signals to each of the source drivers 21 and 22, respectively. A horizontal image having a smaller number of pixels than the number of horizontal pixels of the panel 20 (1024 horizontal pixels in this embodiment). When the respective horizontal image signals of the source drivers 21 and 22 are combined, the number of horizontal pixels of the display panel 20 is reduced. (1024 in this embodiment).

Next, as shown in FIG. 1, the XGA standard (10
24 × 768), the input video signal (original data) is X
GA standard data and VGA standard (640 × 48
The respective operations will be described for the case of data 0). <When the original data conforms to the XGA standard> Video signal generator 26
When the original data (video signal) sent to the signal processing circuit 25 via the signal line 26a from the input terminal is input to the latch circuit 27, the latch circuit 27 latches the original data and
8 and the signal selection circuit 29. The frequency dividing circuit 28 decomposes the original data into two pieces of odd-numbered data and even-numbered data and sends it to the signal selecting circuit 29. The signal selection circuit 29 determines the resolution of the original data based on the original data sent from the latch circuit 27, determines that the original data has the XGA standard resolution, and divides the frequency by the frequency dividing circuit 28. The data is selected and the odd-numbered data is sent to the first source driver 21 via the video signal line 29a.
2, the even-numbered data is sent via the video signal line 29b. Then, by inputting the data sent to each of the source drivers 21 and 22 directly to the source wiring side of the display panel 20, the XGA standard data is input and displayed on the display panel 20 having the XGA standard resolution without any trouble. can do. That is, when the number of horizontal pixels of the original data and the number of horizontal pixels of the display panel 20 are the same, the signal processing circuit 25 divides the original data into two by the frequency dividing circuit 28 and then directly converts the original data into the first source driver 21 and the second source driver 22. To display.

<When the original data is VGA standard> When the original data is the number of horizontal pixels 640, that is, when the 1H = 640 VGA standard data, the display panel 20 displays the number of horizontal pixels 102
4, that is, since it has the resolution of the XGA standard of 1H = 1024, the processing described below is performed. First, the original data sent to the signal processing circuit 25 is input to the latch circuit 27, latched, and sent to the frequency dividing circuit 28 and the signal selecting circuit 29, respectively. The signal selection circuit 29 determines the resolution of the original data, determines that the resolution is VGA standard, and creates exactly the same two-series data as the original data sent from the latch circuit 28 (that is, the original data). Copy) and
The two data are directly used as the first and second source drivers 2
1 and 22 via video signal lines 29a and 29b. Next, the horizontal control circuit 30 controls the timing at which the data sent to the source drivers 21 and 22 is sampled.

For example, the horizontal control circuit 30 temporarily stops the clock of the driver, thereby thinning out some of the data a input to the source drivers 21 and 22 to reduce the thinned data. As shown in b and c ′ of FIG. 2 for each source driver (for example, data b of ABCE... In which D is thinned out as the output of the first source driver, and A in which B is thinned out as the output of the second source driver)
The data c ′) of CDE... Are created, and the thinned-out and sampled data b and c ′ are output to the display panel 20 side and united to obtain d (see the output d in FIG. 2).
Output as

Here, the rate of thinning out the data needs to correspond to the change rate of the resolution. In order to output 1H = 1024 data by the two source drivers 21 and 22, 512 data per one driver are required. Since 1H = 640 data per driver is required for 5
12 (that is, the data input to each of the source drivers 21 and 22 is individually thinned out by 20%). When the thinned and sampled data b and c ′ are input to the display panel 20 side, the data output to the display panel 20 becomes AAB as shown in FIG.
1024 data per 1H as in CCDEE. That is, the magnification of the horizontal pixel number conversion is 1.6 times, that is, the data is converted from the VGA standard to the XGA standard data.

As described above, in the first embodiment, by performing the signal processing described above with reference to the structure shown in FIG. 1 and FIG. 2, an individual clock generation circuit which is conventionally required is required. Therefore, an output that matches the resolution can be obtained, which contributes to downsizing of the circuit, reduction of power consumption, and improvement in reliability of the display device.

In the above description, the case where the video signal of the VGA standard or the XGA standard is displayed on the display device of the XGA standard has been described.
Of course, the present invention can also be applied to a case where video signals having various numbers of horizontal pixels are input to any of a standard display device, an SXGA standard display device, and a UXGA standard display device. In this case, the source driver 21,
In the case of sampling at 22, the number of pixels to be thinned can be adjusted to any number of pixels by appropriately adjusting the number of data to be thinned according to the conversion ratio of the number of pixels. That is,
The sampling timing signal is adjusted in accordance with the conversion ratio between the number of horizontal pixels of the input video signal and the number of horizontal pixels of the display panel 20, and when the number of horizontal pixels of the video signal is larger than the number of horizontal pixels of the display panel. Even if the number of horizontal pixels of the video signal is smaller than the number of horizontal pixels of the display panel, the video signal is divided or copied, and each signal is adjusted by the sampling timing signal to adjust the required number of pixels. In any case, a horizontal video signal according to the number of horizontal pixels of the display panel can be transmitted by the adjusted signal combination.

In the first embodiment, the display based on the conversion of the number of horizontal pixels has been described. However, the display in the vertical direction can be displayed by, for example, a method described below. First Example of Vertical Display The conversion of the number of pixels in the vertical direction is not particularly performed, and a margin display is used in the vertical direction. In the vertical direction display of a generally used wide wide television screen, the lower or upper part is a margin part, and the image is converted and displayed only in the horizontal direction, so by adopting this method in the present invention, Both horizontal and vertical display can be performed in combination with the horizontal pixel number conversion described above. By employing this method, it is possible to display in both the horizontal and vertical directions while taking advantage of the feature of the present invention that the circuit is downsized by not using a memory circuit such as a memory.

Second Example of Vertical Display A plurality of gates are collectively driven in accordance with the magnification of the horizontal pixel number conversion. For example, when the gate driver 23 shown in FIG. 3A is controlled, it is turned on (ON) during one horizontal scanning period.
By switching the number of gate lines (gate lines) to be displayed, enlarged display in the vertical direction can be performed. The number of gate lines to be turned on at the same time can be switched according to the conversion magnification. For example, if the VGA display is XGA
When converting to display, the number of lines needs to be increased by 1.6 times. Therefore, information for 5 lines of gate lines shown in FIG. 3A is converted into information for 8 lines, and display in the vertical direction is performed. For example, when an original image signal composed of A, B, C, D, and E shown in FIG.
3 to a, a, b, c, c, d,
Signals are input as e and e. That is, A, B, C, D,
When writing only the line data of A, C, and E with respect to the five line data of E, two gate lines are simultaneously turned on. Thereby, the five line data can be enlarged and displayed to eight lines.

The locations on the screen to be simultaneously turned on in this manner are shown in FIG. 3 (B) in field units (or frame units) in the same manner as described with reference to FIG. By switching as shown in (1), a spatially calculated (averaged) display can be obtained, and an extremely smooth display form can be obtained. That is, by controlling the number of gate lines that are simultaneously turned on in accordance with the conversion rate, it is possible to cope with conversions of any resolution. Further, such a vertical conversion can be easily applied to any of the embodiments described below.

[Second Embodiment] FIG. 4 shows a second embodiment of the resolution conversion display device according to the present invention. The resolution conversion display device 33 of this example has a source wiring and a gate wiring arranged in a matrix. And an active matrix type display panel (for example, a liquid crystal display panel: L) in which pixel electrodes and thin film transistors are arranged in a matrix.
CD) 20, a first source driver 21 and a second source driver 22 connected to the source wiring side, a gate driver 23 connected to the gate wiring side, and a signal processing circuit 35 connected thereto. It is configured. The display panel 20 used in this embodiment has 1024 horizontal pixels and 76 vertical pixels according to the XGA standard.
Eight.

Next, the signal processing circuit 35 is configured so that a video signal from a video signal generating device 26 such as a personal computer is input thereto.
1, a horizontal control circuit (horizontal video signal control circuit) 30 for controlling the gate driver 23 and a vertical control circuit (vertical video signal control circuit) 31 for controlling the gate driver 23 are provided. Further, in the structure of this embodiment, the first source driver 21, the second source driver 22, and the gate driver 23 have the same structure as that of the previous embodiment, but the video signal (original data) output from the video signal generator is used. ) Are configured to be directly input to the source drivers 21 and 22 via the video signal lines 36a and 36b branched from the video signal line 36.

The horizontal control circuit 30 includes a source driver 21,
22 is connected to each of the source drivers 21 and 22 via control lines 30a and 30b, respectively.
1 and 22 are horizontal images having a smaller number of pixels than the number of horizontal pixels of the display panel 20 (the number of horizontal pixels is 1024 in this embodiment). The configuration is such that horizontal video signals having the number of horizontal pixels (1024 in this embodiment) of the display panel 20 can be sequentially generated (for each field).

<When the original data is a standard smaller than the resolution XGA standard of the display device> The original data is 64 horizontal pixels.
In the case of a standard smaller than the data of the XGA standard, such as 0, that is, the VGA standard of 1H = 640, the display panel 20 has 1024 horizontal pixels, that is, the resolution of the XGA standard of 1H = 1024. Perform processing. First, the original data is directly sent to the two source drivers 21 and 22 via the signal lines 36a and 36b. The data is thinned out by controlling the sampling of digital data in the source drivers 21 and 22. The sampling control here can be individually thinned out and controlled by temporarily stopping the sampling of data by the source drivers 21 and 22 by the operation of the horizontal control circuit 30, and the thinned out data is line by line. Switch. Then, the thinned data is output to the display panel 20 as it is.

In this case, the n-th output from the source driver 21 is indicated by f in FIG. 5, and the n-th output from the source driver 22 is indicated by g in FIG. By combining these, the display shown in FIG. 5H can be output to the liquid crystal panel 20. Next, the (n + 1) th output from the source driver 21 is indicated by i in FIG. 5, and the (n + 1) th output from the source driver 22 is indicated by j in FIG. Fig. 5
(K) can be output to the liquid crystal panel 20. That is, in the above processing, the thinned data is switched for each line by the source drivers 21 and 22 and the thinned data is output to the display panel 20 as it is.

<When the original data conforms to the resolution XGA standard of the display device> In this case, the original data is sent to the two source drivers 21 and 22 as they are via the signal lines 36a and 36b. At the time of sampling digital data, the data is thinned out and only half of the original data is sampled. Then, by outputting the thinned data to the display panel 20 as it is, the liquid crystal panel 20 can display XGA standard data.

The data thinning rate must correspond to the resolution change rate. In order to output 1H = 1024 data by the two source drivers 21 and 22, 512 data are required for one driver. Because there is one
1H = 1024 data per driver is reduced by half to 5
12 (that is, by thinning out the data input to the source drivers 21 and 22 individually by 50%).

As described above, in the second embodiment, by performing the signal processing described above with reference to the structure shown in FIG. 4 and FIG. 5, an individual clock generation circuit which is conventionally required is required. Therefore, an output that matches the resolution can be obtained, which contributes to downsizing of the circuit, reduction of power consumption, and improvement in reliability of the display device. In addition, since the thinning data is changed for each vertical line, the display of the line to be switched (horizontal line for thinning) can be displayed in a spatially integrated display form, and the thinning data is averaged over the entire screen. Therefore, the contour on the display can be smoothed, and a display similar to the original image can be obtained. In addition, flicker can be reduced by improving the spatial frequency.

[Third Embodiment] FIGS. 6 and 7 show a third embodiment of the present invention.
Display panel with a resolution of 024 × 768 pixels), 41
Is a source driver corresponding to the VGA standard (640 × 480 pixels), 43 is a gate driver, 45 is a signal processing circuit, 47 is a latch circuit, 48 is a frequency divider circuit, 49 is a signal selection circuit (resolution determination circuit), and 50 is A horizontal control circuit (horizontal video signal control circuit), 51 indicates a vertical system control circuit (vertical video signal control circuit), 49a indicates a video signal line, and 50a indicates a control line. 8 and 9 show structural examples of a liquid crystal display device suitable as a display panel of the second embodiment. The configuration of this mode is equivalent to 1H in which the number of outputs is about half of the XGA standard
= 640 VGA standard source driver and 1
This is a mode for displaying images of the XGA standard and the VGA standard on a display panel (for example, a liquid crystal display panel: LCD) 40 in the case of a configuration having a display panel having a resolution of the XGA standard of H = 1024. In this embodiment, the source driver 41 is configured by applying a driver having an output capability of the VGA standard to a structure described below with reference to FIG. 8 or FIG.

<When the data conforms to the XGA standard> Original data (video signal) from the video signal generator 26 such as a personal computer is transmitted to the signal processing circuit 45 via the signal line 26a.
The original data is input to the latch circuit 47, which latches the original data and
8 and the original data are sent to the signal selection circuit 49, respectively. The original data is thinned out every other data by the frequency dividing circuit 48, the number of data is reduced to half, and sent to the signal selecting circuit 49. The data to be thinned out at this time is switched for each frame.

Next, the signal selection circuit 49 uses the latch circuit 47.
Determines the resolution of the original data sent from
It is determined that the resolution is A standard, and the data divided by the frequency dividing circuit 48 is selected and sent to the source driver 41 via the video signal line 49a. The data sent to the source driver 41 is output to the display panel 40 as it is. By performing such processing, a source driver 41 compatible with the VGA standard and a display panel 40 compatible with the XGA standard are provided, and when the original data of the XGA standard is input, the display panel 40 conforms to the XGA standard without any trouble. Can output video.

Next, before describing the signal processing situation in the case where the data conforms to the VGA standard, an example of a display panel 40 suitable for application to the circuit of the second embodiment will be described. FIG.
Shows a circuit configuration example of a drive substrate of an active matrix type liquid crystal display panel suitable for application to the circuit of the second embodiment. In this example, source wirings D1 and D2 are connected to output terminals of a source driver 41. , D3, D4,..., And the gate wiring G is connected to each output terminal of the gate driver 43.
1, G2, G3, G4, G5, G6, G7... Are connected, and one or two are connected to a region surrounded by a source wiring and a gate wiring.
One pixel electrode S is provided, and a region corresponding to the pixel electrode S is a display unit.

In the structure of this example, the gate lines G1, G
2, G3, G4, G5, G6,... Other than the first and last ones are provided adjacent to each other in pairs, and each pixel electrode S and a part of a source line or a gate line. A switching element T such as a thin film transistor is connected to a part thereof. Further, two rows of pixel electrodes S located on the left and right sides of one source line D are connected via switching elements T, respectively, and one source line D
, Each of the pixel electrodes S located on the left and right thereof is connected to a different gate line G.

In order to drive the display panel having this configuration, as shown in the timing chart of FIG. 10, even-numbered gate lines G2 are arranged in the order of gate lines G2, G4, G6,. , G4, G6,... Are operated. Next, in the second field, the switching elements T connected to the odd-numbered gate lines G1, G3, G5,... Are operated in the order of the gate lines G1, G3, G5,. By the operation of the gate driver 43, the writing position of the data sent from the source driver 41 can be switched for each field, whereby the original data (video data) of the VGA standard can be switched as described above with reference to FIG. Signal) can be output to the display panel 40 of the XGA standard.

In the structure shown in FIG. 8, two rows of pixel electrodes S are connected to one source line via the switching elements T, so that the data sent to the source driver under the control of the gate driver 43 is controlled. Can be switched for each frame.

Next, FIG. 9 shows an example of a circuit configuration of a drive substrate of an active matrix type liquid crystal display panel suitable for application to the circuit of the second embodiment described above. Source wiring D1, D at output terminal
, D3, D4,... Are connected, and gate lines G1, G2, G3, G4, G5, G6,.
Are connected in parallel to the source lines D1, D2, D3, D4,... And adjacent to the odd-numbered source lines D1, D3, D5,. Control lines CB adjacent to the source lines D2, D4, D6,.
Are provided, and one pixel electrode S is provided in a region surrounded by the source wiring D, the gate wiring G, and the control wiring CA or CB, and a region corresponding to these pixel electrodes S is Have been.

In the structure of this example, the gate lines G1, G
, G3, G4, G5, G6,... Are spaced at substantially equal intervals, and a pixel electrode S is provided between these wirings.
A pixel electrode S is disposed on each of the left and right sides of D2, D3, D4,..., And a switching element T such as a thin film transistor is connected to each pixel electrode S and a part of a source wiring or a part of a gate wiring. They are provided in pairs. Furthermore,
Two columns of pixel electrodes S located on the left and right sides of one source line D are connected via switching elements T and T, respectively, and the pixels located on the left and right sides of one source line D are also connected. In each of the electrodes S, a switching element T closer to the source wiring D is connected to the source wiring D, and the other switching element T is connected to a control line C adjacent to each pixel electrode S.

In order to drive the display panel having this configuration, as shown in the timing chart of FIG. 11, the gate lines G1, G2, G3,.
The control line CA is set to the high level, CB is set to the low level, and the switching element T connected to the control line CA is turned on. Next, in the second field, G
1, G2, G3,..., The control line CB is set to a high level, the control line CA is set to a low level, and the switching element T connected to the control line CB is turned on (on). State). By the operation of the source driver 41 'and the control lines CA and CB, the write position of the data sent from the source driver 41' can be switched for each field. That is, in the structure shown in FIG. 9, since two columns of pixel electrodes S are connected to one source wiring via the switching elements T, the data sent to the source driver under the control of the gate driver 43 ' Can be switched for each frame.

<When the data conforms to the VGA standard> As shown in FIG. 6, the original data sent from the video signal generator 26 to the signal processing circuit 45 is latched by the latch circuit 47, and the frequency dividing circuit 48 and the signal selecting circuit Send each to 49. The signal selection circuit 49 determines the resolution, determines that the resolution is VGA, selects the data sent from the latch circuit 47, and sends it to the source driver 41. Next, the timing for sampling the data sent to the source driver 41 is controlled. More specifically, as an example, this can be realized by temporarily stopping the clock of the source driver 41, whereby the data can be thinned. The thinning is switched between the first field and the second field as shown by n and o in FIG. Next, the thinned and sampled data is output to the display panel 40 as described above.

The display panel 40 has the structure shown in FIG. 8 or FIG. 9 described above. The pixel electrodes S in two rows on the left and right sides are connected to one source line via the switching element T. The gate driver 43 or 4
The location where the data sent to the source driver 41 or 41 'is written by the control of 3' (source wiring unit)
Can be switched for each field. Therefore, the output data is 1024 per 1H, and the magnification of the pixel number conversion is 1.6 times, that is, the number of pixels of the VGA standard is XG.
It was possible to drive by converting the number of pixels to the A standard. In this embodiment, the clock frequency of the data of the maximum resolution of the display panel 40 (65 MHz in the case of the XGA standard)
(z, 75 MHz), the use of the frequency dividing circuit 48 in the signal processing circuit 45 can be eliminated.

As described above, in the third embodiment,
By performing the signal processing described above with reference to the structure shown in FIGS. 6 and 8 and FIG. 7, an output corresponding to the resolution of the display panel can be obtained without the need for a separate clock generation circuit which has been conventionally required. Since it can be obtained, it contributes to miniaturization of a circuit and reduction of power consumption, and leads to improvement of reliability as a display device. Furthermore, if the thinning signal is switched for each field or frame, the existence of the thinned data can be averaged over the entire screen, so that a display similar to the original image can be obtained.

Fourth Embodiment In the internal structure of the display panel 40 according to the third embodiment described above, as shown in FIG. 12, an extension line (Dn, D2, D3,...) Extends from one source line Dn (D1, D2, D3...). L1, L2, L3) to supply signals to the three pixel electrodes S. At this time, three gate wirings (G1a, G1b, G1c, G2a, G2b, G2c...
), Signals can be supplied and driven in three fields. By performing such driving, the number of source drivers can be further reduced and the number of pixels in the horizontal direction can be converted. It is needless to say that the signals are thinned out according to the magnification of the conversion of the number of pixels.

[Fifth Embodiment] FIGS. 13 and 14 show a fifth embodiment of the present invention.
Display panel with a resolution of 600 x 1200 pixels), 6
1 is a source driver corresponding to UXGA, 63 is a gate driver, 65 is a signal processing circuit, 67 is a latch circuit, 6
8 is a frequency dividing circuit, 69 is a signal selection circuit (resolution determination circuit), 70 is a horizontal control circuit (horizontal video signal control circuit),
Reference numeral 71 denotes a vertical control circuit (vertical video signal control circuit). Data latch circuits 61a and 61b are provided inside the source driver 61, and data latch circuits 62a and 62b are provided inside the source driver 62.
Are provided, and among the source lines of the liquid crystal display panel 60, the odd-numbered source lines are provided with the data latch circuit 6.
Signals are alternately input from 1a and 61b, and signals are alternately input from the data latch circuits 62a and 62b to the even-numbered source lines in the liquid crystal display panel 60. The configuration of this embodiment is for displaying, for example, UXGA and VGA images on a display driver having a UXGA resolution and a source driver compliant with the UXGA standard whose output number is 1H = 1600.

<When the data is UXGA> The original data (video signal) sent from the video signal generator 26 to the signal processing circuit 65 is latched by the latch circuit 67, and the frequency dividing circuit 6
8 to the signal selection circuit 69. The original data is decomposed into odd-numbered data and even-numbered data by the frequency dividing circuit 68 and sent to the signal selecting circuit 49. The signal selection circuit 49 allows the latch circuit 67
The resolution is determined using the original data sent from, and it is determined that 1H = 1600 UXGA resolution, and the frequency-divided data from the frequency dividing circuit 68 is selected.
The divided data is sent to the two source drivers 61 and 62 via the video signal lines 69a and 69b, respectively. In other words, the source drivers 61 and 62 have the same 2
Send series data. The transmitted data is input to two-system data latch circuits 61a, 61b or 62a, 62b inside the source driver 61 or 62, respectively. By directly displaying the input data on the display panel 60, the UXGA data can be displayed on the UXGA display panel without any trouble.

<When the data is VGA> The original data (video signal) sent from the video signal generator 26 to the signal processing circuit 65 is input to the latch circuit 67, and the frequency dividing circuit 68
To the signal selection circuit 69. The signal selection circuit 69 determines the resolution based on the original data, determines that the resolution of the VGA is 1H = 640, creates exactly the same two series of data sent from the latch circuit 67, and generates two data as it is. It is sent to source drivers 61 and 62. Source driver 6
In steps 1 and 62, the timing for sampling the data sent thereto is controlled. For example, the clocks of the source drivers 61 and 62 are temporarily stopped.
As a result, data can be thinned out.

This control is performed by the respective drivers 61 and 6
2 data latch circuits 61a, 61b, 62a, 62b
Perform each one individually. The thinned and sampled data is output to the display panel 60. The output data is 1
There are 1600 data per H. The magnification of the pixel number conversion is 2.5 times since the conversion is from VGA (640 pixels) to UXGA (1600 pixels). In each of the four data latch circuits, a signal for 640 pixels is converted into a signal for 400 pixels.
By thinning to 00, the total of the four data latch circuits is 4
A signal for 00 × 4 = 1600 pixels can be generated. FIG. 14 shows each data latch circuit 61a, 61b, 62
a, the driver output from 62b is denoted by s, t, u, v,
The display on the liquid crystal panel 60, which is the sum of all the outputs, is indicated by the symbol w in FIG. Note that the data output method of this embodiment is switched over in units of frames (fields) in the same manner as in the previous embodiment, so that the configuration of the data latch circuit can be halved.

As described above, in the fifth embodiment, FIG.
By using the structure shown in FIG. 3 and the signal processing described above with reference to FIG. 14, it is possible to obtain an output corresponding to the resolution without the need for a separate clock generation circuit which has been conventionally required. This contributes to downsizing of a circuit and reduction in power consumption, and leads to improvement in reliability as a display device.

[Sixth Embodiment] The configuration shown in FIG. 1 may be adopted, and the operation processing shown in FIG. 15 may be performed as a timing operation to display an image on the display panel 20. First, the original data is sent to the two source drivers 21 and 22 via the signal line 29.
a, directly via 29b. The data is thinned out by controlling the sampling of digital data in the source drivers 21 and 22. The sampling control here can be individually thinned out and controlled by temporarily stopping the sampling of data by the respective source drivers 21 and 22 by the operation of the horizontal control circuit 30, and the thinned data is switched for each field. To do. Then, the thinned data is displayed on the display panel 20 as it is.
Output to

In this case, the output of the first field of the source driver 21 is indicated by reference numeral b1 in FIG.
The output of the field is indicated by c'1 in FIG. 15, and the output of the second field is indicated by c'2 in FIG. By combining these, the display of the first field can be obtained as indicated by d1 in FIG. 15 and the display of the second field can be obtained as indicated by d2 in FIG. 15. In the liquid crystal panel 20, finally, the display of FIG. The display shown in d can be obtained.

At this time, the data to be thinned out is switched for each field. As a result, two different data are calculated in the frame display, and the average display is obtained by combining the display of the first field and the display of the second field, so that there is an effect of smoothing the gradation of the display image. Such a driving method can of course be applied to other embodiments.

Incidentally, in the above embodiment, 640
VGA (dot) display VGA standard and 1024 × 7
XGA standard of 68 (dot) display and 1600 × 120
Although only the conversion between the 0 (dot) display and the UXGA standard has been described, there are various other types of image display standards for personal computers, and further, various resolutions for TV and video. Therefore, it goes without saying that the drive circuit of the present invention can be applied to all of these. In other words, the resolution can be applied to any resolution change by appropriately adjusting the number of signals to be decomposed or copied and the number to be thinned out according to the conversion rate of the number of pixels.

The resolutions of the personal computer described below are widely known in addition to those described above.
720 × 400 pixels (VGA text), 832 × 62
4 pixels (Macintosh16; Apple Computer, USA), 800 × 600 pixels (SVGA), 1152 × 8
70 pixels (Macintosh 21; trademark of Apple Computer, USA).

The following are widely known as TV resolutions (horizontal resolution × vertical resolution). 352
× 240, 352 × 480, 704 × 480, 720 ×
480 (NTSC format in MPEG2:
DVD), 352 × 288, 352 × 576, 704 ×
576, 720 × 576 (PAL in MPEG2)
Format: DVD), 854 × 480, 944 × 5
12,640 × 480,704 × 480,1280 × 7
20, 1920 × 1080 (above, the standard for digital terrestrial broadcasting in the United States) and 1920 × 1035 (a proposed standard prescribed by the Japan Broadcasting Corporation: HDTV).

Further, FIG. 18 and FIG. 19 list specific numerical values of specific conversion rates in various resolutions. As shown in FIGS. 18 and 19, for example, in order to make 640 pixels 800 pixels, the original data is doubled to 1280 and then 37.5% of the data is thinned out to 800. In order to make 1600 pixels, the data is output after being doubled, and in order to make 1024 pixels of 640 pixels, the original data is doubled to be 1280, and 20% of the data is thinned out to be 1024. As described above, the ratio of the thinned data can be easily calculated from the conversion rates shown in FIGS.

[0066]

As described above, the present invention provides a horizontal video signal control in which a set of sampling timing signals is supplied to a pair of source drivers to generate a horizontal video signal having a predetermined number of horizontal pixels in each source driver. Since the circuit is provided, by adjusting the sampling timing signal, the video signal matched to the display panel resolution can be sent to both source drivers without adding a separate memory and without requiring a separate clock generation circuit. Since they can be combined and sent to a display panel, they contribute to miniaturization of circuits and reduction in power consumption, leading to improvement in reliability as a display device.

Next, according to the present invention, a horizontal video signal is temporally or structurally decomposed into two or more data or duplicated into two or more data to create a plurality of columns of data. It has a horizontal video signal control circuit that combines the pixels or thins them out according to the conversion rate of the number of pixels or combines them as they are, and then outputs them to the display panel, so that the output is adjusted to the resolution without the need for a separate clock generation circuit. Can be obtained. Therefore, it contributes to downsizing of the circuit and reduction of power consumption, leading to improvement in reliability as a display device. In addition, by arbitrarily setting the data to be thinned out according to the conversion ratio of the number of pixels between the input data and the data to be output, it is possible to easily cope with any conversion ratio of the number of pixels. it can.

In the present invention, the data to be thinned out is changed for each field or each frame in accordance with the conversion of the number of pixels from the data of a plurality of columns, so that the data to be thinned out can be easily changed at an arbitrary cycle. . Therefore, the number of data that needs to be processed by the signal processing circuit can be reduced by half, the circuit required by the signal processing circuit can be simplified, and the thinned signal can be averaged as an entire image, which is closer to the original image. A smooth display can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a first embodiment according to the present invention.

FIG. 2 is a signal output diagram of each part of the circuit when driving the circuit of the first embodiment shown in FIG. 1;

FIG. 3A is a diagram illustrating a first example of a vertical driving mode, and FIG. 3B is a diagram illustrating a second example.

FIG. 4 is a diagram showing a circuit configuration of a second embodiment according to the present invention.

5 is a signal output diagram of each part of the circuit when driving the circuit of the second embodiment shown in FIG. 4;

FIG. 6 is a diagram showing a circuit configuration of a third embodiment according to the present invention.

FIG. 7 is a signal output diagram of each part of the circuit when driving the circuit of the third embodiment shown in FIG.

FIG. 8 is a diagram showing a first example of a circuit configuration of a liquid crystal display panel substrate suitable for use in the circuit of the third embodiment.

FIG. 9 is a diagram illustrating a second example of a circuit configuration of a liquid crystal display panel substrate suitable for use in the circuit of the third embodiment.

FIG. 10 is a diagram showing a first example of a timing chart when driving the display panel having the circuit configuration of the third embodiment shown in FIG. 8;

FIG. 11 is a diagram showing a second example of a timing chart when driving the display panel having the circuit configuration of the third embodiment shown in FIG. 8;

FIG. 12 is a diagram showing a circuit configuration of a fourth embodiment according to the present invention.

FIG. 13 is a diagram showing a circuit configuration of a fifth embodiment according to the present invention.

FIG. 14 is a signal output diagram of each part of the circuit when driving the circuit of the fifth embodiment shown in FIG.

FIG. 15 is a timing operation diagram of the sixth embodiment.

FIG. 16 is a diagram showing a circuit configuration of a display device assumed by the present inventors.

17 is a signal output diagram of each part of the drive circuit when driving the circuit shown in FIG.

FIG. 18 is a diagram illustrating an example of the relationship between the size of a display device and the number of pixels of image data.

FIG. 19 is a diagram illustrating another example of the relationship between the size of the display device and the number of pixels of image data.

[Explanation of symbols]

20, 40, 60 ... display panel, 21, 22, 41,
61 ... source driver, 23, 43, 63 ... gate driver, 25, 35, 45, 65 ... signal processing circuit, 2
6 video signal generator, 27, 47, 67 latch circuit, 28, 48, 68 frequency divider circuit 29, 49, 69
..Signal selection circuits (resolution determination circuits), 30, 50, and 70
... Horizontal control circuit (horizontal video signal control circuit), 31, 5
1, 71 ... vertical control circuit.

Claims (6)

[Claims] 1. A pair of source drivers connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplying a horizontal video signal of the predetermined number of horizontal pixels, and the same source by branching the video signal. A video signal line for sending a video signal to each of the source drivers, and a set of sampling timing signals are given to each of the pair of source drivers, and each source driver generates a horizontal video signal having the predetermined number of horizontal pixels. And a horizontal video signal control circuit for driving the image display device. 2. A pair of source drivers which are connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and provide a horizontal video signal of the predetermined number of horizontal pixels, and wherein the video signal is When the number of horizontal pixels is smaller than a predetermined horizontal video signal, the signal is duplicated into two, and when the video signal is the predetermined horizontal video signal, the signal is divided into two, and each of the duplicated or divided video signals is divided into the source driver. And a video signal having the predetermined number of horizontal pixels or a video signal having a smaller number of horizontal pixels than the signal according to the synchronization signal. A resolution discriminating circuit for providing a control signal; a frequency dividing circuit for dividing the video signal into two to supply the divided video signal to the signal selection circuit; Horizontal video signals having a smaller number of pixels than the predetermined number of horizontal pixels at each source driver, and having the predetermined number of horizontal pixels when these horizontal video signals are combined. A driving circuit for an image display device, comprising: a horizontal video signal control circuit for generating a signal. 3. A source driver which is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplies a horizontal video signal of the predetermined number of horizontal pixels, and a video signal which is duplicated to obtain the same video. A video signal line for sequentially transmitting signals to the source driver; and a horizontal signal for sequentially supplying a set of sampling timing signals to the source driver and sequentially generating a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels in the source driver. A driving circuit for an image display device, comprising: a video signal control circuit. 4. A source driver which is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplies a horizontal video signal of the predetermined number of horizontal pixels, and a video signal which is duplicated to obtain the same video. A video signal line for sequentially transmitting signals to the source driver and a set of sampling timing signals are sequentially supplied to the source driver, and the source driver generates a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels. And a horizontal video signal control circuit for changing a position of data to be thinned out from the predetermined number of horizontal pixels for at least one of a field, a line, and a time. 5. A source driver which is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set and supplies a horizontal video signal of the predetermined number of horizontal pixels, When the signal has a smaller number of horizontal pixels than the horizontal video signal, it is duplicated into two, and when the video signal is the predetermined horizontal video signal, it is divided into two, and each of the duplicated or divided video signals is sequentially sent to the source driver. A signal selection circuit to send, a video signal having the predetermined number of horizontal pixels or a video signal having a smaller number of horizontal pixels than this signal is determined in accordance with the synchronization signal, and a control signal indicating whether the video signal is copied or divided is transmitted to the signal selection circuit. A resolution discriminating circuit, a frequency dividing circuit that divides the video signal into two and supplies the divided video signal to the signal selection circuit, and sequentially supplies a set of sampling timing signals to the source driver. A horizontal video signal control circuit for sequentially generating a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels in the source driver and having the number of horizontal pixels when these horizontal video signals are combined; A driving circuit for an image display device, comprising: 6. A source driver which is connected to a display panel in which a predetermined number of horizontal pixels and a predetermined number of vertical pixels are respectively set, and supplies a horizontal video signal of the predetermined number of horizontal pixels, When the number of horizontal pixels is smaller than that of the horizontal video signal, the video signal is divided into two when the video signal is the predetermined horizontal video signal, and each of the duplicated or divided video signals is divided into two by the source driver. A video signal having the predetermined number of horizontal pixels or a video signal having a smaller number of horizontal pixels than this signal in accordance with a synchronization signal, and controlling whether the video signal is to be copied or divided by the signal selection circuit. A resolution discriminating circuit for supplying a signal, a frequency dividing circuit for dividing the video signal into two and supplying the divided video signal to the signal selection circuit, and a set of sampling timing signals to the source driver in order. Next, a source driver generates a horizontal video signal having a smaller number of pixels than the predetermined number of horizontal pixels and a horizontal video signal having the number of horizontal pixels when these horizontal video signals are combined. A driving circuit for an image display device, comprising: a horizontal video signal control circuit for changing a position of data to be thinned out from the number of horizontal pixels for at least one of a field, a line, and time.