JPH11274581A - Thermoelectric conversion element and method of manufacturing the same - Google Patents
Thermoelectric conversion element and method of manufacturing the sameInfo
- Publication number
- JPH11274581A JPH11274581A JP10078940A JP7894098A JPH11274581A JP H11274581 A JPH11274581 A JP H11274581A JP 10078940 A JP10078940 A JP 10078940A JP 7894098 A JP7894098 A JP 7894098A JP H11274581 A JPH11274581 A JP H11274581A
- Authority
- JP
- Japan
- Prior art keywords
- conversion element
- layer
- chip
- thermoelectric conversion
- active layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000006243 chemical reaction Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title description 10
- 239000000758 substrate Substances 0.000 claims abstract description 28
- 238000009413 insulation Methods 0.000 abstract description 7
- 229910052594 sapphire Inorganic materials 0.000 abstract description 5
- 239000010980 sapphire Substances 0.000 abstract description 5
- 239000010410 layer Substances 0.000 description 63
- 238000000034 method Methods 0.000 description 12
- 230000001681 protective effect Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 6
- 238000010248 power generation Methods 0.000 description 5
- 229910019021 Mg 2 Sn Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 239000000969 carrier Substances 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000012159 carrier gas Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- ZSWFCLXCOIISFI-UHFFFAOYSA-N cyclopentadiene Chemical compound C1C=CC=C1 ZSWFCLXCOIISFI-UHFFFAOYSA-N 0.000 description 2
- 238000010292 electrical insulation Methods 0.000 description 2
- 239000011810 insulating material Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 230000005678 Seebeck effect Effects 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910008310 Si—Ge Inorganic materials 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- PZPGRFITIJYNEJ-UHFFFAOYSA-N disilane Chemical compound [SiH3][SiH3] PZPGRFITIJYNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 229910000078 germane Inorganic materials 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000003960 organic solvent Substances 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 238000007789 sealing Methods 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
Landscapes
- Led Devices (AREA)
Abstract
(57)【要約】
【課題】 電気絶縁性や機械的強度に優れた熱電変換素
子を得る。
【解決手段】 サファイア基板１１上に熱電活性層のｎ
型層１２、ｐ型層１３を成長させ、これらを短冊状に切
断してチップを作成し、ｎ型層１２を形成した第１のチ
ップとｐ型層１３を形成した第２のチップを交互に積層
して、ｎ型層１２、ｐ型層１３が電気的に直列に接続さ
れるように電極１４を形成する。
(57) [Problem] To provide a thermoelectric conversion element excellent in electric insulation and mechanical strength. The thermoelectrically active layer is formed on a sapphire substrate.
The mold layer 12 and the p-type layer 13 are grown and cut into strips to form a chip, and the first chip on which the n-type layer 12 is formed and the second chip on which the p-type layer 13 is formed are alternately formed. To form an electrode 14 so that the n-type layer 12 and the p-type layer 13 are electrically connected in series.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は熱エネルギーを電気
エネルギーに変換する熱電変換素子およびその製造方法
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thermoelectric conversion element for converting heat energy into electric energy and a method for manufacturing the same.
【０００２】[0002]
【従来の技術】熱を電気に変換する熱電変換素子は材料
の持つゼーベック効果による熱起電力を取り出そうとす
るものである。このような熱電変換素子には材料として
金属を用いたものと半導体を用いたものとがあり、発電
の目的には通常、半導体を用いたものが利用されてい
る。2. Description of the Related Art A thermoelectric conversion element for converting heat into electricity is intended to extract a thermoelectromotive force due to the Seebeck effect of a material. Such thermoelectric conversion elements include those using a metal as a material and those using a semiconductor, and those using a semiconductor are generally used for power generation.
【０００３】半導体を用いた熱電変換素子においては、
一対のｐｎ接合から取り出せる電力は数十ｍＷ程度から
１Ｗ程度と小さいものであり、大規模な発電のみなら
ず、一般家庭で利用するような電力を得ようとする場合
でも数千個から数万個の素子を直列あるいは並列に接続
して発電する必要がある。このような場合、従来は一組
のｐｎ接合を形成してそれらを接合する方法が一般的で
あった。In a thermoelectric conversion element using a semiconductor,
The electric power that can be extracted from the pair of pn junctions is as small as about tens of mW to about 1 W, so that not only large-scale power generation but also thousands to tens of thousands of electric power used for general households can be obtained. It is necessary to connect the elements in series or in parallel to generate power. In such a case, conventionally, a method of forming a pair of pn junctions and joining them is common.
【０００４】この方法における問題点としては、素子の
接合を効率的に行なう手段が開発されていないという点
と素子間の電気絶縁性をどのように確保するかという
点、さらにはモジュールとしての機械的強度をどのよう
に保つかという点等が挙げられる。[0004] Problems with this method include the fact that means for efficiently joining the elements have not been developed, how to ensure electrical insulation between the elements, and the machine as a module. And how to maintain the target strength.
【０００５】電気絶縁性と機械的強度に関しては、素子
間の間隙に樹脂等の電気絶縁材料を充填する方法や真空
絶縁を行なう方法が考えられている。しかし前者は高温
で発電する素子に用いることが難しく、後者は機械的強
度の確保や真空封じ技術における問題点が存在してい
る。[0005] Regarding the electric insulation and the mechanical strength, a method of filling an electric insulating material such as a resin into a gap between elements and a method of performing vacuum insulation have been considered. However, it is difficult to use the former for an element that generates power at a high temperature, and the latter has problems in securing mechanical strength and vacuum sealing technology.
【０００６】[0006]
【発明が解決しようとする課題】上述したように、従来
の熱電変換素子においては電気絶縁性や機械的強度の問
題が存在していた。本発明はこのような問題を解決する
ためになされたもので、電気絶縁性や機械的強度に優れ
た熱電変換素子およびその製造方法を提供することを目
的とする。As described above, the conventional thermoelectric conversion elements have problems of electrical insulation and mechanical strength. The present invention has been made to solve such a problem, and an object of the present invention is to provide a thermoelectric conversion element excellent in electric insulation and mechanical strength and a method for manufacturing the same.
【０００７】[0007]
【課題を解決するための手段】上記の問題を解決するた
めに本発明は請求項１の発明として、第１導電型熱電活
性層と、第２導電型熱電活性層と、前記第１および第２
導電型熱電活性層間に形成され前記第１および第２導電
型熱電活性層よりも熱伝導率が小さい電気絶縁性の基板
と、前記第１および第２導電型熱電活性層を電気的に直
列に接続する電極とを備えた熱電変換素子を提供する。In order to solve the above problems, the present invention provides a first conductive type thermoelectric active layer, a second conductive type thermoelectric active layer, and the first and second conductive type thermoelectrically active layers. 2
An electrically insulating substrate formed between conductive type thermoelectrically active layers and having a lower thermal conductivity than the first and second conductive type thermoelectrically active layers, and the first and second conductive type thermoelectrically active layers are electrically connected in series. Provided is a thermoelectric conversion element including an electrode to be connected.
【０００８】また請求項２の発明として、前記第１およ
び第２導電型熱電活性層がそれぞれ複数形成されている
請求項１記載の熱電変換素子を提供する。さらに請求項
３の発明として、前記第１および／または第２導電型熱
電活性層が量子井戸構造を有する請求項１、２記載の熱
電変換素子を提供する。According to a second aspect of the present invention, there is provided the thermoelectric conversion element according to the first aspect, wherein a plurality of the first and second conductive type thermoelectric active layers are respectively formed. According to a third aspect of the present invention, there is provided the thermoelectric conversion element according to the first or second aspect, wherein the first and / or second conductive type thermoelectric active layers have a quantum well structure.
【０００９】また本発明の請求項４に係る発明は熱電変
換素子の製造方法であり、電気絶縁性の基板上にこの基
板よりも熱伝導率が大きい第１導電型熱電活性層を形成
して第１のチップを形成する工程と、電気絶縁性の基板
上にこの基板よりも熱伝導率が大きい第２導電型熱電活
性層を形成して第２のチップを形成する工程と、前記第
１および第２のチップを積層する工程と、前記第１およ
び第２導電型熱電活性層を電気的に直列に接続するよう
に電極を形成する工程とを備えたことを特徴とするもの
である。According to a fourth aspect of the present invention, there is provided a method for manufacturing a thermoelectric conversion element, comprising forming a first conductivity type thermoelectric active layer having a higher thermal conductivity than an electrically insulating substrate on the substrate. Forming a first chip; forming a second conductive type thermoelectric active layer having a higher thermal conductivity than the substrate on an electrically insulating substrate to form a second chip; And a step of laminating a second chip, and a step of forming an electrode so as to electrically connect the first and second conductive type thermoelectric active layers in series.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図面
を参照しつつ説明する。なお以下の実施の形態において
は第１導電型をｎ型、第２導電型をｐ型としている。 （第１の実施の形態）図１に本発明の第１の実施の形態
に係る熱電変換素子の製造工程概略斜視断面図を示す。
本実施の形態においては熱電活性層にＭｇとＳｉまたは
Ｇｅによる混晶系の材料を用いる。Embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type. (First Embodiment) FIG. 1 is a schematic perspective sectional view showing a manufacturing process of a thermoelectric conversion element according to a first embodiment of the present invention.
In the present embodiment, a mixed crystal material of Mg and Si or Ge is used for the thermoelectric active layer.
【００１１】まず図１（ａ）に示すように、熱電活性層
に比べて熱伝導率の低い電気絶縁性の基板としてサファ
イアを用いた基板１１を用意し、シクロペンタジエン、
ゲルマン、ジシランを原料とする気相成長法によりＭｇ
2 Ｇｅ0.2 Ｓｉ0.8 層を基板１１上に積層する。このＭ
ｇ2 Ｇｅ0.2 Ｓｉ0.8 層にアンチモンを添加することに
より第１導電型熱電活性層としてのｎ型層１２が、ボロ
ンを添加することにより第２導電型熱電活性層としての
ｐ型層１３がそれぞれ形成される。これらのｎ型層１
２、ｐ型層１３のキャリア濃度は１０19ｃｍ-3オーダー
とする。First, as shown in FIG. 1A, a substrate 11 using sapphire is prepared as an electrically insulating substrate having a lower thermal conductivity than the thermoelectric active layer, and cyclopentadiene,
Mg by vapor phase growth using germane and disilane as raw materials
A 2 Ge 0.2 Si 0.8 layer is laminated on the substrate 11. This M
By adding antimony to the g 2 Ge 0.2 Si 0.8 layer, the n-type layer 12 as the first conductivity type thermoelectric active layer is formed, and by adding boron, the p-type layer 13 as the second conductivity type thermoelectric active layer is formed. It is formed. These n-type layers 1
2. The carrier concentration of the p-type layer 13 is on the order of 10 19 cm −3 .
【００１２】次に、図１（ｂ）に示すように、ｎ型層１
２、ｐ型層１３を成長させた基板１１を所望の幅を持つ
短冊状のチップに切断して、ｎ型層１２を形成した第１
のチップとｐ型層１３を形成した第２のチップを得る。
これらの切断したチップの図中のＡで示す端面に、図示
せぬ有機保護膜あるいは絶縁性被膜を被覆する。Next, as shown in FIG.
2. First, the substrate 11 on which the p-type layer 13 has been grown is cut into strip-shaped chips having a desired width to form the n-type layer 12.
And a second chip on which the p-type layer 13 is formed.
An end face indicated by A in the figure of these cut chips is coated with an organic protective film or an insulating film (not shown).
【００１３】その後、図１（ｃ）に示すように、第１、
第２のチップを交互に積層する。この際に、ｎ型層１２
を形成した第１のチップの保護膜で覆われていない端面
がそれを挟むｐ型層１３を形成した第２のチップの保護
膜で覆われた端面よりも凹、反対にｐ型層１３を形成し
た第２のチップの保護膜で覆われていない端面はこれを
挟むｎ型層１２を形成した第１のチップの保護膜で覆わ
れた端面よりも凹となるように積層する。これらの積層
したチップの保護膜で覆われていない端面、すなわち凹
部となっている部分に金属を埋め込む。この際に保護膜
で覆われている端面上にも金属が被着される。この後、
保護膜を有機溶剤等で溶解させる、いわゆるリフトオフ
の手法によって保護膜上に被着された金属を除去して電
極１４が形成され、電極１４によってｎ型層１２、ｐ型
層１３が電気的に直列に接続されるようになる。Thereafter, as shown in FIG.
Second chips are alternately stacked. At this time, the n-type layer 12
The end face of the first chip, which is not covered with the protective film, is more concave than the end face of the second chip, on which the p-type layer 13 sandwiching it is formed, and the p-type layer 13 is oppositely formed. The end face of the formed second chip which is not covered with the protective film is laminated so as to be more concave than the end face covered with the protective film of the first chip on which the n-type layer 12 is formed. Metal is buried in the end faces of these stacked chips that are not covered with the protective film, that is, in the recessed portions. At this time, metal is also deposited on the end face covered with the protective film. After this,
The electrode 14 is formed by removing the metal deposited on the protective film by a so-called lift-off method in which the protective film is dissolved with an organic solvent or the like, and the electrode 14 electrically connects the n-type layer 12 and the p-type layer 13. It will be connected in series.
【００１４】このようにして形成された電極１４上に図
示せぬ絶縁膜を形成して、図示せぬ伝熱板で挟み込むこ
とにより、本実施の形態に係る熱電変換素子が完成す
る。本実施の形態によれば、熱電活性層の間に電気絶縁
性の基板を用いるため、電気絶縁性の優れた熱電変換素
子を得ることができる。An insulating film (not shown) is formed on the electrode 14 thus formed, and is sandwiched between heat transfer plates (not shown) to complete the thermoelectric conversion element according to the present embodiment. According to the present embodiment, since an electrically insulating substrate is used between the thermoelectrically active layers, a thermoelectric conversion element having excellent electric insulation can be obtained.
【００１５】また、従来の樹脂等の電気絶縁材料を間隙
に埋め込む方法と比較して製造工程が簡略化されると共
に、樹脂を用いる場合と比較して、熱電活性層の間に熱
電活性層よりも熱伝導性の低い基板を用いるため、高温
での使用が可能となる。Further, the manufacturing process is simplified as compared with the conventional method of embedding an electric insulating material such as a resin in the gap, and the thermoelectric active layer is disposed between the thermoelectric active layers as compared with the case where a resin is used. Since a substrate having low thermal conductivity is used, it can be used at a high temperature.
【００１６】さらに従来の真空絶縁を行なう方法と比較
すると、熱電活性層の間に基板を用いて間隙のない熱電
変換素子を得ることができるため、機械的強度が向上す
る。これらに加えて各熱電活性層に直接接する形で電気
絶縁性の基板が存在するので、各熱電活性層に付加され
る熱歪みが緩和されるという効果も得られる。Further, as compared with the conventional method of performing vacuum insulation, a thermoelectric conversion element having no gap can be obtained by using a substrate between thermoelectrically active layers, so that the mechanical strength is improved. In addition, since the electrically insulating substrate exists in direct contact with each thermoelectric active layer, the effect of reducing thermal strain applied to each thermoelectric active layer is also obtained.
【００１７】なおチップを積層する際に、各チップの積
層する面を鏡面となるように処理した上で積層し、その
後に熱処理をすることにより、いわゆるシリコンウェハ
の直接接着と同様の現象を生じさせて各チップを一体化
することも可能である。このような処理を行なうことで
各チップの接合強度がさらに向上し、その結果として熱
歪みがさらに緩和した熱電変換素子が得られる。When stacking chips, the chips are stacked so that the surfaces to be stacked are mirror-finished, and then heat-treated. This causes a phenomenon similar to the so-called direct bonding of silicon wafers. Then, each chip can be integrated. By performing such processing, the bonding strength of each chip is further improved, and as a result, a thermoelectric conversion element with further reduced thermal distortion is obtained.
【００１８】（第２の実施の形態）図２に本発明の第２
の実施の形態に係る熱電変換素子に用いられるチップの
概略断面図を示す。本実施の形態は第１の実施の形態に
おける熱電活性層のｎ型層１２、ｐ型層１３を量子井戸
構造としたものである。(Second Embodiment) FIG. 2 shows a second embodiment of the present invention.
1 is a schematic sectional view of a chip used for a thermoelectric conversion element according to an embodiment. In this embodiment, the n-type layer 12 and the p-type layer 13 of the thermoelectric active layer in the first embodiment have a quantum well structure.
【００１９】図中、２１はサファイアを用いた基板であ
り、基板２１上に熱電活性層を積層する際に、Ｍｇ2 Ｇ
ｅ0.2 Ｓｉ0.8 層２２を積層した後、Ｍｇ2 Ｓｎ0.1 Ｇ
ｅ0.2 Ｓｉ0.7 層２３を積層し、この上にさらにＭｇ2
Ｇｅ0.2 Ｓｉ0.8 層２４を積層する。In the figure, reference numeral 21 denotes a substrate using sapphire. When a thermoelectric active layer is laminated on the substrate 21, Mg 2 G
After the e 0.2 Si 0.8 layer 22 is laminated, the Mg 2 Sn 0.1 G
e 0.2 Si 0.7 layer 23 is laminated, and further Mg 2
A Ge 0.2 Si 0.8 layer 24 is laminated.
【００２０】このような構造を有するとＭｇ2 Ｓｎ0.1
Ｇｅ0.2 Ｓｉ0.7 層２３の禁制帯幅がＭｇ2 Ｇｅ0.2 Ｓ
ｉ0.8 層２２、２４の禁制帯幅よりも狭くなり、いわゆ
る量子井戸構造となる。この構造では高温部で発生した
キャリアがＭｇ2 Ｓｎ0.1 Ｇｅ0.2 Ｓｉ0.7 層２３、す
なわち井戸層に落ち込み、ｎ型では伝導帯を電子が、ｐ
型では価電子帯をホールが二次元キャリアガスとして高
い移動度を持って輸送される。従って、Ｍｇ2 Ｇｅ0.2
Ｓｉ0.8 層２２、２４、すなわちバリア層のキャリア濃
度を低くしてもキャリアを輸送できるだけの速度を得る
ことができるようになる。With such a structure, Mg 2 Sn 0.1
The forbidden band width of the Ge 0.2 Si 0.7 layer 23 is Mg 2 Ge 0.2 S
The band gap becomes narrower than the forbidden band width of the i 0.8 layers 22 and 24, and a so-called quantum well structure is formed. In this structure, carriers generated in the high-temperature portion fall into the Mg 2 Sn 0.1 Ge 0.2 Si 0.7 layer 23, that is, the well layer.
In the type, holes are transported with high mobility in the valence band as a two-dimensional carrier gas. Therefore, Mg 2 Ge 0.2
Even if the carrier concentration of the Si 0.8 layers 22 and 24, that is, the carrier concentration of the barrier layer is reduced, it is possible to obtain a speed enough to transport the carriers.
【００２１】ここで、熱電変換における発電材料の性能
を評価するために用いられる性能指数Ｚは以下の式
（１）で表わされる。 Ｚ＝α２／（ρκ） （１） 式（１）において、αはゼーベック係数、ρは電気抵抗
率、κは熱伝導率を示す。Here, the performance index Z used to evaluate the performance of the power generation material in thermoelectric conversion is represented by the following equation (1). Z = α2 / (ρκ) (1) In equation (1), α represents the Seebeck coefficient, ρ represents the electrical resistivity, and κ represents the thermal conductivity.
【００２２】キャリア濃度が高くなると熱伝導率が増大
し、その結果としてＺは低下してしまう。しかし本実施
の形態では、バリア層のキャリア濃度を低くしてもキャ
リアを輸送できるだけの速度を得ることができるため、
Ｚが低下することを抑制することができる。As the carrier concentration increases, the thermal conductivity increases, and as a result, Z decreases. However, in this embodiment mode, even if the carrier concentration of the barrier layer is reduced, a speed enough to transport carriers can be obtained.
Z can be prevented from decreasing.
【００２３】すなわち、二次元キャリアガスによるキャ
リア輸送現象を用いて、キャリアの輸送量を低下させる
ことなく熱伝導率を低下させることが可能となり、その
ため高いＺを得ることができるようになる。That is, the thermal conductivity can be reduced without lowering the transport amount of the carrier by using the carrier transport phenomenon by the two-dimensional carrier gas, so that a high Z can be obtained.
【００２４】また井戸層とバリア層との界面においてフ
ォノンが散乱され、これによっても熱伝導率が低下する
ため、Ｚが高くなる。これらの結果としてＺが高めら
れ、発電効率が向上する。In addition, phonons are scattered at the interface between the well layer and the barrier layer, which also lowers the thermal conductivity, thereby increasing Z. As a result, Z is increased, and power generation efficiency is improved.
【００２５】以上のような量子井戸構造を基板上に作成
し、その上で第１の実施の形態に示したような方法によ
り熱電変換素子を製造することで、第１の実施の形態と
同様な効果が得られる他、第１の実施の形態と比較し
て、より高い発電効率の熱電変換素子を得ることができ
る。The quantum well structure as described above is formed on a substrate, and a thermoelectric conversion element is manufactured by the method described in the first embodiment. In addition to the above advantages, it is possible to obtain a thermoelectric conversion element having higher power generation efficiency as compared with the first embodiment.
【００２６】（第３の実施の形態）図３に本発明の第３
の実施の形態に係る熱電変換素子に用いられるチップの
製造工程一部概略斜視断面図を示す。本実施の形態では
基板に凸部を設けて、これにより素子を分割する。(Third Embodiment) FIG. 3 shows a third embodiment of the present invention.
2 is a schematic perspective sectional view showing a part of a manufacturing process of a chip used for the thermoelectric conversion element according to the embodiment. In this embodiment mode, a projection is provided on the substrate, and the element is divided by the projection.
【００２７】まず図３（ａ）に示すように、サファイア
を用いた基板３１にエッチング等の方法により短冊状の
凸部３２を形成する。そして図３（ｂ）に示すように、
凸部３２により分離される形で、基板３１上にｎ型もし
くはｐ型の熱電活性層３３を形成する。First, as shown in FIG. 3A, a strip-shaped convex portion 32 is formed on a substrate 31 using sapphire by etching or the like. Then, as shown in FIG.
An n-type or p-type thermoelectric active layer 33 is formed on the substrate 31 so as to be separated by the projections 32.
【００２８】この凸部３２は基板３１に複数個形成して
も良い。また熱電活性層３３は第１の実施の形態のよう
な単一の層でも良いし、第２の実施の形態のような積層
された量子井戸構造でも良い。A plurality of the projections 32 may be formed on the substrate 31. The thermoelectric active layer 33 may be a single layer as in the first embodiment, or may be a stacked quantum well structure as in the second embodiment.
【００２９】このようにして熱電活性層３３を形成した
チップを積層する。ｎ型の熱電活性層３３を形成した第
１のチップとｐ型の熱電活性層３３を形成した第２のチ
ップとを交互に積層して、その後、第１の実施の形態と
同様な方法で熱電変換素子を製造する。The chips on which the thermoelectrically active layers 33 are formed in this manner are stacked. The first chip on which the n-type thermoelectric active layer 33 is formed and the second chip on which the p-type thermoelectric active layer 33 is formed are alternately stacked, and thereafter, the same method as in the first embodiment is used. A thermoelectric conversion element is manufactured.
【００３０】本実施の形態によっても第１の実施形態と
同様な効果が得られ、熱電活性層を量子井戸構造とした
場合には第２の実施の形態と同様な効果が得られる。そ
の上で本実施の形態の特徴は、ｐｎ接合を並列に並べて
高電流の素子を製造しようとする場合に、ｐｎ接合によ
る並列構造を、基板に凸部を設ける工程以外は、ｐｎ接
合が直列に接続されたのみの素子である第１の実施の形
態と同様な工程で製造できることにある。さらには、素
子が大きくなると、不良チップが生じた場合に通電不能
となる部分が大きくなるが、本実施の形態を適用して基
板の凸部によって並列にｐｎ接合が形成されるようにし
ておけば、この問題を回避することが可能となる。According to this embodiment, the same effect as that of the first embodiment can be obtained. When the thermoelectric active layer has a quantum well structure, the same effect as that of the second embodiment can be obtained. The feature of the present embodiment is that when a high current element is to be manufactured by arranging pn junctions in parallel, a parallel structure using pn junctions is used. The device can be manufactured by the same process as in the first embodiment, which is an element only connected to the device. Further, when the size of the element increases, a portion where current cannot be supplied when a defective chip occurs increases. However, by applying this embodiment, the pn junction is formed in parallel by the convex portion of the substrate. Thus, this problem can be avoided.
【００３１】以上、本発明の実施の形態を説明したが、
本発明は上述の実施の形態に限定されるものではない。
上述の実施の形態ではＭｇ―ＳｉＧｅＳｎ系の熱電材料
を用いた例について説明したが、Ｓｉ―Ｇｅ系、ＰｂＴ
ｅ系、Ｚｎ―Ｓｂ系、スクッテルダイト型結晶系、Ｂｉ
―Ｔｅ系等の材料を用いることも可能である。また、基
板としてサファイアを用いた例について説明したが、基
板上に形成する熱電材料に比べて熱伝導率が小さく、電
気絶縁性であるという条件を満足する基板であれば他の
基板を用いても良い。その他、本発明の要旨を逸脱しな
い範囲で種々の変形が可能である。The embodiment of the present invention has been described above.
The present invention is not limited to the above embodiment.
In the above-described embodiment, an example using a Mg-SiGeSn-based thermoelectric material has been described. However, a Si-Ge-based, PbT
e system, Zn-Sb system, skutterudite type crystal system, Bi
-It is also possible to use a material such as Te. Also, an example in which sapphire is used as a substrate has been described. Is also good. In addition, various modifications can be made without departing from the gist of the present invention.
【００３２】[0032]
【発明の効果】以上説明したように本発明によれば、電
気絶縁性や機械的強度に優れた熱電変換素子およびその
製造方法を提供することができる。As described above, according to the present invention, it is possible to provide a thermoelectric conversion element excellent in electric insulation and mechanical strength and a method for manufacturing the same.
【図１】 本発明の第１の実施の形態に係る熱電変換素
子の製造工程概略斜視断面図。FIG. 1 is a schematic perspective sectional view of a manufacturing process of a thermoelectric conversion element according to a first embodiment of the present invention.
【図２】 本発明の第２の実施の形態に係る熱電変換素
子に用いられるチップの概略断面図。FIG. 2 is a schematic sectional view of a chip used for a thermoelectric conversion element according to a second embodiment of the present invention.
【図３】 本発明の第３の実施の形態に係る熱電変換素
子に用いられるチップの製造工程一部概略斜視断面図。FIG. 3 is a schematic perspective sectional view showing a part of a manufacturing process of a chip used for a thermoelectric conversion element according to a third embodiment of the present invention.
１１、２１、３１…基板 １２…ｎ型層 １３…ｐ型層 １４…電極 ２２、２４…Ｍｇ2 Ｇｅ0.2 Ｓｉ0.8 層 ２３…Ｍｇ2 Ｓｎ0.1 Ｇｅ0.2 Ｓｉ0.7 層２３ ３２…凸部 ３３…熱電活性層11, 21, 31 ... substrate 12 ... n-type layer 13 ... p-type layer 14 ... electrode 22, 24 ... Mg 2 Ge 0.2 Si 0.8 layer 23 ... Mg 2 Sn 0.1 Ge 0.2 Si 0.7 layer 23 32 ... convex part 33 ... thermoelectric Active layer
Claims (4)
第１および第２導電型熱電活性層よりも熱伝導率が小さ
い電気絶縁性の基板と、 前記第１および第２導電型熱電活性層を電気的に直列に
接続する電極とを備えた熱電変換素子。A first conductive type thermoelectric active layer; a second conductive type thermoelectric active layer; a first conductive type thermoelectric active layer formed between the first and second conductive type thermoelectric active layers; A thermoelectric conversion element comprising: an electrically insulating substrate having a small thermal conductivity; and an electrode for electrically connecting the first and second conductive type thermoelectric active layers in series.
それぞれ複数形成されている請求項１記載の熱電変換素
子。2. The thermoelectric conversion element according to claim 1, wherein a plurality of the first and second conductive type thermoelectric active layers are formed.
活性層が量子井戸構造を有する請求項１、２記載の熱電
変換素子。3. The thermoelectric conversion element according to claim 1, wherein said first and / or second conductivity type thermoelectric active layer has a quantum well structure.
伝導率が大きい第１導電型熱電活性層を形成して第１の
チップを形成する工程と、 電気絶縁性の基板上にこの基板よりも熱伝導率が大きい
第２導電型熱電活性層を形成して第２のチップを形成す
る工程と、 前記第１および第２のチップを積層する工程と、 前記第１および第２導電型熱電活性層を電気的に直列に
接続するように電極を形成する工程とを備えた熱電変換
素子の製造方法。Forming a first chip by forming a first conductivity type thermoelectric active layer having a higher thermal conductivity on the electrically insulating substrate to form a first chip; and forming the first chip on the electrically insulating substrate. Forming a second chip by forming a second conductive type thermoelectric active layer having a higher thermal conductivity than the substrate; stacking the first and second chips; and forming the first and second conductive layers. Forming an electrode so as to electrically connect the thermoelectrically active layers in series with each other.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10078940A JPH11274581A (en) | 1998-03-26 | 1998-03-26 | Thermoelectric conversion element and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10078940A JPH11274581A (en) | 1998-03-26 | 1998-03-26 | Thermoelectric conversion element and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11274581A true JPH11274581A (en) | 1999-10-08 |
Family
ID=13675891
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10078940A Pending JPH11274581A (en) | 1998-03-26 | 1998-03-26 | Thermoelectric conversion element and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH11274581A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002530874A (en) * | 1998-11-13 | 2002-09-17 | エイチアイ−ゼット・テクノロジー・インク | Quantum well thermoelectric materials on ultra-thin substrates |
| DE10112383A1 (en) * | 2001-03-15 | 2002-10-02 | Karlsruhe Forschzent | Thermal generator for producing thermo-electric power has a single thermal element made of a square carrier body of dielectric material with dimensional stability and a side with a layer of electric potential. |
| WO2012114650A1 (en) | 2011-02-22 | 2012-08-30 | Panasonic Corporation | Thermoelectric conversion element and producing method thereof |
| JP2018174273A (en) * | 2017-03-31 | 2018-11-08 | トヨタ自動車株式会社 | Thermoelectric conversion material and manufacturing method therefor |
-
1998
- 1998-03-26 JP JP10078940A patent/JPH11274581A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002530874A (en) * | 1998-11-13 | 2002-09-17 | エイチアイ−ゼット・テクノロジー・インク | Quantum well thermoelectric materials on ultra-thin substrates |
| DE10112383A1 (en) * | 2001-03-15 | 2002-10-02 | Karlsruhe Forschzent | Thermal generator for producing thermo-electric power has a single thermal element made of a square carrier body of dielectric material with dimensional stability and a side with a layer of electric potential. |
| DE10112383B4 (en) * | 2001-03-15 | 2004-01-29 | Forschungszentrum Karlsruhe Gmbh | Thermocouple and thermogenerator built from it |
| EP1249878A3 (en) * | 2001-03-15 | 2006-05-24 | Forschungszentrum Karlsruhe GmbH | Thermoelectric element and thermoelectric generator |
| WO2012114650A1 (en) | 2011-02-22 | 2012-08-30 | Panasonic Corporation | Thermoelectric conversion element and producing method thereof |
| US9219214B2 (en) | 2011-02-22 | 2015-12-22 | Panasonic Intellectual Property Management Co., Ltd. | Thermoelectric conversion element and producing method thereof |
| JP2018174273A (en) * | 2017-03-31 | 2018-11-08 | トヨタ自動車株式会社 | Thermoelectric conversion material and manufacturing method therefor |
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