JPH11274451A - Solid-state image pick up device and its drive - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a solid-state image pick up device which provides a microminiaturized pixel structure having a high sensitivity, by achieving a high numerical aperture and a high signal charge - signal voltage conversion gain. SOLUTION: This image pick up device is provided with a photoelectric conversion means 3 which is formed on a semiconductor substrate for photoelectric conversion, a resetting means 9 for resetting accumulated signal charges, an amplifying transistor 20 which is modulated by the signal charge, and a line selecting means for selecting a line to read. The image pick up device has at least one of the following constitutions; a first constitution is provided with the line selecting means 8 which has a line selecting channel structure composed of a low-concentration impurity layer of the same conductivity type as that of the semiconductor substrate, and the potential of the line selecting channel structure is modulated by the potential of the drain of the amplifying transistor 20, and a second constitution is provided with the resetting means 9 which has a reset channel structure composed of a low-concentration impurity layer of the same conductivity type as that of the semiconductor substrate, and the potential of the reset channel structure is modulated by the potential of the drain of the amplifying transistor 20.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a solid-state image pickup device and a driving device thereof, and more particularly to a row selection structure and a reset structure inside a unit pixel of the solid-state image pickup device, which has a high aperture ratio and a high signal charge-signal voltage conversion. The present invention relates to a solid-state imaging device capable of providing a highly sensitive miniaturized pixel structure by realizing a gain and a driving device thereof.

[0002]

2. Description of the Related Art A solid-state imaging device having an amplifying function inside a pixel by modulating the potential of a signal charge accumulating section with a signal charge generated by photoelectric conversion and modulating an amplifying transistor inside the pixel with the potential is amplified. It is called a solid-state imaging device, and can compensate for a decrease in sensitivity due to a decrease in the photodiode area due to a decrease in pixel size. At the same time, since such a solid-state imaging device can be manufactured by a so-called MOS process, its future is expected as a solid-state imaging device capable of mounting an on-chip pulse generation circuit and a signal processing circuit outside the pixel region. ing.

A unit pixel in an amplification type solid-state imaging device is
A photodiode for photoelectric conversion, a reset transistor for initializing the voltage of this photodiode, a transistor for amplification, a transistor for row selection or capacitive coupling, and a photodiode and an amplification transistor gate And the wiring to be connected. As a means for selecting a row, a method of pulse-driving the drain voltage of the amplification transistor (Ishida et al., “160
10,000 pixels BCAST image sensor ”, ITE Technical Re
port, Vol. 20, No. 23, pp. 37-42, 1996) is also possible, but in that case, a reset transistor structure is necessary.

Further, when the photoelectrically converted signal charge is stored for a certain period, a structure for storing the charge is provided in a region different from the photodiode, and a transfer gate is provided between the photodiode and the charge storage unit.

[0005]

In the conventional pixel configuration of the amplification type solid-state imaging device, as a row selection means for signal reading, a method of arranging a row selection transistor structure in series with an amplification transistor or a method of amplifying transistor Any of the methods for forming capacitive coupling between the gate section and the row selection line has been used.

When the first method, that is, a row selection transistor structure, is employed, it is necessary to form a transistor inside the pixel structure. The aperture ratio, which is an important factor that governs the sensitivity of the device, decreases.

On the other hand, in the row selection method based on capacitive coupling, it is possible to avoid the above-described aperture ratio problem by introducing a so-called stack capacitor structure in which capacitive coupling is stacked above the gate structure. But,
The capacitive coupling for row selection is added to the capacitance of the floating diffusion structure, which is constituted by the amplification transistor gate capacitance and the like inside the pixel. As a result, the signal charge-signal voltage conversion gain of the floating diffusion structure is reduced. And the sensitivity is reduced (Y. Iida et al., "A 1 / 4-Inch 330k squa
re pixel progressive scan CMOS active pixel image
sensor ", IEEE Journal of Solid-State Circuits, Vol.
32, No. 12, pp. 2030, 1997).

Of course, in any of the row selecting means, a row selection line connected to a wiring common to each row needs to cross the pixel region for row selection. He himself was one of the factors that reduced the aperture ratio.

Further, in the conventional pixel structure of the amplification type solid-state imaging device, a transistor structure which is turned on by a reset signal pulse from outside the pixel region is used as a structure for resetting signal charges accumulated inside the pixel. Was common.

The internal structure of a pixel when a row selecting means and a resetting means using a transistor structure are used becomes complicated as shown in FIG. 9, and this is a problem particularly when a fine pixel structure is designed (M .Yamawaki et al., "A Pixel Size
Shrinkage of Amplified MOS Imager with Two-Line
Mixing, "IEEE Trans. On Electron Devices, Vol.43,
NO.5, pp.713-719, 1996).

Further, in the amplification type solid-state imaging device,
It is an important technical issue to reduce the fixed pattern noise caused by the characteristic variation of the amplification transistor placed inside the pixel, but it is reported that this fixed pattern noise strongly depends on the gate length of the amplification transistor described above. (M. Yamawaki et al., "A Pixel Size Shrinkageof
Amplified MOS Imager with Two-Line Mixing, "IEEE T
rans.On ElectronDevices, Vol.43, NO.5, pp.713-71
9, 1996). However, with the miniaturization of the pixel structure, the miniaturization of the amplifying transistor structure is also required. Therefore, the occurrence of fixed pattern noise due to the reduction in the gate length of the amplifying transistor has become a problem.

Further, K. Mabuchi et al. Reported an example in which a reset structure was realized by a buried transistor structure (K. Mabuchi et al., "A 5.5 μm CMOS image s
ensor cell utilizing a buried channel ", 1997 Sympo
sium on VLSI TechnologyDigest of Technical papers,
pp.75-76, 1997), but in this report, the photodiode potential is modulated by the capacitive coupling between the photodiode and amplification transistor gate and the line selection line, and as a result, reset operation and line selection are performed. It is shown that the operation is realized by ternary driving of the same wiring, and at the same time, the polysilicon gate structure for resetting is omitted from inside the pixel. However, a row selection line is still required as a wiring crossing the pixel, and the capacity of the so-called floating diffusion for converting a signal charge into a signal voltage increases due to the above-mentioned capacitive coupling. , The signal charge-signal voltage conversion gain is greatly reduced.

The present invention has been made in view of such a problem, and an object thereof is to achieve a high sensitivity miniaturization by achieving a high aperture ratio and a high signal charge-signal voltage conversion gain. An object of the present invention is to provide a solid-state imaging device capable of realizing a pixel structure and a driving device thereof.

[0014]

In order to achieve the above object, a solid-state imaging device according to a first aspect of the present invention comprises a photoelectric conversion means for photoelectric conversion formed on a semiconductor substrate, and a photoelectric conversion means which is stored by the photoelectric conversion. A solid-state imaging device comprising: reset means for resetting the signal charge; an amplification transistor modulated by the signal charge; and a row selection means for selecting a row to be read when reading a signal current from the amplification transistor. The structure of the row selection means is a row selection channel structure made of a low-concentration impurity layer of the same conductivity type as the semiconductor substrate, and the potential of the row selection channel structure is modulated by the potential of the drain of the amplification transistor. The first structure and the structure of the reset means are the same as those of the semiconductor substrate. A is, the potential of the reset channel structure has at least one of the configuration of the second configuration being modulated by the drain potential of the amplifying transistor.

Further, a solid-state imaging device according to a second aspect of the present invention comprises:
The solid-state imaging device according to a first aspect of the present invention has the first and second configurations, wherein a channel length (Ls) of the row selection channel structure is shorter than a channel length (Lr) of the reset channel structure (Ls). <Lr) or the channel impurity concentration (Ns) of the row selection channel structure is lower than the channel impurity concentration (Nr) of the reset channel structure (Ns <Nr).

Further, a solid-state imaging device according to a third aspect of the present invention comprises:
In the solid-state imaging device according to the first aspect, only one active region exists in each unit pixel, and the photoelectric conversion unit, the amplification transistor, the row selection channel structure,
And the reset channel structure are arranged in the same active region.

A solid-state imaging device according to a fourth aspect of the present invention comprises:
In the solid-state imaging device according to the first aspect, only one active region exists in each unit pixel, and amplification is modulated by signal charges generated by photoelectric conversion means inside an active region inside a certain pixel. A transistor is present inside the active region inside the adjacent pixel.

Further, a solid-state imaging device according to a fifth aspect of the present invention comprises:
In the solid-state imaging device according to the first aspect, the amplification transistor, the photoelectric conversion unit, the row selection unit, and the reset unit are formed linearly in a first direction and a second direction opposite to the first direction. A single active region, the unit pixel includes a plurality of active regions, and the active region is shared between adjacent unit pixels in a first direction and a second direction. An amplification gate of the amplification transistor is connected to an active region adjacent in a third direction orthogonal to the first and second directions and in a fourth direction opposite to the third direction, and includes the photoelectric conversion unit. The active region is an active region including the amplifying transistor of the unit pixel adjacent in any one of the first and second directions.

Further, a solid-state imaging device according to a sixth aspect of the present invention comprises:
In the solid-state imaging device according to the first aspect, the unit pixel has no gate structure other than the gate of the amplification transistor.

According to a seventh aspect of the present invention, there is provided a driving apparatus for a solid-state image pickup device, comprising: a photoelectric conversion unit formed on a semiconductor substrate for photoelectric conversion; and a reset unit for resetting signal charges accumulated by the photoelectric conversion. A solid-state imaging device comprising: an amplification transistor modulated by the signal charge; and a row selection unit that selects a row to be read in reading out a signal current from the amplification transistor. Is a row selection channel structure composed of a low-concentration impurity layer of the same conductivity type as the semiconductor substrate, and the potential of this row selection channel structure is modulated by the potential of the drain of the amplification transistor; The structure is a reset channel structure comprising a low-concentration impurity layer of the same conductivity type as that of the semiconductor substrate. A driving device for driving a solid-state imaging device in which a potential of a structure is modulated by a potential of a drain of the amplifying transistor, wherein the pulse for selecting a row and the pulse for resetting are supplied to the amplifying transistor. Superimposing means for superimposing on the drain voltage of
The solid-state imaging device is driven by the superimposed pulse.

[0021]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram of a unit pixel of an amplification type solid-state imaging device according to an embodiment of the present invention, FIG. 2 is an example of a cross-sectional structure for configuring the circuit shown in FIG. 1, and FIG. FIG. 2 is a diagram showing a drain pulse for driving the unit pixel shown in FIG. 1 and a change in the output signal line potential at that time.

As shown in FIGS. 1 and 2, in this embodiment, as a means for realizing the row selection and reset functions, a low impurity concentration channel structure without a gate, that is, a row selection means (row selection channel) 8 And reset means (reset channel 9).

More specifically, in the present embodiment, the structure for selecting a row in signal reading, which is one of the causes of complicating the internal structure of the pixel, is based on a conventional gate drive pulse from outside the pixel region. It is not formed of an operating transistor structure type or a capacitive coupling type, but is formed by a row selection channel 8 constituted by a low-concentration impurity layer of the same conductivity type as the semiconductor substrate. As in the case of (1), they are arranged in series with the amplification transistor 20. The channel length is set short enough and the impurity concentration is set sufficiently low so that the potential of row selection channel 8 is easily modulated by the potential of drain 4 of amplifying transistor 20 adjacent to row selection channel 8. I have. Therefore, by applying an appropriate voltage to the drain 4, the row selection channel potential can be set higher than the dark potential below the gate 1 of the amplification transistor 20, and this state is referred to as a row selection state. Become. FIG. 4 shows a potential distribution diagram during such a row selection operation.

In the present embodiment, the reset structure of the accumulated signal charge, which is one of the causes of the complicated internal structure of the pixel, is a polysilicon gate transistor structure operated by a gate drive pulse from outside the pixel region. Instead, the reset channel 9 is formed of a low-concentration impurity layer of the same conductivity type as that of the semiconductor substrate. The channel length is set short enough and the impurity concentration is set low enough so that it can be easily modulated by the potential. Therefore, by applying an appropriate voltage to the drain 4, the potential of the reset channel 9 can be set as the dark potential of the photoelectric conversion means (photodiode) 3 or the signal charge storage portion. Becomes FIG. 5 is a potential distribution diagram during such a reset operation.

With the above structure, the only polysilicon gate structure required inside the pixel is the only amplifying transistor. The pixel structure is greatly simplified, and the degree of freedom in designing the pixel structure is greatly improved. In particular, the simplification of the pixel structure enables the aperture ratio, which is defined by the ratio of the photodiode area to the pixel area, and is an important index of light sensitivity, to be greatly improved, and therefore significantly increases the sensitivity.

In addition, according to the present embodiment, it is possible to realize a fine pixel structure without causing a short channel of the amplifying transistor which causes an increase in fixed pattern noise. It becomes possible. further,
Since there is no capacitive coupling for line selection or reset, the signal charge-signal voltage conversion gain of the floating diffusion in the pixel does not decrease.

The row selecting operation according to the present embodiment will be described below. In this embodiment, the amplification type solid-state imaging device is driven by superimposing the row selection pulse on the drain voltage of the amplification transistor 20. That is, when an intermediate voltage: Vmiddle shown in FIG. 3 is applied to the drain line 5, the row selection channel 8 having a low impurity concentration adjacent to the drain 4 is formed.
Depletion layer extends and modulates the potential of the end of the amplification transistor gate 1 which is separated from the drain 4 by the distance Ls. At this time, by appropriately designing the relationship between the row selection channel length: Ls, the row selection channel impurity concentration: Ns, and the intermediate voltage: Vmiddle, a potential distribution diagram in row selection as shown in FIG. 4 can be obtained.

During the row selection operation by applying the above-mentioned intermediate voltage: Vmiddle to the drain line 5, a low impurity concentration channel (reset channel) 9 provided between the drain 4 and the photodiode 3 is provided. Are reset channel length: Lr and reset channel impurity concentration: Nr
By appropriately designing the relationship between the signal and the intermediate voltage: Vmiddle, as shown in FIG. 5, it is possible to function as an overflow drain for overflowing signal charges excessively generated inside the photodiode 3 during the row selection operation. is there.

Hereinafter, the reset operation according to the present embodiment will be described. In this embodiment, the amplification type solid-state imaging device is driven by superimposing a reset pulse on the drain voltage of the amplification transistor 20. That is, FIG.
When a high voltage Vhigh as shown in FIG. 1 is applied, a low impurity concentration reset channel 9 adjacent to the drain 4 is applied.
Depletion layer extends and modulates the potential at the end of the photodiode 3 that is separated from the drain 4 by a distance Lr. At this time, by appropriately designing the relationship between the reset channel length: Lr, the reset channel impurity concentration: Nr, and the high voltage: Vhigh, a potential distribution diagram in the reset operation as shown in FIG. 5 can be obtained.

Further, while the reset operation is performed by applying the high voltage: Vhigh to the drain line 5,
The low impurity concentration channel (row selection channel) provided between the drain 4 and the amplification transistor 20 appropriately designs the relationship between the row selection channel length: Ls, the row selection channel impurity concentration: Ns, and the high voltage: Vhigh. By doing so, it is possible to maintain the row selection state as shown in FIG.

FIG. 6 is a plan view of a pixel structure of an amplification type solid-state imaging device according to an embodiment of the present invention, and FIG.
In FIG. 6, the Al wiring structure is omitted for the purpose of making the figure easier to read, and FIG. 6B is a plan view including the Al wiring structure.

This embodiment is an example in which a pixel structure of 5.6 μm × 5.6 μm is designed according to the 0.7 μm rule. In the present embodiment, the reset channel length: Lr
= 0.9 μm and the row selection channel length: Ls = 0.4 μm.

In the present embodiment, in order to realize the above-described row selection operation and reset operation, the channel impurity is set to 2 × 10 ¹⁵ cm ⁻³ , and the pulse voltage applied to the drain 4 is set to Vhigh = 9 [V]. ], Vmiddle
= 5 [V], the row selection operation and the reset operation as shown in FIGS. 4 and 5 become possible. At this time, V
The dark potential of the photodiode 3 set by the high reset operation: φd is 4.2 [V], Vmid
The overflow potential φo set by the row selection operation by dle is 1.2 [V], and these potentials define the dark level and the saturation level, respectively.

The potential at the end of the row selection channel in the row selection operation is 3.8 [V], and the characteristic of the amplification transistor gate 1 is Vth = 0.2 which is a general value.
[V], the potential under the amplification transistor gate 1 at the dark level when the modulation factor = 0.8 (3.2
[V]), the row selection operation shown in FIG. 4 becomes possible.

In this embodiment, the row selection channel 8
And the value of the impurity concentration of the reset channel 9 is equal to the value of the impurity concentration: Ns of the reset channel 9. In this case, the channel length of the row selection channel 8 is L as described above.
The relationship between s and the channel length of the reset channel 9: Lr may be designed such that Lr> Ls, and the drain line 5 may be driven by the pulse voltage as described above.

Conversely, if Lr = Ls is required due to design requirements, the relationship between Ns and Nr is expressed as Ns <N.
By setting r, it is possible to drive similarly. In the present embodiment, since the connection between the amplification transistor gate 1 and the photodiode 3 causes a part of the photodiode 3 to be shielded from light by the Al wiring, the opening area of the photodiode 3 is slightly reduced. But
Nevertheless, an extremely high aperture ratio of 37% can be realized.

Further, another structural feature of the present embodiment is that the gate length of the gate 1 of the amplification transistor 20 (FIG. 2)
La) is designed to be very large. In the amplification type solid-state imaging device, reduction of fixed pattern noise due to variation in characteristics of the amplification transistor 20 disposed inside the pixel is an important technical problem. It has been reported that there is a strong dependence on gate length (M. Yamawaki
et al., "A Pixel Size Shrinkageof Amplified MOS I
mager with Two-Line Mixing, "IEEE Trans. on Electr
onDevices, Vol.43, NO.5 pp.713-719, 1996). However, with the miniaturization of the pixel structure, the miniaturization of the amplifying transistor structure is also required. Therefore, the occurrence of fixed pattern noise due to the reduction of the gate length of the amplifying transistor has become a problem. In the embodiment, La =
Since an extremely large value of 2.0 μm is realized, the above-described fixed pattern noise is significantly reduced.

FIGS. 7 and 8 show a pixel having a size of 3.7 μm × 3.7 μm as an example of a miniaturized pixel configuration.
This is an embodiment laid out according to the μm rule. The basic driving method of the elements having the layouts shown in FIGS. 7 and 8 is the same as that of the above-described driving method, and the description thereof is omitted.

7 and 8, an amplifying transistor gate 1, a reset structure 9, and a photodiode 3 are formed in an active region formed linearly in the left-right direction. It has a structure that shares an area. Further, the configuration is such that the amplification transistor gate 1 modulated by the potential change of the photodiode 3 exists inside the pixel adjacent above.

3.7 μm × 3.7 μm shown in FIGS.
In the extremely fine pixel layout, the gate length (La) of the amplification transistor 20 as shown in FIG.
Although the increase cannot be realized, the aperture ratio of each of the photodiodes 3 realizes a very large value.

In the embodiment of FIG. 7, the reset channel length: Lr = 0.9 μm, the row selection channel length: Ls =
In this case, the aperture ratio of the photodiode 3 is 10.2%.

Also in the case of the present embodiment, in order to realize the above-described row selection operation and reset operation, the channel impurity is set to 2 × 10 ¹⁵ cm ⁻³ , and the pulse voltage applied to the drain 4 is set to Vhigh = 9. [V], Vmiddl
By setting e = 5 [V], the row selection operation and the reset operation as shown in FIGS. At this time, V
The dark potential of the photodiode 3 set by the high reset operation: φd is 4.2 [V], Vmid
The overflow potential φo set by the row selection operation by dle is 1.2 [V], and these potentials define the dark level and the saturation level, respectively.

The potential at the end of the row selection channel in the row selection operation is 3.6 [V], and the characteristic of the amplification transistor gate 1 is Vth = 0.2 which is a general value.
[V], the potential under the amplification transistor gate 1 at the dark level when the modulation factor = 0.8 (3.2
[V]), the row selection operation shown in FIG. 4 becomes possible.

In the embodiment shown in FIG. 8, Lr and Ls are further miniaturized in the same basic structure as in FIG.
r = 0.7 μm and Ls = 0.25 μm. As a result, the aperture ratio of the photodiode 3 is improved to 13.2%.

In this embodiment, in order to realize the above-described row selection operation and reset operation, the channel impurity is set to 5 × 10 ¹⁵ cm ⁻³ , and the pulse voltage applied to the drain 4 is set to Vhigh = 9 [V]. ], Vmiddle
= 5 [V], the row selection operation and the reset operation shown in FIGS. At this time, Vhigh
, The dark potential of the photodiode 3 set by the reset operation due to: φd is 3.2 [V], and the overflow potential set by the row selection operation by Vmiddle:
φo is 1.2 [V], and these potentials define the dark level and the saturation level, respectively. The potential of the end of the row selection channel in the row selection operation is 3.8 [V], and the characteristic of the amplification transistor 1 is Vt which is a general value.
Since h = 0.2 [V] and the modulation level = 0.8, the potential is higher than the potential (2.4 [V]) under the amplification transistor gate 1 at the dark level when darkness is used. Row selection operation becomes possible.

Furthermore, because of such a fine structure and no additional capacitance for row selection,
According to the pixel layouts shown in FIGS. 7 and 8, the floating diffusion capacitance formed by the gate capacitance of the amplification transistor gate 1 and the capacitance of the photodiode 3 is extremely small. Therefore, the signal charge-signal voltage in the floating diffusion structure is reduced. The conversion gain is as high as 30 [μV / electron].

As a modification of the unit pixel structure shown in FIGS. 6, 7, and 8, the connection between the amplification transistor gate 1 and the photodiode 3 is not provided by metal wiring, The amplification transistor 1 can be modulated by capacitive coupling formed between the same material layer and the photodiode 3. According to the modulation structure of the amplification transistor by such a capacitive coupling,
In FIGS. 6, 7, and 8, no light is shielded by the metal wiring that caused a decrease in the aperture ratio, and a high aperture ratio can be maintained for light on a relatively long wavelength side that is not completely absorbed in the gate material layer. . When applied to the structures of FIGS. 6, 7 and 8, the aperture ratios are 40.5%, 17.2%, 2
0.5%.

According to the above-described embodiment of the present invention, a transistor structure for resetting signal charges and a transistor structure for selecting rows, which hindered a reduction in pixel size in a conventional amplification type solid-state imaging device, are not required. Thus, a structure in which only an amplification transistor exists as the only transistor inside the unit pixel is possible, and a fine pixel structure is realized.

Further, since the driving of the amplification type solid-state imaging device having the above structure can be performed by superposing the row selection pulse and the reset pulse on the drain voltage of the amplification transistor, the pixels inside the imaging region and those outside the imaging region can be driven. Only a signal line and a drain line, which are necessary for amplification, are provided at least between the driving unit and the driving unit. This not only facilitates the configuration of the peripheral driving circuit but also minimizes the number of wirings traversing the inside of the pixel.

As a result, the aperture ratio defined by the ratio of the photodiode area to the pixel area inside the pixel can be greatly improved and the sensitivity can be increased as compared with the conventional amplification type solid-state imaging device. Becomes

Further, as compared with the conventional capacitance-coupling type row selection structure, the capacitance added to the capacitance of the floating diffusion structure constituted by the gate capacitance of the amplifying transistor inside the pixel is greatly reduced.
The signal charge-signal voltage conversion gain can be greatly increased, and high sensitivity can be achieved. In addition, various modifications can be made without departing from the spirit of the present invention.

[0052]

According to the present invention, since the internal structure of the pixel in the amplification type solid-state imaging device can be simplified, the degree of freedom in design is greatly improved. As a result, a high photodiode aperture ratio and a high signal It is possible to obtain a charge-signal voltage conversion gain, thereby realizing a highly sensitive miniaturized pixel structure.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram of a unit pixel of an amplification type solid-state imaging device according to an embodiment of the present invention.

FIG. 2 is a sectional structural view of an amplification type solid-state imaging device according to an embodiment of the present invention.

3 is a timing chart illustrating a drain pulse for driving a unit pixel and a change in an output signal line potential at that time according to the configuration of FIG. 1;

FIG. 4 is a potential distribution diagram for explaining a row selection operation in the amplification type solid-state imaging device according to one embodiment of the present invention.

FIG. 5 is a potential distribution diagram for explaining a reset operation in the amplification type solid-state imaging device according to one embodiment of the present invention.

FIG. 6 is a cell layout diagram for explaining a cell layout of the amplification type solid-state imaging device according to one embodiment of the present invention.

FIG. 7 is a cell layout diagram for explaining a cell layout of the amplification type solid-state imaging device according to one embodiment of the present invention.

FIG. 8 is a cell layout diagram for explaining a cell layout of the amplification type solid-state imaging device according to one embodiment of the present invention.

FIG. 9 is a cell layout diagram for explaining a cell layout of a conventional amplification type solid-state imaging device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... Amplification transistor gate 2 ... Contact hole 3 ... Photodiode 4 ... Drain 5 ... Drain line 6 ... Signal output part 7 ... Signal line 8 ... Row selection channel 9 reset channel 12 contact hole 20 amplifying transistor

Claims (3)

[Claims] A photoelectric conversion means for photoelectric conversion formed on a semiconductor substrate; a reset means for resetting signal charges accumulated by the photoelectric conversion; an amplification transistor modulated by the signal charges; A row selecting means for selecting a row to be read in reading a signal current from the amplifying transistor, wherein the row selecting means has the same conductivity type low-concentration impurity as the semiconductor substrate. A row select channel structure comprising layers,
A first structure in which the potential of the row selection channel structure is modulated by the potential of the drain of the amplification transistor; and a reset channel structure in which the structure of the reset means is a low-concentration impurity layer of the same conductivity type as the semiconductor substrate. A solid-state imaging device having at least one of a second configuration in which a potential of the reset channel structure is modulated by a potential of a drain of the amplification transistor. 2. The semiconductor device having both the first and second configurations, wherein a channel length (Ls) of the row selection channel structure is shorter than a channel length (Lr) of the reset channel structure (Lr).
2. The solid-state imaging device according to claim 1, wherein s <Lr, or a channel impurity concentration (Ns) of the row selection channel structure is lower (Ns <Nr) than a channel impurity concentration (Nr) of the reset channel structure. apparatus. 3. A photoelectric conversion means for photoelectric conversion formed on a semiconductor substrate, reset means for resetting signal charges accumulated by the photoelectric conversion, and an amplification transistor modulated by the signal charges. A row selecting means for selecting a row to be read in reading a signal current from the amplifying transistor, wherein the row selecting means has the same conductivity type low-concentration impurity as the semiconductor substrate. A row select channel structure comprising layers,
The potential of the row selection channel structure is modulated by the potential of the drain of the amplification transistor, and the structure of the reset means is a reset channel structure made of the same conductivity type low concentration impurity layer as the semiconductor substrate, A drive device for driving a solid-state imaging device in which the potential of the reset channel structure is modulated by the potential of the drain of the amplification transistor, wherein the pulse for row selection and the pulse for reset are: A driving apparatus for a solid-state imaging device, comprising: superposition means for superimposing on a drain voltage of the amplification transistor, wherein the superimposed pulse drives the solid-state imaging device.