JP3615144B2 - Solid-state imaging device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a solid-state image pickup device, and more particularly to a solid-state image pickup device using a threshold voltage modulation type MOS image sensor used for a video camera, an electronic camera, an image input camera, a scanner, a facsimile, or the like.
[0002]
[Prior art]
Semiconductor image sensors such as CCD image sensors and MOS image sensors are excellent in mass productivity, and are applied to almost all image input device devices with the progress of pattern miniaturization technology.
In particular, in recent years, MOS type image sensors have been reviewed by taking advantage of the fact that the power consumption is small compared to CCD type image sensors and the sensor elements and peripheral circuit elements can be produced by the same CMOS technology.
[0003]
In view of such a trend in the world, the applicant of the present application improved the MOS image sensor and applied for a patent relating to a sensor element having a carrier pocket (high-concentration buried layer) 25 under the channel region of the optical signal detection MOS transistor. (Japanese Patent Application No. 10-186453) has been made to obtain a patent (Registration No. 2935492).
In this MOS type image sensor, as shown in FIG. 13 and FIG. 14 of this application, the unit pixel 101 includes a light receiving diode 111 and an optical signal detecting field effect transistor 112 adjacent to the light receiving diode 111.
[0004]
In the MOS type image sensor, the unit pixels 101 are arranged in rows and columns. Adjacent unit pixels 101 are separated by an element isolation region. The element isolation region includes an insulating isolation region 14 formed on the substrate surface by a LOCOS (LOCal Oxidation of Silicon) method, and a p-type diffusion isolation region 13 formed on the semiconductor substrate therebelow.
[0005]
Using this MOS image sensor, a high reverse voltage is applied to each electrode during the initialization period to cause depletion, and photogenerated holes remaining in the hole pocket 25 are emitted. Irradiating the light collected by the microlens to the light receiving diode 111 during the accumulation period to generate photogenerated holes, move them to accumulate in the hole pocket 25, and in proportion to the accumulated amount of photogenerated holes during the readout period Then, the optical signal is detected by detecting the threshold voltage of the modulated optical signal detecting field effect transistor 112.
[0006]
[Problems to be solved by the invention]
By the way, when the pixel pitch is to be reduced in order to further increase the pixel arrangement, the structure of the peripheral portion of the gate electrode 19 is more complex than that of the light receiving diode 111 portion. The reduction rate is limited. Accordingly, in the present state or the near future, it is considered that the width of the gate electrode 19 is 1/2 or more with respect to the pixel pitch, or 2/3 or more with respect to the pixel pitch when the pixel is further miniaturized.
[0007]
When attempting to reduce the pixel pitch based on such a situation, as shown in FIG. 9, the light receiving portion of the light receiving diode 111 has an elongated rectangular shape. For this reason, when the light condensed by the microlens has a defocusing focus and the light spot diameter is slightly widened, the irradiated light is received in the short side direction of the light receiving unit as shown in FIG. It may protrude from the department. In this case, the amount of incident light is insufficient at both ends in the short side direction, and so-called shading occurs in which the output from the image sensor becomes non-uniform even when a uniform pattern is photographed.
[0008]
In addition, in an imaging apparatus using CCD elements, the resolution is improved by a system such as a three-plate type that receives light by three CCD elements, but a MOS type image sensor can take advantage of the features of low power consumption and small size. It is desired to improve the resolution with a single plate type that receives light by one image sensor.
In addition, there is a demand for further downsizing the entire image sensor by stopping element isolation by LOCOS.
[0009]
The present invention has been created in view of the above-described problems of the prior art, and can reduce the size of the entire image sensor, prevent the occurrence of so-called shading, and improve the resolution with a single plate type. A solid-state imaging device is provided.
[0010]
[Means for Solving the Problems]
In order to solve the above-described problems, the present invention relates to a solid-state imaging device, and as a basic configuration of the solid-state imaging device, as shown in FIGS. 2 and 4, the solid-state imaging device is formed in a first well region 54 a of one conductivity type. Formed in the light receiving diode 111 and the second well region 54b of one conductivity type adjacent to the first well region 54b of the light receiving diode 111 and electrically connected so as to be able to accumulate photogenerated charges generated in the light receiving diode 111. The unit pixel 101 is provided with the insulated gate field effect transistor 112 for optical signal detection.
The gate electrode 59 of the insulated gate field effect transistor 112 has, for example, a ring shape, and an n-type (opposite conductivity type) source region 56 is provided inside the inner peripheral portion of the gate electrode 59. An n-type (opposite conductivity type) drain region 57 a is provided outside the outer periphery of 59. These are provided in the p-type (one conductivity type) second well region 54b. Further, the drain region 57 a is electrically connected to an n-type (opposite conductivity type) impurity region 57 formed on the surface of the first well region 54 a of the light receiving diode 111. As a result, photogenerated charges generated in the light receiving diode 111 are accumulated under the channel region 54c below the gate electrode 59, and the optical signal is detected by modulating the threshold voltage of the channel region 54c in the insulated gate field effect transistor 112. It is characterized by.
[0011]
1, 3, and 5 to 8, the unit pixels 101 are arranged in rows and columns, and the light receiving diodes 111 are connected to the insulated gate field effect transistors 112 of the unit pixels 101. The peripheral portion is surrounded by the insulated gate field effect transistor 112 of the adjacent unit pixel 101, and the insulated gate field effect transistor 112 is connected to the light receiving diode 111 of its own unit pixel 101 and the adjacent unit pixel 101. The light receiving diode 111 is disposed so as to surround the periphery thereof.
In the unit pixel 101, the gate electrodes 59 of the insulated gate field effect transistors 112 in the row direction are connected to each other, and the source regions 56 of the insulated gate field effect transistors 112 in the same column are connected to each other. It is characterized by being. The unit pixel 101 is connected to an adjacent pixel by an n-type (opposite conductivity type) diffusion isolation region (diffusion region) 53 electrically connected to the drain region 57a at least in the same row. .
[0012]
Further, in the planar arrangement of the unit pixels 101 in the solid-state imaging device, in particular, as shown in FIGS. 5 to 8, the light receiving diodes 111 and the gate electrodes 59 are alternately arranged along the row direction and along the column direction. It is characterized by being lined up.
In this case, for example, as shown in FIG. 5, the arrangement of the unit pixels 101 in the same row is linear along the row direction, and the arrangement of the light receiving diodes 111 is zigzag along the row direction. Yes. Further, for example, as shown in FIGS. 6 to 8, in addition to the arrangement of the light receiving diodes 111, the arrangement of the unit pixels 101 in the same row is zigzag along the row direction.
[0013]
Below, the effect | action and effect which are show | played by the said structure are demonstrated.
In the solid-state imaging device according to the present invention, unit pixels 101 each including an insulated gate field effect transistor 112 for optical signal detection are arranged in rows and columns, and the light receiving diode 111 is an insulated gate of its own and adjacent unit pixels. The peripheral portion of the insulated gate field effect transistor 112 is surrounded by the light-receiving diode 111 of its own and adjacent unit pixel. That is, the pixel arrangement shown in FIGS. 1, 3, and 5 to 8 is obtained. In this case, in one pixel 101, a ring-shaped gate electrode 59 whose outer peripheral portion has a polygonal shape or a circular shape having four or more sides is provided, and the light-receiving diode 111 is a polygonal shape of the gate electrode 59. Are provided on at least one side of or adjacent to a part of a circular circumference.
[0014]
In FIG. 1 and FIG. 3, since the inside of the pixel 101 is arranged so that the direction from the gate electrode 59 to the light-receiving diode 111 coincides with the row direction and the column direction, the width of the gate electrode 59 For example, the ratio of the short side to the long side of the quadrangular light-receiving part is close to 1 while maintaining the pixel pitch at 1/2 or more than 2/3 of the pixel pitch. It becomes easy to form the light receiving diode 111 including the light receiving portion.
[0015]
In FIG. 5, the inside of the pixel 101 is arranged so that the direction from the gate electrode 59 to the light receiving diode 111 coincides with the row direction and the column direction. In addition, the arrangement of the light receiving diodes 111 is zigzag along the row direction.
Therefore, in particular in the row direction, the light-receiving diode 111 having a light-receiving portion having a so-called isotropic extension while maintaining the width of the gate electrode 59 at 1/2 or 2/3 or more with respect to the pixel pitch. Easy to form.
[0016]
In FIGS. 6 to 8, the pixel 101 is arranged so that the direction from the gate electrode 59 to the light receiving diode 111 coincides with the row direction and the column direction. In addition, the arrangement of the light receiving diodes 111 and the arrangement of the pixels 101 in the same row are zigzag along the row direction. That is, since the pixel pitch is substantially reduced by about 1/2 pitch in the row and column directions, the width of the gate electrode 59 is held at 1/2 or more or 2/3 or more with respect to the pixel pitch. However, it becomes easy to form the light receiving diode 111 having a light receiving portion having a so-called isotropic spread.
By the way, in the case of FIG. 9 in which the pixels are arranged without any ingenuity, as shown in FIG. 10C, the output of the photoelectric signal from the pixels is lowered due to the irradiation light spot protruding from the light receiving part. To do. On the other hand, in the pixel array as in the present invention, since the light receiving diode 111 having a light receiving portion having a more isotropic spread can be obtained, as shown in FIGS. The occurrence of so-called shading that the output of the photoelectric signal from the pixel decreases due to the spot protruding from the light receiving portion can be prevented.
[0017]
In the planar arrangement of the pixels 101 in the solid-state imaging device, as shown in FIGS. 5 to 8, the light receiving diodes 111 and the gate electrodes 59 are alternately arranged along the row direction and along the column direction. .
In this case, in particular, as shown in FIG. 5, the arrangement of the pixels 101 in the same row is linear along the row direction, and the arrangement of the light receiving diodes 111 is zigzag along the row direction. . In particular, as shown in FIGS. 6 to 8, in addition to the arrangement of the light receiving diodes 111, the arrangement of the pixels 101 in the same row is zigzag along the row direction.
[0018]
The arrangement as shown in FIGS. 5 to 8, that is, the arrangement in which the centers of the light receiving diodes 111 are zigzag has the same effect as the so-called pixel shift in the three-plate type solid-state imaging device using the CCD element. That is, by shifting the arrangement of the light receiving sections in a specific row by 1/2 pitch with respect to the arrangement of the light receiving sections in the upper or lower row, there are substantially further light receiving sections between the light receiving sections. The video signal between the light receiving units is also captured as compared to the video when pixel shifting is not performed. Therefore, the resolution can be improved with a single plate type. In the case of a CCD, in the case of a CCD, the sequential output method is used, so it is considered to be quite difficult. However, in the case of a MOS type element such as the present invention, a video signal is output from pixels in an arbitrary row. Therefore, the resolution can be easily improved by single-plate pixel shifting.
[0019]
A ring-shaped gate electrode 59 is provided, and the inside of the gate electrode 59 is a source region 56 and the outside thereof is a drain region 57a.
Therefore, by forming the element isolation region by the diffusion isolation region 53 having the same conductivity type as that of the drain region 57a and connecting to the drain region 57a, it is not necessary to use element isolation by the LOCOS method. Miniaturization is possible.
[0020]
When the well regions 54a, 54b, etc. are of the opposite conductivity type, that is, when the high-concentration buried layer 25 is n-type, the high-concentration buried layer 25 becomes an electron pocket (carrier pocket), and photogenerated electrons are Will accumulate.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described below with reference to the drawings.
(First embodiment)
FIG. 1 is a plan view showing a layout of pixels constituting the MOS type image sensor according to the first embodiment of the present invention.
[0022]
As shown in FIG. 1, a unit pixel 101 including a light receiving diode 111 and an optical signal detecting insulated gate field effect transistor (hereinafter sometimes referred to simply as a MOS transistor) 112 adjacent to the light receiving diode 111 is provided. Arranged in rows and columns. An n-channel MOS (nMOS) is used as the MOS transistor 112. The unit pixel 101 is surrounded by an element isolation region in which a diffusion isolation region 53 is a series. Further, the gate electrode 59 in the portion of the MOS transistor 112 has an octagonal peripheral portion, a strip shape, and a ring shape.
[0023]
The gate electrodes 59 of the MOS transistors 112 arranged along the row direction are connected to each other by vertical scanning signal (VSCAN) supply lines 59a, 59b,... And the source regions 56 of the MOS transistors 112 arranged along the column direction are Are connected to each other by vertical output lines (or source electrodes) 60a, 60b,. The vertical scanning signal (VSCAN) supply lines 59a, 59b,... And the vertical output lines (or source electrodes) 60a, 60b,. The diffusion isolation region 53 connected to the drain region 57a also serves as drain voltage (VDD) supply lines (or drain electrodes) 61a, 61b,.
[0024]
In particular, the first embodiment has the following features. That is, in the pixel 101, the direction from the gate electrode 59 of the MOS transistor 112 to the light receiving diode 111 is inclined with respect to the row direction and the column direction.
The light receiving diode 111 is surrounded by the gate electrode 59 of the MOS transistor 112 in the pixel and the gate electrode 59 of the MOS transistor 112 in the adjacent pixel. Conversely, the gate electrode 59 of the MOS transistor 112 is surrounded by the light receiving diode 111 in the pixel and the light receiving diode 111 of the adjacent pixel.
[0025]
Further, the gate electrodes 59 of the MOS transistors 112 connected to each other by the same vertical scanning signal (VSCAN) supply lines 59a, 59b,... Are arranged in a straight line along the row direction, and a vertical output line (or source electrode). The gate electrodes 59 of the MOS transistors 112 in which the source regions 56 are connected to each other by 60a, 60b,... Are aligned in a straight line along the column direction.
[0026]
Next, a cross-sectional structure of one unit pixel 101 of the MOS type image sensor according to the embodiment of the present invention will be described with reference to FIG. 2 is a cross-sectional view taken along line II-II in FIG.
As shown in FIG. 2, each of the light receiving diode 111 and the MOS transistor 112 includes a different p-type well region, that is, a first well region (one-conductivity type semiconductor layer) 54a and a second well region (one-conductivity type). (Semiconductor layer) 54b and the well regions 54a and 54b are connected to each other. The first well region 54a in the portion of the light receiving diode 111 constitutes a part of a region where charge is generated by light irradiation. The second well region 54b in the portion of the MOS transistor 112 constitutes a gate region in which the channel threshold voltage can be changed by the potential applied to the region 54b.
[0027]
An n-type source region 56 is provided inside the inner peripheral portion of the gate electrode 59 having a band shape and a ring shape in the portion of the MOS transistor 112, and an n-type drain region 57 a is provided outside the outer peripheral portion of the same gate electrode 59. Is provided. A region between the source region 56 and the drain region 57a and the surface layer of the second well region 54b under the gate electrode 59 is a channel region. The gate electrode 59 is formed on the channel region 54 c via the gate insulating film 58. In order to keep the channel region in an electron accumulation state or depletion state at a normal operating voltage, an n-type impurity having an appropriate concentration is introduced into the channel region to form the channel dope layer 54c.
[0028]
Further, the drain region 57a extends to form the impurity region 57 of the light receiving diode 111. That is, the impurity region 57 and the drain region 57a are integrally formed so as to cover most of the regions on the surface layers of the first and second well regions 54a and 54b connected to each other. Further, the impurity region 57 and the drain region 57 a extend to the periphery of the pixel 101 and are connected to the diffusion isolation region 53 surrounding the pixel 101.
[0029]
Further, the carrier pocket (high-concentration buried layer) 55, which is a feature of the MOS image sensor, is a partial region in the channel length direction from the drain region 57a to the source region 56, and is formed on the source region 56 side. And over the entire channel width direction.
The above-described components are covered with an insulating film 64 such as a silicon oxide film, and regions other than the light receiving window 63 of the light receiving diode 111 are covered with a metal layer (light shielding film) 62 formed on the insulating film 64. Shaded.
[0030]
Next, the overall configuration of a MOS type image sensor using unit pixels having the above structure will be described with reference to FIG. FIG. 11 shows a circuit configuration diagram of the MOS type image sensor in this embodiment.
As shown in FIG. 11, this MOS image sensor has a two-dimensional array sensor configuration, and pixels 101 having the above-described structure are arranged in a matrix in the column direction and the row direction.
[0031]
Further, a driving scanning circuit 102 for vertical scanning signal (VSCAN) and a driving scanning circuit 103 for drain voltage (VDD) are arranged on the left and right sides of the pixel region. One vertical scanning signal supply line (VSCAN supply line) 59a, 59b,... Is provided for each row from the drive scanning circuit 102 for the vertical scanning signal. The vertical scanning signal supply lines 59a, 59b,... Are connected to the gate electrodes 59 of the MOS transistors 112 in all the unit pixels 101 arranged in the row direction.
[0032]
Further, one drain voltage supply line (VDD supply line) 61a, 61b,... Is provided for each row from the drive scanning circuit 103 for drain voltage (VDD). The drain voltage supply lines 61a, 61b,... Are connected to the drain regions 57a of the optical signal detection MOS transistors 112 in all the unit pixels 101 arranged in the row direction.
[0033]
Further, one vertical output line 60a, 60b,... Is provided for each column, and each vertical output line 60a, 60b,... Is connected to the MOS transistors 112 in all the unit pixels 101 arranged in the column direction. Each is connected to the source region 56.
Further, the source region 56 of the MOS transistor 112 is connected to the signal output circuit 105 through vertical output lines 60a, 60b,. As shown in FIG. 10, the source region 56 is directly connected to a line memory composed of a capacitor (not shown) in the signal output circuit 105.
[0034]
By sequentially driving the MOS transistor 112 of each unit pixel 101 by the vertical scanning signal (VSCAN) and the horizontal scanning signal (HSCAN), a video signal (Vout) that does not include a noise component due to residual charges proportional to the amount of incident light. ) Is read from the signal output circuit 105.
Next, the element operation for optical signal detection in the MOS type image sensor will be described with reference to FIG. FIG. 12 is a timing chart showing an element operation for optical signal detection.
[0035]
In element operation for optical signal detection, accumulation period-read period-initialization period (accumulation period-read period-initialization period (sweep period) -noise voltage read period-accumulation period--). A series of processes of sweeping period) -noise voltage reading period is repeated.
[0036]
In the accumulation period shown in FIG. 12, carriers are generated by light irradiation, and holes in the carriers are moved in the first and second well regions 54a and 54b and accumulated in the carrier pocket 55. In this case, a positive voltage of about +1.6 V is applied to the drain region 57a, and the source region 56 is held in a high impedance state. A positive voltage of about +2 V is applied to the gate electrode 59 so that sufficient electrons are accumulated in the channel region of the MOS transistor 112. As a result, a positive voltage of about +1.6 V, which is the same as that of the drain region 57a, is applied to the source region 56 as well. This accumulation period is a period in which a voltage corresponding to the difference between the first source potential modulated by the optical signal stored in the first and second line memories and the second source potential before the optical signal enters is output. But there is.
[0037]
Similarly, in the reading period, the change in the threshold voltage of the MOS transistor 112 due to the photo-generated charges accumulated in the carrier pocket 55 is read as a change in the source potential and stored in the first line memory. A positive voltage of about +2 to 3 V is applied to the drain region 57 a and a positive voltage of about +2 to 3 V is applied to the gate electrode 59 so that the MOS transistor 112 operates in a saturated state.
[0038]
Similarly, in the initialization period, before accumulating the photogenerated charge (photogenerated carrier), the photogenerated charge remaining after reading is completed, the acceptor, the donor, etc. are neutralized or positively captured by the surface level. Residual charges before reading out the optical signal, such as holes and electrons, are discharged from the semiconductor to empty the carrier pocket 55. A positive high voltage of about +5 V or more is applied to the source region 56, the drain region 57a, and the gate electrode 59.
[0039]
In the noise voltage readout period, the second source potential is stored in the second line memory in a state where the photo-generated charges are swept from the carrier pocket 55 between the initialization period and the accumulation period. Also during this period, the light receiving diode 111 and the MOS transistor 112 are applied with the same voltage as in the reading period.
[0040]
Next, another configuration different from the configuration shown in FIGS. 1 and 2 will be described with reference to FIGS. 3 and 4.
3 is a plan view showing another structure different from the structure shown in FIG. 1, and FIG. 4 is a cross-sectional view taken along line III-III in FIG.
1, VDD supply lines 61a, 61b,... Extending in parallel with the VSCAN supply lines 59a, 59b,... Are newly provided above the drain region 57a. 57a is connected. 3 and 4, the same reference numerals as those shown in FIGS. 1 and 2 denote the same elements as those in FIGS.
[0041]
3 and 4 can minimize the potential difference of the drain voltage between the pixels 101 and make the operation of the solid-state imaging device uniform.
As described above, according to the first embodiment of the present invention, in one pixel 101, the gate electrode 59 whose peripheral part has an octagonal planar shape is used, and the light receiving diode 111 is formed of the gate electrode 59. Provided adjacent to at least one side of the octagon, the pixels 101 are arranged in rows and columns.
Further, the inside of the pixel 101 is arranged so that the direction from the gate electrode 59 to the light receiving diode 111 coincides with the oblique direction with respect to the row direction and the column direction. The light receiving diode 111 is arranged so that its peripheral portion is surrounded by the gate electrode 59 of the insulated gate field effect transistor 112, and the gate electrode 59 of the insulated gate field effect transistor 112 is arranged so as to be surrounded by the light receiving diode 111. doing.
Thereby, for example, it becomes easy to form the light receiving diode 111 including the light receiving portion having a so-called isotropic spread in which the ratio of the short side to the long side of the rectangular light receiving portion is close to 1.
By the way, when the width of the gate electrode 59 is set to 1/2 or more or 2/3 or more of the pitch of the pixel 101, if the pixels are arranged without any modification as shown in FIG. As shown in FIG. 10C, the output of the photoelectric signal from the pixel is lowered by the irradiation light spot protruding from the light receiving portion. On the other hand, in the pixel array as in the present invention, since the light receiving diode 111 having a light receiving portion having a more isotropic spread can be obtained, as shown in FIG. By protruding from the pixel, it is possible to prevent the occurrence of so-called shading that the output of the photoelectric signal from the pixel is lowered.
[0042]
(Second Embodiment)
FIG. 5 is a plan view showing an arrangement of pixels in the MOS type image sensor according to the second embodiment of the present invention.
In the second embodiment of the present invention, the arrangement of the pixels 101 in the same row is the same as that of the first embodiment in that they are aligned along the row direction. The light receiving diode 111 is surrounded by the gate electrode 59 of the MOS transistor 112 in the pixel 101 and the gate electrode 59 of the MOS transistor 112 of the adjacent pixel, and conversely, the gate electrode 59 of the MOS transistor 112 is The point that the light receiving diode 111 in the pixel and the light receiving diode 111 of the adjacent pixel surround the peripheral portion is the same as in the first embodiment.
[0043]
On the other hand, the difference from the first embodiment is that, in the pixel 101, the direction from the gate electrode 59 of the MOS transistor 112 to the light receiving diode 111 is orthogonal to the row direction and to the column direction. The arrangement of the gate electrodes 59 of the MOS transistors 112 is zigzag along the row direction.
Further, a diffusion isolation region 53 having the same conductivity type as that of the drain region 57a is formed in one row, and the pixel 101 is formed by the element isolation region 53 formed deeper than the first and second well regions 54a and 54b. The enclosed points are the same as in the first embodiment, but differ from the first embodiment in that an inter-row separation band 62a for separating the rows is provided. The row separation band 62a includes, for example, a field oxide film formed by LOCOS (Local Oxide of Silicon) and a p-type layer reaching the substrate from the surface of the semiconductor substrate below the field oxide film.
[0044]
Other components in FIG. 5 that are denoted by the same reference numerals as those in FIG. 1 and FIG. 2 are the same as those in FIG. 1 and FIG.
Further, the cross-sectional structure of the pixel 101 is the same as the cross-sectional structure of the pixel shown in FIG.
The configuration of the second embodiment of the present invention has the same effect as that of the first embodiment.
[0045]
Furthermore, the second embodiment has the following configuration that is different from the configuration of the first embodiment. That is, in the planar arrangement of the pixels 101 in the solid-state imaging device, as shown in FIG. 5, the light receiving diodes 111 and the gate electrodes 59 are alternately arranged along the row direction and along the column direction. In this case, in particular, the arrangement of the pixels 101 in the same row is linear along the row direction, and the arrangement of the light receiving diodes 111 is zigzag along the row direction.
[0046]
The arrangement as shown in FIG. 5, that is, the arrangement in which the centers of the light receiving diodes 111 are zigzag has the same effect as so-called pixel shift in a three-plate type solid-state imaging device using a CCD element. That is, by shifting the arrangement of the light receiving sections in a specific row by 1/2 pitch with respect to the arrangement of the light receiving sections in the upper or lower row, there are substantially further light receiving sections between the light receiving sections. The video signal between the light receiving units is also captured as compared to the video when pixel shifting is not performed. Therefore, the resolution can be improved with a single plate type.
[0047]
In the case of a CCD image sensor, it is considered that the single-plate type pixel shift is considerably difficult because a sequential output method is used. However, in the case of a MOS type image sensor such as the present invention, an image from a pixel in an arbitrary row is considered. Since the signal can be output, the resolution can be easily improved by the single-plate pixel shift.
(Third embodiment)
FIG. 6 is a plan view showing an arrangement of pixels in the MOS image sensor according to the third embodiment of the present invention.
[0048]
In the third embodiment, the arrangement of the light receiving diodes 111 and the arrangement of the gate electrodes 59 of the MOS transistors 112 are both zigzag along the row direction, similar to the second embodiment. The light receiving diode 111 is surrounded by the gate electrode 59 of the MOS transistor 112 in the pixel 101 and the gate electrode 59 of the MOS transistor 112 of the adjacent pixel, and conversely, the gate electrode 59 of the MOS transistor 112 is The second embodiment is the same as the second embodiment in that the light receiving diode 111 in the pixel and the light receiving diode 111 of the adjacent pixel surround the periphery.
[0049]
On the other hand, the difference from the second embodiment is that in the pixel 101, the direction from the gate electrode 59 of the MOS transistor 112 to the light receiving diode 111 is in the row direction.
Further, a diffusion isolation region 53 having the same conductivity type as that of the drain region 57a is formed in one row, and the pixel 101 is formed by the element isolation region 53 formed deeper than the first and second well regions 54a and 54b. The enclosed points are the same as in the first and second embodiments, but are different from the second embodiment in that the inter-row separation band 62a for separating the rows is not provided.
[0050]
Further, the second embodiment is different from the second embodiment in that the gate interconnection portion 59x that connects the gate electrodes 59 is formed of the same material as the gate electrode 59. For example, when the gate electrode 59 is formed by patterning, the connection portion 59x is formed by patterning the same material as the gate electrode 59 at the same time.
1, 3, and 5, the second well region 54 b, the impurity region 57, and the drain region 57 a indicated by dotted lines are similar to those in FIGS. 1, 3, and 5 in FIG. 6. Although it exists around the gate electrode 59, it is omitted in FIG.
[0051]
In addition, in FIG. 6, the other components shown by the same reference numerals in FIG. 1 and FIG. 2 are the same as those in FIG. 1 and FIG. Description is omitted.
The cross-sectional structure of the pixel 101 is the same as the cross-sectional structure of the pixel shown in FIG.
Next, another configuration different from the configuration shown in FIG. 6 will be described with reference to FIG. FIG. 7 is a plan view showing another structure different from the structure shown in FIG.
[0052]
6 is characterized in that the gate electrodes 59 are connected to each other by VSCAN supply lines 59a, 59b,... Instead of connecting the gate electrodes 59 to each other by the connecting portion 59x. . 7 that are the same as those shown in FIG. 6 are the same as those in FIG.
As described above, the third embodiment of the present invention has substantially the same configuration as that of the second embodiment, and thus has the same effects as those of the second embodiment.
[0053]
(Fourth embodiment)
FIG. 8 is a plan view showing an arrangement of pixels in the MOS image sensor according to the fourth embodiment of the present invention.
In the third embodiment, the arrangement of the light receiving diodes 111 and the arrangement of the gate electrodes 59 of the MOS transistors 112 are zigzag along the row direction, similar to the second and third embodiments. is there. The light receiving diode 111 is surrounded by the gate electrode 59 of the MOS transistor 112 in the pixel 101 and the gate electrode 59 of the MOS transistor 112 of the adjacent pixel, and conversely, the gate electrode 59 of the MOS transistor 112 is The second embodiment is the same as the second and third embodiments in that the light receiving diode 111 in the pixel and the light receiving diode 111 of the adjacent pixel surround the periphery.
[0054]
On the other hand, the difference from the third embodiment is that in the pixel 101, the direction from the gate electrode 59 of the MOS transistor 112 to the light receiving diode 111 is in the column direction.
Further, a diffusion isolation region 53 having the same conductivity type as that of the drain region 57a is formed in one row, and the pixel 101 is formed by the element isolation region 53 formed deeper than the first and second well regions 54a and 54b. The enclosed points are the same as in the first to third embodiments, but are different from the second embodiment in that no inter-row separation band 62a for separating the rows is provided.
[0055]
Further, the third embodiment is the same as the third embodiment in that the gate interconnection 59x that connects the gate electrodes 59 is formed of the same material as the gate electrode 59. As in the third embodiment, the connection portion 59x is formed by patterning the same material as that of the gate electrode 59 when the gate electrode 59 is formed by patterning, for example.
1, 3, and 5, the second well region 54 b, the impurity region 57, and the drain region 57 a indicated by dotted lines are similar to those in FIGS. 1, 3, and 5 in FIG. 8. Although it exists around the gate electrode 59, it is omitted in FIG.
[0056]
In addition, in FIG. 8, the other components shown by the same reference numerals in FIG. 6 and FIG. 7 are the same as those in FIG. 6 and FIG. Description is omitted.
The cross-sectional structure of the pixel 101 is also the same as the cross-sectional structure of the pixel shown in FIG.
As described above, the fourth embodiment of the present invention has substantially the same configuration as the second and third embodiments, and thus has the same effects as those of the second and third embodiments.
[0057]
(Comparative example)
FIG. 9 is a plan view showing an arrangement of pixels in a MOS image sensor of a comparative example with respect to the MOS image sensor according to the above embodiment.
The pixels 101 are arranged in rows and columns so that the light receiving diodes 111 and the MOS transistors 112 in the pixels 101 are aligned in the same direction as the row direction.
[0058]
In this case, unlike the above embodiment, the light receiving diode 111 and the gate electrode 59 are arranged in a straight line in the column direction.
When one pixel is miniaturized and the width of the gate electrode 59 in the pixel 101 is set to 1/2 or more of the pitch of the pixel 101, or further reduced to 2/3 or more, the light receiving unit As shown in FIG. 9, the light receiving portion has an elongated rectangular shape.
For this reason, as shown in FIG. 10C, the irradiation light spot protrudes from the light receiving portion, so that the output of the photoelectric signal from the pixel is lowered.
On the other hand, in the pixel array as in the first to fourth embodiments, the light receiving diode 111 including the light receiving portion having a more isotropic spread can be obtained. As shown by the pixels of the first and second embodiments shown in (1)), the irradiation light spot comes into the light receiving portion. For this reason, it is possible to prevent the occurrence of so-called shading, in which the output of the photoelectric signal from the pixel 101 decreases due to the irradiation light spot protruding from the light receiving portion.
[0059]
Although the present invention has been described in detail with the embodiments, the scope of the present invention is not limited to the examples specifically shown in the above embodiments, and the above embodiments within the scope of the present invention are not deviated. Variations in form are within the scope of this invention.
For example, in the above-described embodiment, the planar shape of the peripheral portion of the gate electrode 59 is an octagonal shape, but other than the octagonal shape, a polygonal shape or a circular shape having four or more sides may be used. it can.
[0060]
Furthermore, various modifications are conceivable as the structure of the pixel 101 to which the present invention is applied. The light receiving diode 111 and the MOS transistor 112 for detecting an optical signal are adjacent to each other to constitute one pixel 101, and the light receiving diode 111 Is surrounded by the gate electrode 59 of the insulated gate field effect transistor 112, and the gate electrode 59 of the insulated gate field effect transistor 112 may be surrounded by the light receiving diode 111.
[0061]
Further, in one row, the light receiving diodes 111 are arranged in a zigzag manner, and the light receiving diodes 111 are arranged substantially in half the pitch in the row direction and the column direction. Just do it.
Further, the first and second well regions 54a and 54b are formed in the n-type layers 52a and 52b on the p-type substrate 51. Instead of the n-type layers 52a and 52b, a p-type epitaxial layer is formed. An n-type impurity may be introduced to form an n-type layer, and the first and second well regions 54a and 54b may be formed in the n-type layer.
[0062]
Furthermore, although the p-type substrate 51 is used, an n-type substrate may be used instead. In this case, in order to obtain the same effect as that of the above embodiment, all the conductivity types of the respective layers and regions described in the above embodiment may be reversed. In this case, carriers to be accumulated in the carrier pocket 55 are electrons among electrons and holes.
[0063]
【The invention's effect】
As described above, according to the present invention, the pixels including the insulated gate field effect transistors for detecting optical signals are arranged in rows and columns, and the light receiving diode is formed by the gate electrode of the insulated gate field effect transistor. The peripheral part is surrounded, and the gate electrode of the insulated gate field effect transistor is surrounded by the light receiving diode.
Thereby, for example, it becomes easy to form a light receiving diode having a light receiving portion having a so-called isotropic spread in which a ratio of a short side to a long side of a rectangular light receiving portion is close to 1. For this reason, it is possible to prevent so-called shading, that is, the output of the photoelectric signal from the pixel is lowered due to the irradiation light spot protruding from the light receiving portion.
[0064]
In the planar arrangement of the pixels in the solid-state imaging device, the light receiving diodes and the gate electrodes are alternately arranged along the row direction and along the column direction.
In this case, in particular, the arrangement of pixels in the same row is linear along the row direction, and the arrangement of the gate electrodes of the insulated gate field effect transistors is zigzag along the row direction. In particular, in addition to the arrangement of the gate electrodes of the insulated gate field effect transistors, the arrangement of pixels in the same row is zigzag along the row direction.
[0065]
With the arrangement in which the centers of the light receiving diodes are zigzag, there are further light receiving portions between the light receiving portions, and the resolution can be improved with a single plate type.
[Brief description of the drawings]
FIG. 1 is a plan view showing an element layout in a pixel of a solid-state imaging element used in a solid-state imaging apparatus according to a first embodiment of the present invention.
2 is a cross-sectional view taken along line II-II in FIG.
FIG. 3 is a plan view showing an element layout in a pixel of a solid-state imaging element used in another solid-state imaging apparatus according to the first embodiment of the present invention.
4 is a cross-sectional view taken along line III-III in FIG.
FIG. 5 is a plan view showing an element layout in a pixel of a solid-state imaging element used in a solid-state imaging apparatus according to a second embodiment of the present invention.
FIG. 6 is a plan view showing an element layout in a pixel of a solid-state imaging element used in a solid-state imaging apparatus according to a third embodiment of the present invention.
FIG. 7 is a plan view showing an element layout in a pixel of a solid-state imaging device used in another solid-state imaging device according to a third embodiment of the present invention.
FIG. 8 is a plan view showing an element layout in a pixel of a solid-state imaging device used in a solid-state imaging device according to a fourth embodiment of the present invention.
FIG. 9 is a plan view showing an element layout in a pixel of a solid-state imaging element used in a solid-state imaging apparatus according to a comparative example.
FIGS. 10A to 10C are plan views for explaining the effect of the present invention in comparison with a comparative example. FIGS.
FIG. 11 is a diagram showing an overall circuit configuration of a solid-state imaging device having a solid-state imaging element according to the present invention.
FIG. 12 is a timing chart showing a method for driving the solid-state imaging device according to the embodiment of the present invention.
FIG. 13 is a plan view showing an element layout in a unit pixel of a solid-state imaging element used in a solid-state imaging apparatus according to a conventional example.
14 is a cross-sectional view taken along line II in FIG.
[Explanation of symbols]
53 Diffusion isolation region (element isolation region)
54a First well region
54b Second well region
54c Channel doped layer
55 Carrier pocket (high concentration buried layer)
56 Source area
57 Impurity region
57a Drain region
58 Gate insulation film
59 Gate electrode
59a, 59b, 59c VSCAN supply line
59x gate interconnect
60a, 60b, 60c, 60d Vertical output line
61a, 61b VDD supply line
71 Horizontal output line
72a, 72b HSCAN supply line
73a, 73b Boost voltage supply line
101 unit pixel
102 VSCAN drive scanning circuit
103 VDD drive scanning circuit
104 HSCAN input scanning circuit
105 Signal output circuit
107 Video signal output terminal
108 Boost scanning circuit
111 Light-receiving diode
112 Insulated gate field effect transistor for optical signal detection (MOS transistor for optical signal detection)

Claims (7)

A light-receiving diode formed in a first well region of one conductivity type, and a one-conductor conductively adjacent to the first well region of the light-receiving diode and electrically connected so as to be able to accumulate photogenerated charges generated in the light- receiving diode has a unit pixel and a second well region light signal detecting insulated gate field effect transistor formed in the mold, the insulated gate portion of the field effect transistor and the second of the one conductivity type A drain region of the opposite conductivity type provided in the well region and electrically connected to the surface layer of the opposite conductivity type formed on the surface of the light receiving diode in the first well region, and the drain region and the channel region It has formed opposite conductivity type source region of which accumulates the light generated charge under the channel region under the gate electrode, in the insulated gate field effect transistor The threshold voltage of Yaneru area by modulating a solid-state imaging device for detecting an optical signal,
In the unit pixel, gate electrodes of the insulated gate field effect transistors in a row direction are connected to each other, and source regions of the insulated gate field effect transistors in the same column are connected to each other, and the light receiving A diode is surrounded by an insulated gate field effect transistor of its own unit pixel and an insulated gate field effect transistor of an adjacent unit pixel, and the insulated gate field effect transistor is a light receiving diode of its own unit pixel. And adjacent light-receiving diodes of adjacent unit pixels, the unit pixels are adjacent to each other in a diffusion region of opposite conductivity type that is electrically connected to the drain region at least in the same row. the solid-state imaging device, characterized in that connected to the pixel. 2. The solid-state imaging device according to claim 1, wherein the light receiving diodes and gate electrodes of the insulated gate field effect transistors are alternately arranged in the row direction and the column direction. The gate electrode of the insulated gate field effect transistor has a ring shape, and a source region of opposite conductivity type is provided in the second well region of one conductivity type inside the inner periphery of the gate electrode, and the gate A drain region of opposite conductivity type is provided in the second well region of the one conductivity type outside the outer peripheral portion of the electrode, and the light well is provided in the second well region of the one conductivity type below the channel region. 3. A solid-state imaging device according to claim 1, further comprising a high-concentration buried layer of one conductivity type for accumulating generated charges. 4. The solid according to claim 3, wherein the high-concentration buried layer is a partial region in the channel length direction from the drain region to the source region, and is formed in a ring shape under the channel region. Imaging device. 2. The solid-state imaging device according to claim 1, wherein the diffusion region is connected to the drain region and formed deeper than the first and second well regions. 6. The unit pixel according to claim 1, wherein the unit pixels are connected by the diffusion region electrically connected to the drain region in the same row, and are electrically separated for each row. The solid-state imaging device according to any one of the above. The solid-state imaging device according to claim 1 , wherein the unit pixel is shielded from light except for a light receiving window opening of the light receiving diode .

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