JPH11233641A - Semiconductor device and method of manufacturing semiconductor device - Google Patents

Abstract

[PROBLEMS] To reduce the size of a semiconductor device while ensuring a high ESD withstand voltage. An output transistor has an N ⁺ region as a source region and an N ⁺ region as a drain region. Bipolar transistor 4 has N ⁺ region 12 as a collector region, P well 1 as a base region, and N ⁺ region 14 as an emitter region. A zener diode DZ constituted by a junction between the N ⁺ region 12 and the P ⁺ region 16 is provided, and the BP is turned on instead of the BPP when the high voltage pulse 32 is applied. The Zener voltage VZ of the DZ is controlled by the impurity concentration, and the VZ is made lower than the avalanche breakdown voltage and the snapback voltage in the drain region, and is made higher than the absolute maximum rated voltage. Reduce the gate length, contact size, etc. to minimum dimensions according to design rules. The junction of the Zener diode in a direction parallel to the surface of the semiconductor device is widened.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular, the present invention relates to a structure for protecting a circuit from surges such as static electricity.

[0002]

2. Description of the Related Art In a semiconductor device, it is necessary to increase an ESD withstand voltage so that an internal circuit or the like is not electrostatically damaged by a surge of static electricity or the like. And IEEE TRA as background technology to increase ESD withstand voltage
NSACTIONS ON ELECTRON DEVICES, VOL.44, NO.7, JULY 199
7 and the technology disclosed in JP-A-7-202126 are known. This background technology will be described with reference to FIGS. FIG. 1A is a plan view of this background art, and FIG. 1B is a cross-sectional view taken along line A1-A2 in FIG.

In FIGS. 1A and 1B, an output transistor 2 is provided in a P well 201 formed in a semiconductor substrate.
02 and a bipolar transistor (BP) 204 are formed. The output transistor 202, which is an N-type MOSFET having an LDD (Lightly Doped Drain) structure, has a gate electrode 206, an N ⁺ region 210 as a source region, and N ⁺
The region 212 is a drain region. In the bipolar transistor (BP) 204, the N ⁺ region 212 is a collector region, the P well 201 is a base region, the N ⁺ region 21
4 is the emitter region. Here, the N ⁺ region 210
Are connected to a GND line (ground potential) via a wiring layer 220. The N ⁺ region 212 is connected to a pad 230 (an output terminal, an input / output terminal, an input terminal, etc.) via a wiring layer 222. Further, the N ⁺ region 214 is
4 to a GND line or a given discharge line. The P-well 201, P ⁺ region 22
8 (well tap), via a wiring layer 226, to a GND line or a discharge line.

The feature of this background example is that the output transistor 2
02 is determined by the base width (effective base width) of the bipolar transistor (BP) 204.
The point is that it is longer than BW. By doing this,
When the high voltage pulse (surge) 232 is applied to the pad 230, the BP can be turned on instead of the parasitic bipolar transistor BPP constituted by the N ⁺ region 212, the P well 201 and the N ⁺ region 210. As a result, a large current can be prevented from flowing through the BPP, and the output transistor 202 (particularly, the gate insulating film) can be prevented from being electrostatically damaged.

[0005] However, this background art has a problem that the gate length L cannot be made the minimum dimension according to the design rule. In the case where the base width BW is set to the minimum dimension on the design rule, for example, 0.8 μm, the gate length L must be set to, for example, 1.8 μm. When the gate length L is increased, the current supply capability of the output transistor 202 is reduced.

On the other hand, in order to increase the current supply capability while keeping the gate length L long, it is necessary to increase the gate width W, which results in a large layout area of the output transistor 202. In recent years, a semiconductor device is provided with a very large number of pads (output pads, input / output pads, input pads, and the like). Therefore, an increase in the layout area of the output transistor 202 increases the chip area and the This results in higher costs.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object of the present invention is to provide a semiconductor device capable of realizing a small chip area while securing a high ESD withstand voltage, and a semiconductor device therefor. It is to provide a manufacturing method.

[0008]

In order to solve the above problems, a semiconductor device according to the present invention is formed in a first region of a first conductivity type, has a gate electrode, and has a first region of a second conductivity type.
A second conductivity type FET transistor having an impurity region as a source region and a second conductivity type second impurity region as a drain region; and a second conductivity type FET transistor formed in the first region, wherein the second impurity region is a collector region, One area is the base area,
A third of a second conductivity type which is element-isolated from the second impurity region;
A bipolar transistor having an impurity region as an emitter region, a first conductivity type fourth impurity region formed in a region adjacent to the second impurity region and between the second and third impurity regions, And a Zener diode formed by a junction with the two impurity regions.

According to the present invention, the second impurity region has an ESD.
Is applied, the parasitic diode formed by the junction between the second impurity region and the first region is formed by the junction between the second impurity region and the fourth impurity region before the avalanche breakdown occurs. The Zener diode to be used can be caused to undergo Zener breakdown. As a result, surge current caused by high voltage pulses, etc.
The discharge can be performed by the bipolar transistor including the second impurity region, the first region, and the third impurity region. Therefore, it is possible to prevent a large current from flowing through a parasitic bipolar transistor (a bipolar transistor parasitic to the FET transistor) constituted by the second impurity region, the first region, and the first impurity region, and to increase an ESD withstand voltage. . In addition to this, the present invention
There is no restriction that the gate length must be longer than the base width of the bipolar transistor, and the gate length can be reduced. As a result, according to the present invention, the semiconductor device can be significantly reduced in size while ensuring a high ESD withstand voltage.

The present invention is characterized in that a Zener voltage of the Zener diode is lower than an avalanche breakdown voltage in the drain region of the FET transistor. By doing so, the Zener diode can be reliably broken down before the parasitic diode in the drain region undergoes avalanche breakdown.

Further, the present invention is characterized in that a Zener voltage of the Zener diode is lower than a snapback voltage in the drain region of the FET transistor.

By doing so, a surge current due to a high voltage pulse or the like can be stably discharged through the bipolar transistor.

Further, the present invention is characterized in that the Zener voltage of the Zener diode is lower than one of the avalanche breakdown voltage and the snapback voltage and is equal to or higher than the absolute maximum rated voltage of the semiconductor device. . By doing so, it is possible to effectively reduce the leakage current in the drain region during normal operation while ensuring a high ESD withstand voltage and realizing a compact semiconductor device.

Further, the present invention is characterized in that the Zener voltage is controlled by an impurity concentration of the fourth impurity region. By doing so, it is possible to easily realize control for setting the Zener voltage to a desired value.

Further, the present invention is characterized in that the gate length of the gate electrode of the FET transistor is a minimum dimension according to a design rule. By doing so, a sufficient current supply capability of the FET transistor can be obtained with a short gate width. That is, FET
The semiconductor device can be made compact while maintaining the current supply capability of the transistor.

Further, according to the present invention, the size of a drain contact of the drain region of the FET transistor, a distance between a first side of the drain contact and a third side of the drain region on the gate electrode side, A distance between two sides and a fourth side orthogonal to the third side of the drain region, a size of a source contact of the source region of the FET transistor, a fifth side of the source contact, and a gate electrode side of the source region. Seventh of
At least one of a distance from a side and a distance between a sixth side of the source contact and an eighth side orthogonal to the seventh side of the source region is a minimum dimension in a design rule. . By doing so, the semiconductor device can be made more compact.

Further, according to the present invention, of the junction between the second impurity region and the four impurity regions, a junction in a direction substantially parallel to the surface of the semiconductor device is wider than a junction in a direction crossing the surface of the semiconductor device. It is characterized by. By doing so, the entire area of the junction of the Zener diode can be increased, and the current passage area of the surge current in the discharge path can be increased. As a result, the ESD withstand voltage can be further increased.

According to the present invention, there is provided a method of manufacturing a semiconductor device including a second conductivity type FET transistor and a bipolar transistor, wherein a step of forming a gate electrode of the FET transistor and a source region of the FET transistor are provided. A first impurity region of a second conductivity type, a second impurity region of a second conductivity type that becomes a drain region of the FET transistor and a collector region of the bipolar transistor, and a second impurity region of a second conductivity type that becomes an emitter region of the bipolar transistor. Forming a third impurity region in a first region of a first conductivity type serving as a base region of the bipolar transistor; and forming a third impurity region in a region adjacent to the second impurity region and between the second and third impurity regions. A fourth impurity of the first conductivity type forming a junction of the Zener diode with the second impurity region. Characterized in that it comprises a step of forming a region.

According to the present invention, a compact semiconductor device having a high ESD withstand voltage can be formed. Note that the step of forming the fourth impurity region may be performed before or after the step of forming the first, second, and third impurity regions.

Further, according to the present invention, of the junction between the second impurity region and the four impurity region, the junction in the direction substantially parallel to the surface of the semiconductor device is wider than the junction in the direction intersecting the surface of the semiconductor device. As described above, the impurity-implanted region for forming the second impurity region and the impurity-implanted region for forming the fourth impurity region overlap each other. By doing so, the entire area of the junction of the Zener diode can be increased simply by increasing the overlap between the impurity-implanted regions, and the ESD withstand voltage can be further increased.

Further, the present invention is characterized in that the fourth impurity region is formed in a region separated from the surface of the semiconductor device. This can prevent the fourth impurity region from being exposed on the surface of the semiconductor device.

Further, according to the present invention, the fourth impurity region is formed as a low-concentration impurity region in an LDD structure of a first conductivity type FET transistor, and the first conductivity type FE is formed.
It is formed in any one of the steps of forming the source region and the drain region of the T transistor. By doing so, the number of steps can be reduced, the manufacturing period of the semiconductor device can be shortened, and the cost of the semiconductor device can be reduced.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below. In the following description, the first conductivity type is P-type and the second conductivity type is N-type. An example of application of a MOS output transistor to electrostatic discharge prevention will be described. However, the present invention is also applicable to a case where the first conductivity type is N-type and the second conductivity type is P-type. In addition to the MOS transistor, the present invention can be applied to various FET transistors such as a MIS transistor. Further, in addition to the output transistor, the present invention can be applied to a transistor provided as a protection circuit for an input pad, and the like.

1. Configuration of the present embodiment FIG. 2A shows an example of a plan view of the present embodiment. FIG. 2B is a cross-sectional view taken along line B1-B2 in FIG.

In FIGS. 2A and 2B, an output transistor 2 and a bipolar transistor (B) are formed in a P well 1 (first region of a first conductivity type) formed in a semiconductor substrate.
P) 4 is formed. N-type LDD (Lightly Dope
An output transistor (output buffer) 2 which is a MOSFET having a d drain structure has a gate electrode 6, an N ⁺ region 10 (a first impurity region of the second conductivity type) as a source region,
⁺ Region 12 (second impurity region of the second conductivity type) is used as a drain region. Bipolar transistor (BP)
Reference numeral 4 designates the N ⁺ region 12 as a collector region, the P well 1 as a base region, and the N ⁺ region 14 (third impurity region of the second conductivity type) as an emitter region. That is, the N ⁺ region 12 is
The output transistor 2 is used as a drain region,
The bipolar transistor 4 is used as a collector region (shared by the output transistor 2 and the bipolar transistor 4).

Here, the N ⁺ region 10 is connected to, for example, a GND line (ground potential) via a wiring layer 20. The N ⁺ region 12 is formed, for example, with a pad 30 via a wiring layer 22.
(Output terminal, input / output terminal, input terminal, etc.).
Further, the N ⁺ region 14 is connected to, for example, GND via the wiring layer 24.
Line or a given discharge line.
The P well 1 is connected to, for example, a GND line or a discharge line via a P ⁺ region 28 (well tap) and a wiring layer 26.

In the description below, N ⁺ region 10 is appropriately called source region 10 and N ⁺ region 12 is appropriately called drain region 12.
Alternatively, the collector region 12 is called, and the N ⁺ region 14 is called the emitter region 14 as appropriate.

FIGS. 1A and 1B and FIGS. 2A and 2B
As can be seen from the comparison, the feature of this embodiment is that N ⁺
The point is that a P ⁺ region 16 (a fourth impurity region of the first conductivity type) is provided in a region adjacent to the region 12 and between the N ⁺ region 12 and the N ⁺ region 14. That is, the N ⁺ region 12
And a P ⁺ region 16 provided with a Zener diode DZ. By doing so, when the high voltage pulse 32 is applied to the pad 30, the Zener diode DZ is connected before the parasitic diode DA formed by the junction between the N ⁺ region 12 and the P well 1 undergoes avalanche breakdown. Zener breakdown can be achieved. Thereby, BP can be turned on instead of the parasitic bipolar transistor BPP constituted by the N ⁺ region 12, the P well 1, and the N ⁺ region 10. As a result, a large current can be prevented from flowing through the BPP, and the output transistor 2 (particularly, the gate insulating film) can be prevented from being electrostatically damaged.

Moreover, in the background examples of FIGS. 1A and 1B, if the gate length L is not longer than the base width BW, B
The BP could not be turned on instead of the PP, and the gate length could not be reduced to the minimum dimension in the design rules. On the other hand, according to the present embodiment, the BP can be turned on instead of the BPP while the gate length L is set to the minimum size according to the design rule. As a result, the layout area of the output transistor 2 can be reduced while securing a high ESD withstand voltage, and the semiconductor device can be made compact and low in cost.

2. Setting of Zener Voltage In a normal output transistor without the Zener diode DZ, when a high voltage pulse (surge) is applied to the drain region, the parasitic diode D in the drain region
A breaks down avalanche. At this time, as indicated by E1 in FIG. 3, the drain voltage becomes VAB (avalanche breakdown voltage). Thereafter, when the parasitic bipolar transistor BPP is turned on, the drain voltage drops from VAB to VSB (snapback voltage) as shown by E2 in FIG. Such a phenomenon in which the drain voltage decreases is called snapback.

In this embodiment, as shown by E3 in FIG. 3, the Zener voltage VZ of the Zener diode DZ is set lower than the avalanche breakdown voltage VAB in the drain region 12 of the output transistor 2 (VZ). <VAB). By doing so, it is possible to surely cause the DZ to undergo a Zener breakdown before the DA undergoes an avalanche breakdown, and to turn on the BP instead of the BPP.

More preferably, the Zener voltage VZ is set lower than the snapback voltage VSB in the drain region 12 of the output transistor 2 (VZ <VSB), as shown at E4 in FIG. By doing so, the current can be stably discharged to the bipolar transistor BP side. That is, by setting VZ <VSB, the drain voltage can be clamped to a voltage lower than the snapback voltage VSB when a high voltage pulse is applied. If the drain voltage can be clamped to a voltage lower than VSB in this way, it is possible to reliably guarantee that the BPP will not turn on even if DA has avalanche breakdown for some reason. As a result,
It is possible to effectively prevent the current discharge path from changing from the BP side to the BPP side, and to reliably prevent the electrostatic breakdown of the output transistor 2.

The Zener voltage VZ of DZ is equal to EZ in FIG.
It is desirable that the voltage be equal to or higher than the absolute maximum rated voltage VAM of the semiconductor device as shown in 3 or E4. That is, VAB> VZ
It is desirable that ≧ VAM or VSB> VZ ≧ VAM. By doing so, it is possible to prevent a leakage current from flowing from the drain region 12 to the P well 1 via the Zener diode DZ during normal operation while ensuring a high ESD withstand voltage.

Usually, it is not a preferable design to form the P ⁺ region 16 adjacent to the drain region 12 and provide the Zener diode DZ. This is because a leak current may flow through the DZ. The present embodiment is characterized in that a P ⁺ region 16 is formed adjacent to the drain region 12 and a DZ is provided, contrary to circumstances that hinder the configuration of the present embodiment. That is, it is characterized in that the DZ is provided, paying attention to the fact that the leak current can be prevented from flowing during the normal operation by adjusting the zener voltage VZ so as to be equal to or higher than the absolute maximum rated voltage VAM. And
VZ ≧ VAM and VZ <VAB or VZ <VSB
By adjusting VZ so as to achieve, it becomes possible to increase the ESD withstand voltage when a high voltage pulse is applied, while preventing leakage current during normal operation.

3. Control of Zener Voltage In the present embodiment, the Zener voltage VZ in FIG. 3 is controlled by the impurity concentration of the P ⁺ region 16. Thereby, V
The zener voltage VZ can be controlled so that AB> VZ ≧ VAM or VSB> VZ ≧ VAM.

FIG. 4A shows an X-axis in a direction along the surface of the semiconductor device and a Y-axis in a direction perpendicular to the X-axis as shown in FIG.
The distribution example of the impurity concentration at Y = 0.1 μm when the axis is taken is shown. The junction of the Zener diode DZ is shown in FIG.
It is formed at the boundary indicated by F1 in FIG. The Zener voltage VZ is determined by the N ⁺ impurity concentration at this boundary (see F2; for example, the concentration of arsenic As forming the N ⁺ region 12) and the P ⁺ impurity concentration at this boundary (see F3, P ⁺
(For example, the concentration of boron BF ₂ ) forming the region 16.

FIG. 5 shows that the N ⁺ impurity concentration is 2.0 × 10 ²⁰
7 shows the relationship between the P ⁺ impurity concentration and the Zener voltage when the voltage is fixed at cm ⁻³ . As shown in FIG. 5, for example, in order to set the Zener voltage VZ to 9 V, it is sufficient to set the P ⁺ impurity concentration to about 3.0 × 10 ¹⁷ cm ⁻³ .
Similarly, in order to set the Zener voltage VZ to 7 V and 5 V, the P ⁺ impurity concentration is set to 6.0 × 10 ¹⁷ cm ⁻³ , respectively.
It can be seen that it should be about 1.0 × 10 ¹⁸ cm ⁻³ .
That is, the higher the P ⁺ impurity concentration, the lower the Zener voltage VZ.

By controlling the P ⁺ impurity concentration in this way, the zener voltage VZ can be easily adjusted to a desired value.

4. Gate Length As described above, in the background examples of FIGS. 1A and 1B, the gate length L must be longer than the base width BW. For this reason, the gate length L cannot be set to the minimum dimension according to the design rule. Therefore, in order to increase the current supply capability of the output transistor, the gate width W must be increased, so that the layout area of the output transistor becomes very large as shown in FIG.

On the other hand, in the present embodiment, the constraint of L> BW can be eliminated. Therefore, the gate length L
Can be reduced to the minimum dimension on the design rule. Therefore, as shown in FIG. 6B, the layout area of the output transistor can be significantly reduced as compared with FIG. 6A. As a result, the size and cost of the semiconductor device can be reduced. In particular, in recent years, a semiconductor device is provided with a very large number of pads (output pads, input / output pads, input pads, etc.). Therefore, if the layout area of the pad protection circuit can be reduced, the chip area can be significantly reduced. become able to.

In this embodiment, electrostatic discharge is prevented by discharging a current to the bipolar transistor BP. On the other hand, in a semiconductor device without such a BP, electrostatic breakdown is prevented by discharging a current to the parasitic bipolar transistor BPP when a high voltage pulse is applied. When the element size is not so fine, the output transistor is not electrostatically damaged even if a large current flows through the BPP. However, as the element size becomes finer and the gate insulating film becomes thinner. Then, a situation has arisen in which the output transistor is electrostatically damaged by the large current. In order to prevent the output transistor from being electrostatically damaged even when a large current flows through the BPP, the gate length L of the output transistor must be increased.

In the background examples shown in FIGS. 1A and 1B in which the current is discharged via the BP instead of the BPP in the same manner as in the present embodiment, the gate length L has to be increased due to the restriction of L> BW. Did not get.

On the other hand, in the present embodiment, the current is discharged via the BP instead of the BPP, and the restriction of L> BW can be eliminated. For this reason, the gate length L can be reduced, and the layout area of the output buffer has been dramatically reduced.

5. According to the present embodiment, as shown in FIG. 7, the size D1 of the drain contact 40 formed in the drain region 12, the side 41 of the drain contact 40, and the side 44 of the drain region 12 on the gate electrode 6 side, as shown in FIG. D2, or the side 42 of the drain contact 40 and the side 4 of the drain region 12
6 (perpendicular to the side 44) can be set to the minimum dimension on the design rule. Similarly, according to the present embodiment, the size D4 of the source contact 50 formed in the source region 10 and the side 51 of the source contact 50
D between the source region 10 and the side 54 on the gate electrode 6 side of the source region 10
5 or the side 52 of the source contact 50 and the source region 1
The distance D6 to the zero side 56 (perpendicular to the side 54) can be made the minimum dimension on the design rule. Thus, the layout area of the output transistor can be further reduced.

When a large current flows through the parasitic bipolar transistor BPP due to the application of the high voltage pulse, the sizes D1 and D of the drain contact 40 and the source contact 50, which are the paths through which the current flows, are increased in order to increase the ESD withstand voltage.
4 needs to be increased. It is also necessary to increase the distances D2 and D5 to increase the parasitic resistance of the path through which the current flows. Further, it is necessary to increase the distances D3 and D6 so that electrostatic breakdown does not occur at the sides 46 and 56.

On the other hand, according to the present embodiment, the ESD
Current is discharged via the bipolar transistor BP instead of the parasitic bipolar transistor BPP when the high voltage pulse is applied. Therefore, a high ESD withstand voltage can be ensured even if D1 to D6 are shortened, for example, to the minimum size in the design rule. That is, high ESD
The layout area of the output transistor can be significantly reduced while ensuring the withstand voltage.

6 Form of Junction of Zener Diode Various forms of junction of the Zener diode can be considered. For example, in FIG. 8A, of the junctions of the Zener diode DZ, the junction J1 in a direction substantially parallel to the surface of the semiconductor device is narrow. For example, J1
Is smaller than the junction J2 in the direction intersecting the surface. In such a bonding mode, the total area of the bonding of J1 and J2 is reduced. Therefore, the leakage current (N ⁺ region 12 generated in bonded via the P ⁺ region 16 P
(Leakage current flowing through the well 1) can be reduced. However, there is a possibility that the current passage area at the time of applying the high voltage pulse becomes narrow, and the ESD withstand voltage becomes low. Also,
There is also a possibility that the variation width of the zener voltage due to the fluctuation of the manufacturing process or the like becomes large.

On the other hand, in FIG. 8B, of the junctions of the Zener diode DZ, the junction J1 in a direction substantially parallel to the surface of the semiconductor device is widened. For example, J1
It is wider than the junction J2 in the direction crossing the surface.
In such a bonding mode, the total area of the bonding of J1 and J2 is large. For this reason, the leak current generated at the junction increases. However, when a high-voltage pulse is applied, the current passage area increases, and
D withstand voltage can be increased. In addition, it is possible to reduce the variation of the Zener voltage due to the fluctuation of the manufacturing process.

Therefore, when priority is given to suppression of leakage current, the junction configuration of FIG. 8A is advantageous, and when priority is given to improvement of ESD withstand voltage and reduction of variation in Zener voltage, the junction configuration of FIG. The form is advantageous.

[0050] The size of the junction J1 is, N ⁺ region 12
Implanted region IN and P ⁺ region 1 for forming
6 can be controlled by the size of the overlap region IV with the impurity implantation region IP. For example, as shown in FIG. 8A, if the overlap region IV is narrowed, the junction J1 becomes narrow, and J1 becomes narrower than, for example, the junction J2. This makes it possible to reduce the leak current. On the other hand, as shown in FIG. 8B, if the overlap region IV is made wider, the junction J1 becomes wider, and J1 becomes wider than, for example, the junction J2. As a result, the ESD withstand voltage can be increased and the variation in the Zener voltage can be reduced.

7. Manufacturing Method Next, the manufacturing method of the present embodiment will be briefly described.

(1) Manufacturing Method 1 FIGS. 9 (A) to 9 (F) are cross-sectional views showing the steps of the manufacturing method 1.

First, an element isolation film (field oxide film) 6
0, a channel stopper layer 62 for preventing formation of a parasitic transistor is formed (FIG. 9A). The channel stopper layer 62 is formed by ion implantation of boron or the like.

Next, a gate oxide film 64 having a desired thickness is formed by thermal oxidation (FIG. 9B). Then, a polysilicon film is formed by a CVD method or the like, and after ion implantation for adjusting a threshold value, the polysilicon film is patterned by a photo process to form a gate electrode 6 (FIG. 9C).

Next, for example, phosphorus as an N-type impurity is accelerated at an energy of 40 KeV and a dose of 3.0 × 10 ¹³ cm.
Ion implantation is performed at ^-2 to form low-concentration impurity regions (offset regions) 66, 67, and 68 for the LDD structure (FIG. 9D).

Next, a sidewall 70 for the LDD structure is formed. Then, for example, boron as a P-type impurity is accelerated at an energy of 40 KeV and a dose of 1.2 × 1.
P ⁺ region 16 is formed by ion-implantation at 0 ^{13 to} 5.0 × 10 ¹³ cm ⁻² (FIG. 9E). In this case, when the Zener voltage is set to 9 V, the dose is set to, for example, 1.2 ×
When it is set to about 10 ¹³ cm ^-2 and set to 7V, 3.0
Set to about × 10 ¹³ cm ^-2 and set to 5V.
^{Make it} about 0 × 10 ¹³ cm ⁻² . The boron implantation region IP is set by, for example, a given photomask.

Next, for example, arsenic, which is an N-type impurity, is subjected to an acceleration energy of 50 KeV and a dose of 4.0 × 10 ¹⁵ cm.
Ion implantation is performed at ^-2 to form N ⁺ regions 10, 12, and 14 (FIG. 9F). In this case, the arsenic implantation region IN
Is set by a given photomask, for example.

In the process of forming the P-type low-concentration impurity region (offset region) in the LDD structure of the P-type transistor, the process can be shortened by forming the P ⁺ region 16. In this case, it is necessary to obtain a desired Zener voltage under the process conditions (dose amount or the like) for forming the P-type low concentration impurity region. In this case, the P ⁺ region 16 is formed before the N ⁺ region 12 is formed.

[0059] However, in the like case of not forming a P ⁺ region 16 in the step of forming the low-concentration impurity regions of the P-type, after the formation of the N ⁺ region 12 may be formed a P ⁺ region 16.

Furthermore, if a desired Zener voltage can be obtained, it is possible to shorten the process by forming the P ⁺ region 16 in the process of forming the source region and the drain region of the P-type transistor.

In the manufacturing method 1 described above, FIG.
As shown in FIG. 5, the overlap region IV between the impurity-implanted region IN for forming the N ⁺ region 12 and the impurity-implanted region IP for forming the P ⁺ region 16 is narrow. For example, the overlap is about 1 to 2 μm in consideration of a mask alignment error. Therefore, as already described with reference to FIG. 8A, a semiconductor device in which the ESD withstand voltage is slightly reduced but the leakage current during normal operation is small can be provided.

(2) Manufacturing Method 2 FIGS. 10A to 10F are sectional views showing the steps of the manufacturing method 2.

The difference from the above-described manufacturing method 1 is that
In (E), the implantation region IP of boron as a P-type impurity is widened. The other parts are almost the same as those in the manufacturing method 1, and thus the detailed description is omitted.

According to the manufacturing method 2, as shown in FIG. 10F, the impurity implantation region IN for forming the N ⁺ region 12 and the impurity implantation region IP for forming the P ⁺ region 16 are formed. The overlap area IV becomes wider.
Therefore, as already described with reference to FIG. 8B, although the leakage current during the normal operation is slightly increased, the ESD withstand voltage can be increased and the variation of the Zener voltage can be reduced. (3) Manufacturing Method 3 FIGS. 11A to 11F are process cross-sectional views of Manufacturing Method 3.

The difference from the above-described manufacturing method 1 is that
In (E), boron as a P-type impurity is changed to, for example, 1
The point is that implantation is performed at a high energy of about 100 to 200 KeV. The other parts are almost the same as those in the manufacturing method 1, and thus the detailed description is omitted.

According to Manufacturing Method 3, since boron as a P-type impurity is implanted at a high energy, FIG.
As shown in (1), the P ⁺ region 16 can be formed in a region separated from the surface of the semiconductor device. This can prevent the P ⁺ region 16 from being exposed on the surface of the semiconductor device.

The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the present invention.

For example, the present invention can be applied not only to output transistors but also to various transistors. For example, the present invention can be applied to protection transistors of input transistors connected to pads.

The positional relationship between the second impurity region and the fourth impurity region is not limited to that described in the present embodiment, and various modifications can be made.

The process conditions for forming the impurity regions are not limited to those described in this embodiment.

The layout and device structure of the semiconductor device are not limited to those described in the present embodiment, and various modifications can be made.

The method of setting the zener voltage is preferably the one described in the present embodiment, but is not limited to this.

[0073]

[Brief description of the drawings]

FIG. 1A is a plan view of the background art, and FIG.
FIG. 2B is a cross-sectional view taken along line A1-A2 in FIG.

FIG. 2A is a plan view of the present embodiment, and FIG. 2B is a cross-sectional view taken along line B1-B2 in FIG. 2A.

FIG. 3 is a diagram for describing setting of a Zener voltage VZ.

FIGS. 4A and 4B are diagrams for explaining the impurity concentration distribution; FIG.

FIG. 5 is a diagram showing a relationship between a P ⁺ impurity concentration and a Zener voltage.

FIGS. 6A and 6B are diagrams for explaining a method of setting a gate length L to a minimum dimension according to a design rule.

FIG. 7 is a diagram for explaining a method of setting a contact size and the like to a minimum size according to a design rule.

FIGS. 8A and 8B are diagrams showing various forms of junction of a Zener diode.

FIGS. 9A to 9F are cross-sectional views illustrating the steps of the manufacturing method 1. FIGS.

FIGS. 10A to 10F are cross-sectional views illustrating the steps of the manufacturing method 2; FIGS.

FIGS. 11A to 11F are cross-sectional views illustrating the steps of the manufacturing method 3; FIGS.

[Explanation of symbols]

Reference Signs List 1 P well 2 Output transistor 4 Bipolar transistor 6 Gate electrode 10 N ⁺ region (first impurity region) 12 N ⁺ region (second impurity region) 14 N ⁺ region (third impurity region) 16 P ⁺ region (fourth impurity) Region) 20, 22, 24, 26 wiring layer 28 P ⁺ region 30 pad 32 high-voltage pulse 40 drain contact 41, 42, 44, 46 side 50 source contact 51, 52, 54, 56 side 60 element isolation film 62 channel stopper Layers 66, 67, 68 Low concentration impurity region 70 Side wall 201 P well 202 Output transistor 204 Bipolar transistor 206 Gate electrode 210 N ⁺ region 212 N ⁺ region 214 N ⁺ region 220, 222, 224, 226 Wiring layer 228 P ⁺ region 230 pad 232 high voltage pulse D Zener diode DA parasitic diode BP bipolar transistor BPP parasitic bipolar transistor

Claims (12)

[Claims] A first conductive type first impurity region having a gate electrode, a second conductive type first impurity region serving as a source region, and a second conductive type second impurity region serving as a drain region; A second conductivity type FET transistor formed in the first region, wherein the second impurity region is a collector region, the first region is a base region,
A bipolar transistor having a second conductivity type third impurity region as an emitter region, which is separated from the impurity region by an element; and a region adjacent to the second impurity region and formed between the second and third impurity regions. A semiconductor device comprising: a first conductivity type fourth impurity region; and a Zener diode formed by a junction with the second impurity region. 2. The FET according to claim 1, wherein the Zener voltage of the Zener diode is equal to the FET voltage.
A semiconductor device having a lower avalanche breakdown voltage in the drain region of the transistor. 3. The FET according to claim 1, wherein the Zener voltage of the Zener diode is the FET.
A semiconductor device, which is lower than a snapback voltage at the drain region of the transistor. 4. The semiconductor device according to claim 2, wherein a Zener voltage of the Zener diode is lower than one of the avalanche breakdown voltage and the snapback voltage and equal to or higher than an absolute maximum rated voltage of the semiconductor device. A semiconductor device characterized by the above-mentioned. 5. The semiconductor device according to claim 1, wherein the Zener voltage is controlled by an impurity concentration of the fourth impurity region. 6. The semiconductor device according to claim 1, wherein a gate length of the gate electrode of the FET transistor is a minimum dimension according to a design rule. 7. The drain transistor according to claim 1, wherein a size of a drain contact of the drain region of the FET transistor, a first side of the drain contact, and a third side of the drain region on the gate electrode side. A distance between a second side of the drain contact and a fourth side orthogonal to the third side of the drain region;
The size of the source contact of the source region of the transistor, the distance between the fifth side of the source contact and the seventh side of the source region on the gate electrode side, the sixth side of the source contact and the seventh side of the source region, A semiconductor device, wherein at least one of the distances to an eighth side orthogonal to the side has a minimum dimension according to a design rule. 8. The semiconductor device according to claim 1, wherein a junction in a direction substantially parallel to a surface of the semiconductor device among the junctions of the second impurity region and the four impurity regions intersects with the surface of the semiconductor device. A semiconductor device characterized by being wider than a junction in a direction. 9. A method for manufacturing a semiconductor device including a second conductivity type FET transistor and a bipolar transistor, wherein: a step of forming a gate electrode of the FET transistor; and a second conductivity type forming a source region of the FET transistor. -Type first impurity region, a second conductivity-type second impurity region serving as a drain region of the FET transistor and a collector region of the bipolar transistor, and a second conductivity-type third impurity region serving as an emitter region of the bipolar transistor Forming a first region of a first conductivity type serving as a base region of the bipolar transistor; and Forming a fourth impurity region of the first conductivity type forming a junction of the Zener diode with the two impurity regions; A method of manufacturing a semiconductor device. 10. The semiconductor device according to claim 9, wherein a junction in a direction substantially parallel to a surface of the semiconductor device among junctions of the second impurity region and the four impurity regions is more than a junction in a direction crossing the surface of the semiconductor device. A method of manufacturing a semiconductor device, wherein an impurity-implanted region for forming the second impurity region and an impurity-implanted region for forming the fourth impurity region are overlapped so as to be wider. 11. The method according to claim 9, wherein the fourth impurity region is formed in a region separated from a surface of the semiconductor device. 12. The method according to claim 9, wherein the fourth impurity region is formed as a low-concentration impurity region in an LDD structure of a first conductivity type FET transistor, and the first conductivity type F is formed.
A method for manufacturing a semiconductor device, wherein the method is performed in any one of the steps of forming a source region and a drain region of an ET transistor.