JPH11220167A - Semiconductor light-emitting device and manufacture thereof - Google Patents
Semiconductor light-emitting device and manufacture thereofInfo
- Publication number
- JPH11220167A JPH11220167A JP2179998A JP2179998A JPH11220167A JP H11220167 A JPH11220167 A JP H11220167A JP 2179998 A JP2179998 A JP 2179998A JP 2179998 A JP2179998 A JP 2179998A JP H11220167 A JPH11220167 A JP H11220167A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor light
- light emitting
- electrodes
- emitting element
- emitting device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
Landscapes
- Led Device Packages (AREA)
- Led Devices (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、たとえば青色発光
ダイオード等の光デバイスに利用される窒化ガリウム系
化合物を利用したフリップチップ型の半導体発光装置に
係り、特に配光性の向上を可能とした半導体発光装置及
びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a flip-chip type semiconductor light-emitting device using a gallium nitride compound used for an optical device such as a blue light-emitting diode, and more particularly to an improvement in light distribution. The present invention relates to a semiconductor light emitting device and a method for manufacturing the same.
【0002】[0002]
【従来の技術】GaN,GaAlN,InGaN及びI
nAlGaN等の窒化ガリウム系化合物の半導体の製造
では、その表面において半導体膜を成長させるための結
晶基板として、一般的には絶縁性のサファイアが利用さ
れる。このサファイアのような絶縁性の結晶基板を用い
る場合では、結晶基板側から電極を出すことができない
ので、半導体層に設けるp,nの電極は結晶基板と対向
する側の一面に形成されることになる。2. Description of the Related Art GaN, GaAlN, InGaN and I
In the production of gallium nitride based semiconductors such as nAlGaN, insulating sapphire is generally used as a crystal substrate for growing a semiconductor film on the surface. When an insulating crystal substrate such as sapphire is used, electrodes cannot be provided from the crystal substrate side, so that the p and n electrodes provided on the semiconductor layer are formed on one surface facing the crystal substrate. become.
【0003】たとえば、GaN系化合物半導体を利用し
た発光素子は、絶縁性の基板としてサファイア基板を用
いてその上面にn型層及びp型層を有機金属気相成長法
によって積層形成し、p型層の一部をエッチングしてn
型層を露出させ、これらのn型層とp型層のそれぞれに
n側電極及びp側電極を形成するというものがその基本
的な構成である。そして、p側電極を透明電極とした場
合であれば、これらのp側及びn側の電極にそれぞれボ
ンディングパッド部を形成して、リードフレームや基板
にそれぞれワイヤボンディングされる。For example, a light-emitting device using a GaN-based compound semiconductor uses a sapphire substrate as an insulating substrate, and forms an n-type layer and a p-type layer on the upper surface thereof by metal organic chemical vapor deposition to form a p-type layer. Etch part of the layer to n
The basic configuration is that the mold layer is exposed and an n-side electrode and a p-side electrode are formed on each of the n-type layer and the p-type layer. If the p-side electrode is a transparent electrode, bonding pads are formed on these p-side and n-side electrodes, respectively, and wire-bonded to a lead frame or a substrate.
【0004】一方、サファイア基板側から光を取り出す
ようにしたフリップチップ型の半導体発光素子では、p
側電極を透明電極としないままでこのp側及びn側の電
極のそれぞれにマイクロバンプを形成し、これらのマイ
クロバンプを基板またはリードフレームのp側及びn側
に接続する構成が採用されている。On the other hand, in a flip-chip type semiconductor light emitting device in which light is extracted from the sapphire substrate,
A configuration is adopted in which micro-bumps are formed on each of the p-side and n-side electrodes without the side electrodes being transparent electrodes, and these micro-bumps are connected to the p-side and n-side of the substrate or lead frame. .
【0005】図3はフリップチップ型の半導体発光素子
を利用したLEDランプの概略を示す縦断面図である。FIG. 3 is a longitudinal sectional view schematically showing an LED lamp using a flip-chip type semiconductor light emitting device.
【0006】図において、発光素子1は、絶縁性の透明
なサファイア基板1aの表面に、たとえばGaNバッフ
ァ層,n型GaN層,InGaN活性層,p型AlGa
N層及びp型GaN層を順に積層し、InGaN活性層
を発光層としたものである。そして、n型GaN層の上
面にn側電極20が、及びp型GaN層の上面にはp側
電極30がそれぞれ蒸着法によって形成され、更にこれ
らのn側電極20及びp側電極30の上にはそれぞれマ
イクロバンプ4,5を形成している。In FIG. 1, a light-emitting element 1 includes, for example, a GaN buffer layer, an n-type GaN layer, an InGaN active layer, and a p-type AlGa on a surface of an insulating transparent sapphire substrate 1a.
An N layer and a p-type GaN layer are sequentially stacked, and an InGaN active layer is used as a light emitting layer. An n-side electrode 20 is formed on the upper surface of the n-type GaN layer, and a p-side electrode 30 is formed on the upper surface of the p-type GaN layer by vapor deposition. Have micro bumps 4 and 5, respectively.
【0007】発光素子1を搭載するリードフレーム6の
マウント部6aには、発光素子1に外部から静電気が印
加されないようにしてその破壊を防止するために、静電
気保護素子としてツェナーダイオード7を設ける。この
ツェナーダイオード7は、導電性のAgペースト8によ
ってマウント部6aに接着固定され、その上面にはp側
及びn側の電極7a,7bをそれぞれ形成したものであ
る。A mount 6a of the lead frame 6 on which the light emitting element 1 is mounted is provided with a zener diode 7 as an electrostatic protection element in order to prevent external destruction of the light emitting element 1 by preventing static electricity from being applied thereto. The Zener diode 7 is bonded and fixed to a mount 6a with a conductive Ag paste 8, and has p-side and n-side electrodes 7a and 7b formed on the upper surface thereof.
【0008】発光素子1は、サファイア基板1aが上面
を向く姿勢としてツェナーダイオード7の上に搭載さ
れ、n側及びp側のマイクロバンプ4,5をそれぞれツ
ェナーダイオード7の電極7a,7bに接合することに
よって電気的に導通させる。そして、リードフレーム6
の上端部を含めて発光素子1の全体がエポキシ樹脂9に
よって封止され、図示の形状のLEDランプが構成され
る。The light emitting element 1 is mounted on the Zener diode 7 with the sapphire substrate 1a facing upward, and the n-side and p-side micro bumps 4 and 5 are respectively joined to the electrodes 7a and 7b of the Zener diode 7. In this way, electrical conduction is achieved. And lead frame 6
The entire light emitting element 1 including the upper end portion is sealed with the epoxy resin 9 to form an LED lamp having the shape shown in the figure.
【0009】発光素子1への通電があるときには、半導
体積層膜中のInGaN活性層が発光層となり、この発
光層からの光がサファイア基板1a及びp側電極30の
両方向へ向かう。そして、p側電極30を光透過しない
反射型の積層膜としておくことにより、サファイア基板
1aの上面からの発光輝度を最大としてこの面を主光取
出し面とすることができる。When the light emitting element 1 is energized, the InGaN active layer in the semiconductor laminated film becomes a light emitting layer, and light from this light emitting layer travels in both directions of the sapphire substrate 1a and the p-side electrode 30. By forming the p-side electrode 30 as a reflection type laminated film that does not transmit light, this surface can be used as a main light extraction surface with maximum light emission luminance from the upper surface of the sapphire substrate 1a.
【0010】このようなLEDランプの製造において
は、マイクロバンプ4,5と電極7a,7bとを電気的
に導通させるとともに発光素子1をツェナーダイオード
7の上に固定するため、たとえば導電性の接着剤を用い
たり、超音波加熱圧着による接合が必要である。そし
て、超音波加熱圧着法による場合では、マイクロバンプ
4,5の先端を電極7a,7bの表面に突き当てた状態
として加熱及び荷重を加えた状態で超音波を印加し、こ
れらの部材どうしの溶融固化による接合が行われる。In the manufacture of such an LED lamp, in order to electrically connect the micro bumps 4 and 5 and the electrodes 7a and 7b and fix the light emitting element 1 on the Zener diode 7, for example, a conductive adhesive is used. It is necessary to use a bonding agent or join by ultrasonic heating and pressure bonding. In the case of the ultrasonic heating and compression bonding method, ultrasonic waves are applied while heating and applying a load with the tips of the micro bumps 4 and 5 abutting against the surfaces of the electrodes 7a and 7b. Joining by melting and solidification is performed.
【0011】[0011]
【発明が解決しようとする課題】マイクロバンプ4,5
の機能は、電極7a,7bとの導通接続だけでなく、発
光素子1の下面とツェナーダイオード7の上面との間に
クリアランスを持たせることにより、これらの発光素子
1とツェナーダイオード7との間の短絡を防止すること
である。したがって、マイクロバンプ4,5は或る程度
の高さ寸法を持つように形成することが必要であり、通
常の場合では50μm程度の長さが最適とされている。SUMMARY OF THE INVENTION Micro bumps 4, 5
The function of (1) is to provide a clearance between the lower surface of the light emitting element 1 and the upper surface of the Zener diode 7 in addition to the conductive connection between the electrodes 7a and 7b, thereby providing a clearance between the light emitting element 1 and the Zener diode 7. Is to prevent short-circuiting. Therefore, it is necessary to form the micro bumps 4 and 5 so as to have a certain height dimension, and in a normal case, the length is about 50 μm.
【0012】ところが、マイクロバンプ4,5をn側電
極20及びp側電極30に形成する方法は、Auワイヤ
の先端を球状にしてこの部分を電極上に押圧し、超音波
と熱で球状部をつぶしながら電極上に溶着させた後、A
uワイヤを引っ張ってその幹部で切断するというもので
あり、その成形方法からスタッドバンプと呼ばれること
が多い。このようなスタッドバンプでは、たとえば蒸着
法等による成膜方法とは異なって、高さ寸法すなわちn
側及びp側の電極からの突き出し長さにばらつきを生じ
やすい。したがって、図3に示す発光素子1の例でも、
マイクロバンプ4,5の長さが不揃いになってしまう恐
れがある。However, the method of forming the micro-bumps 4 and 5 on the n-side electrode 20 and the p-side electrode 30 is to make the tip of the Au wire spherical and press this part on the electrode, and to apply the spherical portion by ultrasonic waves and heat. After welding on the electrode while crushing
The u-wire is pulled and cut at its trunk, and is often called a stud bump because of its molding method. In such a stud bump, for example, the height dimension, ie, n
Variations are likely to occur in the protruding lengths from the side and p-side electrodes. Therefore, in the example of the light emitting element 1 shown in FIG.
The lengths of the micro bumps 4 and 5 may be irregular.
【0013】このようにマイクロバンプ4,5の長さが
一様でないと、発光素子1をツェナーダイオード7の上
に搭載して圧着接合したとき、発光素子1の姿勢が傾い
てしまう。たとえば、マイクロバンプ4のほうが他方の
マイクロバンプ5よりも短いと、発光素子1は右下がり
の姿勢となってその発光層も同じ姿勢をとることにな
る。したがって、発光素子1の向きはマイクロバンプ
4,5が揃っていないと、様々に変わってしまうことに
なり、多数のLEDランプの配列によるパネル等の場合
では、各発光素子1からの配光性に一様性がなくなり、
表示画像に好ましくない影響を及ぼすことになる。If the lengths of the micro bumps 4 and 5 are not uniform as described above, the posture of the light emitting element 1 is inclined when the light emitting element 1 is mounted on the Zener diode 7 and pressure-bonded. For example, if the micro-bump 4 is shorter than the other micro-bump 5, the light-emitting element 1 has a downward-sloping posture and the light-emitting layer also has the same posture. Therefore, if the micro bumps 4 and 5 are not aligned, the direction of the light emitting element 1 will be variously changed. In the case of a panel or the like in which a large number of LED lamps are arranged, the light distribution from each light emitting element 1 will be different. Loses uniformity,
This has an undesirable effect on the displayed image.
【0014】また、マイクロバンプ4,5自身は、発光
素子1とツェナーダイオード7との間の短絡防止に十分
貢献するが、各発光素子1のそれぞれについてこれらの
マイクロバンプ4,5を形成する必要がある。したがっ
て、n側電極20やp側電極30を金属蒸着法によって
成膜した一次製品に対して、マイクロバンプ4,5の付
加という工程が必要となり、生産性及び歩留り向上の障
害ともなる。Although the micro bumps 4 and 5 themselves sufficiently contribute to preventing a short circuit between the light emitting element 1 and the Zener diode 7, it is necessary to form the micro bumps 4 and 5 for each light emitting element 1. There is. Therefore, a step of adding the micro bumps 4 and 5 is required for a primary product in which the n-side electrode 20 and the p-side electrode 30 are formed by a metal deposition method, which hinders improvement in productivity and yield.
【0015】このように従来のマイクロバンプを用いる
発光素子の搭載面側への接合構造では、発光素子の姿勢
の乱れによる配光性の劣化を招くほか、マイクロバンプ
形成用の高価なAuを消費してしまうという問題があ
る。As described above, in the conventional bonding structure using the microbumps on the mounting surface side of the light emitting element, the light distribution property is deteriorated due to the disturbance of the attitude of the light emitting element, and expensive Au for forming the microbump is consumed. There is a problem of doing it.
【0016】本発明において解決すべき課題は、発光素
子の姿勢の均一化によって配光性を安定させるとともに
成形工数も少なくして、生産性の向上が可能な半導体発
光装置を提供することにある。The problem to be solved in the present invention is to provide a semiconductor light emitting device which can stabilize the light distribution by uniformizing the posture of the light emitting element, reduce the number of molding steps, and improve the productivity. .
【0017】[0017]
【課題を解決するための手段】本発明は、基板またはリ
ードフレーム等の基材の搭載面にフリップチップ型の半
導体発光素子を搭載し、この半導体発光素子のp側及び
n側の電極を搭載面側の対応する電極に導通接続し、前
記搭載面側と反対側の面を主光取出し面とするGaN系
の半導体発光装置において、前記p側及びn側の電極
を、前記半導体発光素子のp型層及びn型層のそれぞれ
の表面に金属蒸着膜によって形成し、これらの電極の厚
さによって半導体発光素子と搭載面及びその電極との間
に短絡干渉がない隙間を形成可能としてなることを特徴
とする。According to the present invention, a flip-chip type semiconductor light emitting device is mounted on a mounting surface of a substrate such as a substrate or a lead frame, and p-side and n-side electrodes of the semiconductor light emitting device are mounted. In a GaN-based semiconductor light emitting device which is electrically connected to a corresponding electrode on the surface side and has a surface opposite to the mounting surface side as a main light extraction surface, the p-side and n-side electrodes are connected to the semiconductor light-emitting element. A metal-deposited film is formed on each surface of the p-type layer and the n-type layer, and the thickness of these electrodes makes it possible to form a gap without short-circuit interference between the semiconductor light emitting element, the mounting surface, and the electrodes. It is characterized by.
【0018】このような構成では、マイクロバンプを形
成しないまま、発光素子のp側及びn側の電極によって
できる間隔を発光素子と搭載面側との間の短絡干渉の防
止に利用でき、しかも電極は金属蒸着膜によって形成さ
れるので、その肉厚を均一にして発光素子の姿勢を一様
に揃えることができる。In such a configuration, the gap formed by the p-side and n-side electrodes of the light-emitting element can be used to prevent short-circuit interference between the light-emitting element and the mounting surface without forming the microbump. Is formed by a metal vapor-deposited film, the thickness of the light-emitting element can be made uniform, and the posture of the light-emitting element can be made uniform.
【0019】また、本発明の製造方法は、p側及びn側
の電極を搭載面側の対応する電極に対して300〜35
0℃の温度雰囲気で加熱圧着して半導体発光素子を搭載
面に接合することを特徴とする。Further, according to the manufacturing method of the present invention, the p-side electrode and the n-side electrode are set at 300 to 35 with respect to the corresponding electrodes on the mounting surface side.
The semiconductor light emitting device is bonded to the mounting surface by heating and pressing in a temperature atmosphere of 0 ° C.
【0020】この製造方法では、加熱温度を300〜3
50℃とすることで、発光素子であるGaN系LEDに
対して、特性の劣化や外見上の変色等の異常を生じるこ
となく電極間はAu−Snの共晶により安定した接合を
行うことができる。In this manufacturing method, the heating temperature is set to 300 to 3
By setting the temperature to 50 ° C., it is possible to perform stable bonding between the electrodes by Au—Sn eutectic without causing abnormalities such as deterioration of characteristics and appearance discoloration to the GaN-based LED which is a light emitting element. it can.
【0021】[0021]
【発明の実施の形態】請求項1に記載の発明は、基板ま
たはリードフレーム等の基材の搭載面にフリップチップ
型の半導体発光素子を搭載し、この半導体発光素子のp
側及びn側の電極を搭載面側の対応する電極に導通接続
し、前記搭載面側と反対側の面を主光取出し面とするG
aN系の半導体発光装置において、前記p側及びn側の
電極を、前記半導体発光素子のp型層及びn型層のそれ
ぞれの表面に金属蒸着膜によって形成し、これらの電極
の厚さによって半導体発光素子と搭載面及びその電極と
の間に短絡干渉がない隙間を形成可能としてなるもので
あり、マイクロバンプを形成しないまま、発光素子のp
側及びn側の電極によってできる間隔を発光素子と搭載
面側との間の短絡干渉の防止に利用できるとともに、電
極の肉厚を均一にして発光素子の姿勢を一様に揃えると
いう作用を有する。According to the first aspect of the present invention, a flip-chip type semiconductor light emitting device is mounted on a mounting surface of a substrate such as a substrate or a lead frame.
And the n-side electrode is electrically connected to the corresponding electrode on the mounting surface side, and the surface opposite to the mounting surface side is used as a main light extraction surface.
In an aN-based semiconductor light-emitting device, the p-side and n-side electrodes are formed by metal deposition films on respective surfaces of a p-type layer and an n-type layer of the semiconductor light-emitting element, and the thickness of these electrodes varies depending on the thickness of the semiconductor. It is possible to form a gap without short-circuit interference between the light emitting element and the mounting surface and its electrodes.
The gap formed by the n-side and n-side electrodes can be used to prevent short-circuit interference between the light-emitting element and the mounting surface side, and has the effect of making the thickness of the electrode uniform and the posture of the light-emitting element uniform. .
【0022】請求項2の発明は、p側及びn側の電極の
厚さを10〜20μmとしてなる請求項1記載の半導体
発光装置であり、このような電極の厚さであれば、発光
素子と搭載面側との短絡干渉を確実に防止するという作
用を有する。According to a second aspect of the present invention, there is provided the semiconductor light emitting device according to the first aspect, wherein the p-side and n-side electrodes have a thickness of 10 to 20 μm. Has the effect of reliably preventing short-circuit interference between the device and the mounting surface.
【0023】請求項3の発明は、p側及びn側の電極を
それぞれTiとAuとの積層膜とし、前記搭載面側の対
応する電極をAuとSnとの合金としてなる請求項1ま
たは2記載の半導体発光装置であり、TiはAuの付着
力強化材料であり、Auは基板またはリードフレームの
電極をAuとSnの合金とすることで、熱圧着時のAu
との共晶温度を低くできるという作用を有する。According to a third aspect of the present invention, the p-side and n-side electrodes are each a laminated film of Ti and Au, and the corresponding electrodes on the mounting surface side are an alloy of Au and Sn. The semiconductor light emitting device according to the above, wherein Ti is a material for enhancing the adhesion of Au, and Au is an alloy of Au and Sn for the electrode of the substrate or the lead frame, so that Au at the time of thermocompression bonding is used.
Has the effect of lowering the eutectic temperature with
【0024】請求項4に記載の発明は、前記基板の上に
静電気保護素子を搭載して前記基材に導通させ、前記静
電気保護素子の上に前記半導体発光素子をp側及びn側
の電極が逆極性となる関係として搭載接合してなる請求
項1から3のいずれかに記載の半導体発光装置であり、
静電気保護素子によって半導体発光素子の静電破壊が防
止されるという作用を有する。According to a fourth aspect of the present invention, there is provided an electrostatic protection element mounted on the substrate and electrically connected to the substrate, and the semiconductor light emitting element is provided on the p-side and n-side electrodes on the electrostatic protection element. The semiconductor light emitting device according to any one of claims 1 to 3, wherein the semiconductor light emitting device is mounted and bonded as a relationship having opposite polarities.
This has the effect that the electrostatic protection element prevents electrostatic breakdown of the semiconductor light emitting element.
【0025】請求項5の発明は、請求項1〜4のいずれ
かに記載の半導体発光装置の製造方法であって、前記p
側及びn側の電極を搭載面側の対応する電極に対して3
00〜350℃の温度雰囲気で加熱圧着して半導体発光
素子を搭載面に接合する半導体発光装置の製造方法であ
り、発光素子であるGaN系LEDに対して、特性の劣
化や外見上の変色等の異常を生じることがなく、電極間
はAu−Snの共晶による安定した接合を行うことがで
きるという作用を有する。According to a fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor light emitting device according to any one of the first to fourth aspects, wherein
Side and n-side electrodes are 3
This is a method for manufacturing a semiconductor light emitting device in which a semiconductor light emitting element is bonded to a mounting surface by heat-pressing in a temperature atmosphere of 00 to 350 ° C. This has the effect that a stable joining by Au-Sn eutectic can be performed between the electrodes without causing abnormalities in the above.
【0026】以下に、本発明の実施の形態の具体例を図
面を参照しながら説明する。図1は本発明の一実施の形
態による半導体発光装置の要部の拡大図、図2は発光素
子の斜視図である。なお、発光素子はn側及びp側の電
極の形状以外の構成は従来例のものと同じであってツェ
ナーダイオードも同様であり、電極以外について同一部
材には共通の符号で指示し、その詳細な説明は省略す
る。Hereinafter, a specific example of the embodiment of the present invention will be described with reference to the drawings. FIG. 1 is an enlarged view of a main part of a semiconductor light emitting device according to an embodiment of the present invention, and FIG. 2 is a perspective view of a light emitting element. The configuration of the light emitting element is the same as that of the conventional example except for the shapes of the n-side and p-side electrodes, and the zener diode is also the same. Detailed description is omitted.
【0027】図2において、発光素子1はサファイア基
板1aの上面にn型層1b及びp型層1cを形成すると
ともに、これらのn型層1b及びp型層1cの上面には
それぞれn側電極2及びp側電極3を形成している。そ
して、p型層1cの表面にはたとえばNi,Ptの積層
膜またはSb,Ptの積層膜からなる銀白色の光反射膜
1dを形成することにより、発光層からの光をこの光反
射膜1dからサファイア基板1a方向に反射させるよう
にすることで、サファイア基板1aの下面を主光取出し
面とすることができる。In FIG. 2, the light emitting element 1 has an n-type layer 1b and a p-type layer 1c formed on the upper surface of a sapphire substrate 1a, and an n-side electrode is formed on the upper surface of each of the n-type layer 1b and the p-type layer 1c. 2 and a p-side electrode 3 are formed. By forming a silver-white light reflection film 1d made of a laminated film of, for example, Ni and Pt or a laminated film of Sb and Pt on the surface of the p-type layer 1c, light from the light emitting layer is reflected by the light reflection film 1d. Is reflected in the direction of the sapphire substrate 1a, so that the lower surface of the sapphire substrate 1a can be used as a main light extraction surface.
【0028】n側電極2及びp側電極3は、たとえばT
iとAuの合金を材料として蒸着法によって形成された
ものであり、その高さ寸法は10〜20μm程度であ
る。そして、サファイア基板1aの底面を水平面上に位
置させたとき、これらのn側及びp側の電極2,3の上
端面の高さは正確に一致して同一平面内に含まれるよう
に成形する。このような成形は、金属を用いた蒸着法で
あれば高い精度で可能であり、n側及びp側の電極2,
3の上端面を平滑で一様な平面として形成することがで
きる。The n-side electrode 2 and the p-side electrode 3 are, for example,
It is formed by an evaporation method using an alloy of i and Au as a material, and has a height of about 10 to 20 μm. Then, when the bottom surface of the sapphire substrate 1a is positioned on a horizontal plane, the heights of the upper end surfaces of the n-side and p-side electrodes 2 and 3 are exactly the same and are formed so as to be included in the same plane. . Such a molding can be performed with high precision by a vapor deposition method using a metal, and the n-side and p-side electrodes 2 are formed.
3 can be formed as a smooth and uniform plane.
【0029】ツェナーダイオード7の上面に形成するp
側及びn側の電極7a,7bの金属材料としては、発光
素子1のn側及びp側の電極2,3を加熱圧着法によっ
て接合することから、AuとSnの合金が好適である。
この場合、AuとSnの最適比率は、Au:Sn=
(3:9)〜(3:11)程度であり、電極7a,7b
の厚さは5μm程度とすることが好ましい。The p formed on the upper surface of the Zener diode 7
As the metal material of the side and n-side electrodes 7a and 7b, an alloy of Au and Sn is preferable since the n-side and p-side electrodes 2 and 3 of the light emitting element 1 are joined by a heat compression method.
In this case, the optimal ratio of Au to Sn is Au: Sn =
(3: 9) to (3:11), and the electrodes 7a, 7b
Is preferably about 5 μm.
【0030】発光素子1は、従来構造のものと同様に、
サファイア基板1aをマウント部6aの搭載面と逆向き
にして図1に示すようにツェナーダイオード7の上面に
搭載される。このとき、n側電極2及びp側電極3はツ
ェナーダイオード7のp側及びn側の電極7a,7bに
直に加熱圧着法によって接合される。The light emitting element 1 has a structure similar to that of the conventional structure.
The sapphire substrate 1a is mounted on the top surface of the Zener diode 7 as shown in FIG. At this time, the n-side electrode 2 and the p-side electrode 3 are directly joined to the p-side and n-side electrodes 7a and 7b of the Zener diode 7 by a heat compression method.
【0031】この加熱圧着による発光素子1のn側及び
p側の電極2,3とツェナーダイオード7の電極7a,
7bとの接合は、加熱温度が300〜350℃の範囲で
あって加圧力は10g〜20g程度の範囲であればよ
い。このような条件であれば、AuとSnの共晶がn側
及びp側の電極2,3の表面で一様に進行するので、n
側及びp側の電極2,3の接合端面がたとえば円弧状の
凸面等に変形することが防止され、発光素子1の姿勢が
傾くことを防止できる。また、この温度範囲であれば、
発光素子であるGaN系LEDの特性が劣化することの
ない加熱圧着が可能である。The electrodes 2 and 3 on the n-side and p-side of the light-emitting element 1 and the electrodes 7 a and
Bonding with 7b may be performed if the heating temperature is in the range of 300 to 350 ° C. and the pressing force is in the range of about 10 g to 20 g. Under such conditions, the eutectic of Au and Sn proceeds uniformly on the surfaces of the n-side and p-side electrodes 2 and 3, and therefore n
The joint end surfaces of the side and p-side electrodes 2 and 3 are prevented from being deformed into, for example, an arc-shaped convex surface, and the posture of the light emitting element 1 can be prevented from tilting. In this temperature range,
Heat compression bonding can be performed without deteriorating the characteristics of the GaN-based LED that is a light emitting element.
【0032】ここで、従来のGaN系化合物半導体発光
素子におけるp側及びn側の電極の厚さは1〜2μm程
度であり、したがって本発明においてはp側及びn側の
電極2,3の厚さは従来構造に比べると10倍程度大き
い。そして、従来例で示したマイクロバンプ4,5の厚
さは約30μm程度であって、発光素子1とツェナーダ
イオード7との間の間隔を保って短絡を防止するのに十
分な厚みを持つ。Here, the thickness of the p-side and n-side electrodes in the conventional GaN-based compound semiconductor light emitting device is about 1 to 2 μm, and therefore, in the present invention, the thickness of the p-side and n-side electrodes 2 and 3 is The size is about 10 times larger than the conventional structure. The thickness of the micro-bumps 4 and 5 shown in the conventional example is about 30 μm, and has a sufficient thickness to keep a space between the light-emitting element 1 and the Zener diode 7 to prevent a short circuit.
【0033】一方、本発明においては、n側電極2を2
0μmの厚さ及びp側電極3を10μmの厚さとした場
合、従来のマイクロバンプ4,5による隙間よりは小さ
いが、最小でp側電極3によって10μmの隙間を確保
することができる。そして、この10μm程度の隙間で
あれば、発光素子1とツェナーダイオード7との間の接
触を避けることができ、短絡についての問題は生じな
い。On the other hand, in the present invention, the n-side electrode 2 is
When the thickness is 0 μm and the thickness of the p-side electrode 3 is 10 μm, the gap of 10 μm can be secured by the p-side electrode 3 at a minimum, although it is smaller than the gap formed by the conventional micro bumps 4 and 5. If the gap is about 10 μm, contact between the light emitting element 1 and the Zener diode 7 can be avoided, and the problem of short circuit does not occur.
【0034】また、TiとAuの合金を材料とする発光
素子1のn側及びp側の電極2,3と、AuとSnとの
合金であるツェナーダイオード7の電極7a,7bとの
加熱圧着であれば、300℃〜350℃という比較的低
温で均一にAuとSnの共晶による接合を行うことがで
きるとともに、光反射膜1dとの接合もTiにより付着
強度を強く保つことができる。The n-side and p-side electrodes 2 and 3 of the light-emitting element 1 made of an alloy of Ti and Au are heat-pressed to the electrodes 7a and 7b of a zener diode 7 made of an alloy of Au and Sn. In this case, the eutectic bonding of Au and Sn can be uniformly performed at a relatively low temperature of 300 ° C. to 350 ° C., and the bonding strength with the light reflection film 1d can be maintained strongly by Ti.
【0035】以上の構成において、発光素子1に金属蒸
着法によって形成したn側及びp側の電極2,3は、ツ
ェナーダイオード7との接合端面までの長さを高精度で
製作できるので、電極7a,7bの表面に突き合わせし
て接合したとき、発光素子1の姿勢が傾くことが防止さ
れる。そして、n側及びp側の電極2,3の接合端面も
一様な平坦面として形成することで、電極7a,7bに
対して適正な接合が可能となり、発光素子1の傾斜を更
に一層効果的になくすことができる。In the above arrangement, the n-side and p-side electrodes 2 and 3 formed on the light emitting element 1 by metal vapor deposition can be manufactured with high precision in the length up to the junction end face with the Zener diode 7. When the light-emitting elements 1 are joined to the surfaces of the light-emitting elements 1a and 7b, the inclination of the light-emitting element 1 is prevented. Also, by forming the joint end surfaces of the n-side and p-side electrodes 2 and 3 as uniform flat surfaces, proper joining to the electrodes 7a and 7b becomes possible, and the inclination of the light emitting element 1 is further improved. Can be eliminated.
【0036】更に、加熱圧着による熱や圧力の負荷条件
を、n側及びp側の電極2,3の接合端面がたとえば突
き出し方向に膨出変形することがない範囲に設定するこ
とで、これらの電極2,3の接合端の平坦度を高く維持
できる。Furthermore, by setting the load conditions of heat and pressure by the thermocompression bonding within a range in which the joint end surfaces of the n-side and p-side electrodes 2 and 3 do not swell and deform in the protruding direction, for example. The flatness of the joining ends of the electrodes 2 and 3 can be kept high.
【0037】したがって、発光素子1をツェナーダイオ
ード7に対して正しい姿勢として接合でき、多数の発光
素子1を配列するディスプレイパネルであっても、配光
性に優れた鮮明な画像を再生することができる。Accordingly, the light emitting element 1 can be bonded to the zener diode 7 in a correct posture, and even a display panel having a large number of light emitting elements 1 can reproduce a clear image excellent in light distribution. it can.
【0038】なお、以上の実施の形態では、発光素子を
ツェナーダイオードに搭載する例を示したが、リードフ
レームや基板に搭載する場合でも本発明が適用できるこ
とは無論である。In the above embodiment, an example is shown in which the light emitting element is mounted on a Zener diode. However, it goes without saying that the present invention can be applied to a case where the light emitting element is mounted on a lead frame or a substrate.
【0039】[0039]
【発明の効果】請求項1の発明では、肉厚としたp側及
びn側の電極を干渉短絡防止のための隙間を形成するの
に兼用するので、従来のようにマイクロバンプを形成す
る工程がなくなり、製造歩留りの向上が図れる。また、
電極を金属蒸着膜によって形成するので、その肉厚及び
接合端面の精度を高く維持することができ、発光素子の
姿勢の乱れのないアセンブリが可能となる。According to the first aspect of the present invention, the thicker p-side and n-side electrodes are also used to form a gap for preventing interference short-circuit, so that the step of forming a micro-bump as in the prior art is performed. And the production yield can be improved. Also,
Since the electrodes are formed of a metal vapor-deposited film, the thickness of the electrodes and the accuracy of the joint end surface can be maintained at a high level, and an assembly in which the posture of the light emitting element is not disturbed is possible.
【0040】請求項2の発明では、p側及びn側の電極
の厚さを10〜20μmとすることで、発光素子と搭載
面側との間の短絡を確実に防止できる。According to the second aspect of the invention, by setting the thickness of the p-side and n-side electrodes to 10 to 20 μm, a short circuit between the light emitting element and the mounting surface can be reliably prevented.
【0041】請求項3の発明では、p側及びn側の電極
の材料をTiとAuの積層膜とすることで、発光素子と
の付着強度及び基板またはリードフレーム側のAuとS
nとの合金からなる電極と比較的低温で熱圧着が可能に
なり、製造上での歩留りの向上が図られる。According to the third aspect of the present invention, the material of the p-side and n-side electrodes is a laminated film of Ti and Au, so that the adhesion strength to the light emitting element and the Au and S on the substrate or the lead frame side are formed.
Thermocompression bonding can be performed at a relatively low temperature with an electrode made of an alloy of n and the production yield is improved.
【0042】請求項4の発明では、静電気保護素子を備
えることによって、静電耐圧が低いGaN系の半導体発
光素子の静電耐圧を上げることができ、過電流等による
静電破壊が防止される。According to the fourth aspect of the present invention, by providing the electrostatic protection element, the electrostatic breakdown voltage of the GaN-based semiconductor light emitting element having a low electrostatic breakdown voltage can be increased, and the electrostatic breakdown due to an overcurrent or the like can be prevented. .
【0043】請求項5の発明では、加熱温度を300℃
〜350℃とすることで、GaN系発光素子の特性を劣
化させることなく、しかも電極間はAu,Snの一様な
共晶による安定した接合が得られる。According to the fifth aspect of the present invention, the heating temperature is set to 300 ° C.
By setting the temperature to 350 ° C., a stable junction can be obtained between the electrodes by uniform eutectic of Au and Sn without deteriorating the characteristics of the GaN-based light emitting device.
【図1】本発明の一実施の形態を示す図であって、マウ
ント部上のツェナーダイオードに発光素子を加熱圧着し
た状態を示す図FIG. 1 is a view showing one embodiment of the present invention, and is a view showing a state in which a light emitting element is heated and pressed on a Zener diode on a mount portion.
【図2】発光素子の概要を示す斜視図FIG. 2 is a perspective view showing an outline of a light emitting element.
【図3】従来のフリップチップ型の発光素子を備えたL
EDランプの概略縦断面図FIG. 3 shows a conventional L-type chip having a flip-chip type light emitting element.
Schematic vertical sectional view of an ED lamp
1 発光素子 1a サファイア基板 1b n型層 1c p型層 1d 光反射膜 2 n側電極 3 p側電極 4,5 マイクロバンプ 6 リードフレーム 6a マウント部 7 ツェナーダイオード 7a,7b 電極 8 Agペースト 9 エポキシ樹脂 Reference Signs List 1 light emitting element 1a sapphire substrate 1b n-type layer 1c p-type layer 1d light reflection film 2 n-side electrode 3 p-side electrode 4,5 microbump 6 lead frame 6a mounting part 7 Zener diode 7a, 7b electrode 8 Ag paste 9 epoxy resin
Claims (5)
載面にフリップチップ型の半導体発光素子を搭載し、こ
の半導体発光素子のp側及びn側の電極を搭載面側の対
応する電極に導通接続し、前記搭載面側と反対側の面を
主光取出し面とするGaN系の半導体発光装置におい
て、前記p側及びn側の電極を、前記半導体発光素子の
p型層及びn型層のそれぞれの表面に金属蒸着膜によっ
て形成し、これらの電極の厚さによって半導体発光素子
と搭載面及びその電極との間に短絡干渉がない隙間を形
成可能としてなる半導体発光装置。1. A flip-chip type semiconductor light emitting device is mounted on a mounting surface of a substrate such as a substrate or a lead frame, and p-side and n-side electrodes of the semiconductor light emitting device are connected to corresponding electrodes on the mounting surface side. In the GaN-based semiconductor light-emitting device, wherein the surface opposite to the mounting surface side is a main light extraction surface, the p-side and n-side electrodes are connected to the p-type layer and the n-type layer of the semiconductor light-emitting element. A semiconductor light emitting device which is formed on each surface by a metal vapor deposition film, and which can form a gap without short-circuit interference between the semiconductor light emitting element and the mounting surface and its electrodes by the thickness of these electrodes.
20μmとしてなる請求項1記載の半導体発光装置。2. The thickness of the p-side and n-side electrodes is 10 to
2. The semiconductor light emitting device according to claim 1, wherein the thickness is 20 μm.
とAuとの積層膜とし、前記搭載面側の対応する電極を
AuとSnとの合金としてなる請求項1または2記載の
半導体発光装置。3. The p-side and n-side electrodes are each made of Ti.
3. The semiconductor light emitting device according to claim 1, wherein the semiconductor light emitting device is a stacked film of Au and Au, and the corresponding electrode on the mounting surface side is an alloy of Au and Sn.
て前記基材に導通させ、前記静電気保護素子の上に前記
半導体発光素子をp側及びn側の電極が逆極性となる関
係として搭載接合してなる請求項1から3のいずれかに
記載の半導体発光装置。4. An electrostatic protection element is mounted on the substrate and is electrically connected to the substrate, and the semiconductor light emitting element is placed on the electrostatic protection element such that p-side and n-side electrodes have opposite polarities. 4. The semiconductor light emitting device according to claim 1, wherein the device is mounted and joined.
発光装置の製造方法であって、前記p側及びn側の電極
を搭載面側の対応する電極に対して300〜350℃の
温度雰囲気で加熱圧着して半導体発光素子を搭載面に接
合する半導体発光装置の製造方法。5. The method for manufacturing a semiconductor light emitting device according to claim 1, wherein the p-side electrode and the n-side electrode are disposed at a temperature of 300 to 350 ° C. with respect to a corresponding electrode on a mounting surface side. A method for manufacturing a semiconductor light-emitting device in which a semiconductor light-emitting element is bonded to a mounting surface by thermocompression bonding in a temperature atmosphere.
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Cited By (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20020082143A (en) * | 2001-04-23 | 2002-10-30 | 도요다 고세이 가부시키가이샤 | Semiconductor light-emitting device |
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