JPH11204438A - Compound semiconductor epitaxial wafer and manufacture of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To restrain harmful step bunching and improve characteristics of an element, by limiting a substrate temperature within a specified ranqe and using a specified Ga material. SOLUTION: Harmful step bunching is generated when a substrate temperature is approxmmately 570 deg.C or higher. Thus, epitaxial growth is carried out at a substrate temperature of 565 deg.C or lower. Moreover, in such a low- temperature range, triethyl gallium(TEG) is used as a Ga material in order to prevent mixture of carbon and oxygen. Specifically, a compound semiconductor epitaxial wafer containing Ga compound semiconductor epitaxial is manufactured by limiting the substrate temperature within a range from approximately 505 deg.C to 565 deg.C and by using a metalorganic vapor phase epitaxy(MOVPE) using TEG as a Ga material. Thus, since generation of harmful step bunching can be prevented, a high-definition compound semiconductor epitaxial wafer for FET or for HEMT can be provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a compound semiconductor epitaxial wafer and a method for manufacturing the same.

[0002]

2. Description of the Related Art At present, mobile communication, satellite broadcasting, etc.
ET (Field Effect Transistor, Field Effect Transistor) and HEMT (High Electron Mobility Transistor,
Elements such as electron mobility transistors) are frequently used.

Generally, these devices are manufactured using a compound semiconductor epitaxial wafer manufactured by metal organic chemical vapor deposition (MOVPE).

FIG. 1 is a schematic diagram showing an epitaxial layer structure of a general FET wafer.

FIG. 2 is a schematic diagram of an epitaxial layer structure of a general HEMT wafer.

FIGS. 1 and 2 show a general FET.
Of the epitaxial layer of the wafer for HEMT and the wafer for HEMT will be described.

In the example of the FET wafer shown in FIG.
An undoped AlGaAs layer, an undoped GaAs layer, and an n-type GaAs layer are sequentially provided on a GaAs substrate, and an undoped AlGaAs layer and an undoped GaAs layer are provided.
The s layer is the buffer layer.

In the example of the HEMT wafer shown in FIG. 2, an undoped AlGaAs is sequentially formed on a GaAs substrate.
Layer, undoped GaAs layer, undoped InGaAs
Layers, an n-type AlGaAs layer and an n-type GaAs layer are provided, and an undoped AlGaAs layer and an undoped Ga
The As layer is a buffer layer.

The buffer layer is formed as a high-purity, high-resistance layer.

The wafer having the above-described epitaxial layer structure is manufactured by metal organic chemical vapor deposition (MOVPE), and the outline thereof is as follows.

A substrate in a reaction furnace is heated to a predetermined substrate temperature in a predetermined atmosphere, and then a group III source gas and a group V source gas are supplied into the reaction furnace, and the generated III-V compound semiconductor is supplied to the substrate. Epitaxial growth is performed thereon to form an epitaxial layer, and a predetermined epitaxial layer is sequentially formed.

The above-mentioned group III raw materials include a group III element trialkylated product (TMG: trimethylgallium, TMA:
Trimethyl aluminum, TMI: trimethyl indium) is, as the group V raw material of the group V element hydride (AsH _3: arsine, etc.) are used.

[0013] The substrate temperature is 600 ° C to 80 ° C.
A temperature range of 0 ° C. has been used. Substrate temperature is 600 ℃
The reason for this is to prevent the quality of the epitaxial layer to be formed from being deteriorated by the influence of impurities (carbon or oxygen). The reason why the substrate temperature is set to 800 ° C. or lower is to prevent the desired reaction from being hindered.

From the above compound semiconductor wafer, FET or H
To manufacture an EMT, a source electrode (S), a drain electrode (D), and a gate electrode (G) are formed on a wafer having a corresponding epitaxial layer configuration.

In recent years, in order to improve the performance of the device, the process has been miniaturized, for example, by making the epitaxial layer thinner and making the gate electrode length 0.2 μm. Such thinning of the epitaxial layer and miniaturization of the process have created new technical problems as described below.

When an epitaxial layer is formed by metal organic chemical vapor deposition (MOVPE), unevenness occurs when the epitaxial layer is formed. In particular, when the GaAs layer and the InGaAs layer are formed, the unevenness has a height difference of about 30 angstroms. . This is step bunching, and the problem is to suppress its occurrence.

The thinning of the HEMT is remarkable.
The thickness of the channel is about 100 to 200 angstroms. Therefore, the occurrence of step bunching having a height difference of 30 angstroms significantly deteriorates characteristics. In addition, the yield of device manufacturing by the fine process is reduced.

In the metal organic chemical vapor deposition method (MOVPE method), a substrate which is inclined at an angle of about 2 degrees from the (100) crystallographic main plane is used. The above GaAs layer and InG
The occurrence of the step bunching with a height difference of about 30 angstroms in the aAs layer is caused by the influence of the tilt angle. On the other hand, this tilt angle is necessary to reduce the defect density, and eliminating the oblique angle increases the defect density. Therefore, simply using a substrate having no tilt angle involves another technical problem.

[0019]

As described above, compound semiconductor epitaxial wafers by metal organic chemical vapor deposition (MOVPE) and FETs and H
With the progress of thinning and miniaturization of devices such as EMT, it has become a major problem to suppress harmful step bunching in epitaxial wafers, to improve device characteristics, and to improve device yield.

A group III-V compound semiconductor epitaxial wafer, particularly an epitaxial wafer including a GaAs epitaxial layer and an InGaAs epitaxial layer, suppresses step bunching due to the importance of devices such as FETs and HEMTs manufactured therefrom. There is an urgent need to improve device characteristics and device yield.

The present invention solves the above problems. Further, the present invention is also applicable to a case where a GaAs epitaxial layer, an InGaAs epitaxial layer, or the like is formed by a metal organic chemical vapor deposition (MOVPE) method using a tilted substrate.
Angstroms or more) and high yield, high performance FETs and HEs from the resulting epitaxial wafers.
Provided is a technique for manufacturing an element such as an MT.

[0022]

An important technical factor in the occurrence of step bunching in an epitaxial layer is the substrate temperature.

The formation of a compound semiconductor epitaxial layer by metal organic chemical vapor deposition (MOVPE) is carried out at a substrate temperature of 60.
This is performed at 0 ° C. or higher, in order to prevent carbon or oxygen from being mixed in from the surface of the AlGaAs epitaxial layer or the like, thereby preventing the quality of the entire wafer from being deteriorated as a result.

Examining the substrate temperature of step bunching, step bunching grows well at a substrate temperature of 600 ° C. or higher. Experiments were performed under various conditions, and the surface of the epitaxial layer was observed by AFM. As a result, harmful step bunching occurred at a substrate temperature of 570 ° C. or higher, and the substrate temperature was reduced to 5 ° C.
It has been found that the occurrence of harmful step bunching can be suppressed by performing epitaxial growth at 65 ° C. or lower.

However, if the epitaxial growth is simply performed at a substrate temperature of 565 ° C. or lower, the quality degradation and the reduction of the epitaxial growth rate due to the incorporation of carbon and oxygen into the epitaxial layer are reduced as compared with the case where the substrate temperature is set to 600 ° C. or higher by the conventional technique. Will result in reduced productivity.

As a result of conducting various experimental researches to solve the above-mentioned problems, it has been found that the use of TEG (triethylgallium) as a Ga source and a substrate temperature of 505 ° C. to 565 ° C. And the mixing of carbon and oxygen is suppressed to 1/10 or less of the case where TMG (trimethylgallium) is used by the conventional technology,
We were able to solve productivity problems.

FIG. 4 is a diagram showing the temperature dependence of the growth rate.

Hereinafter, the dependence of the epitaxial growth rate on the substrate temperature when various III-V compound semiconductor epitaxial layers are formed using various Group III raw materials will be described with reference to FIG. The group V raw material is AsH
₃ (arsine).

As shown in FIG. 4, the boundary (inflection point) between the diffusion limited region (flat line portion) and the reaction limited region (inclined line portion) is formed of GaAs by TMG (trimethylgallium).
In the layer formation, 565 ° C., in the AlAs layer formation by TMA (trimethylaluminum), 505 ° C., in the InAs layer formation by TMI (trimethylindium), 46 in
5 ° C., 425 ° C. for GaAs layer formation by TEG (triethyl gallium).

Industrial epitaxial growth must be performed in a diffusion-controlled region. However, when the substrate temperature range used in the present invention is 505 ° C. to 565 ° C., TE is used as a Ga raw material.
By using G (triethylgallium), GaAs
It is shown that any of the s layer, the AlAs layer, and the InAs layer can be epitaxially grown in the diffusion controlled region.

Further, according to the present invention, GaAs which is important in the manufacture of a III-V compound semiconductor epitaxial wafer is important.
Layers, AlGaAs layers, or InGaAs layers can be epitaxially grown at the same substrate temperature, but FIG. 4 illustrates the technical background.

[0032]

BEST MODE FOR CARRYING OUT THE INVENTION A compound semiconductor epitaxial wafer according to the present invention is a compound semiconductor epitaxial wafer including Ga compound semiconductor epitaxial, wherein the substrate temperature is in the range of 505 ° C. to 565 ° C., and TEG (triethylgallium) is used as a Ga raw material. 3 is a compound semiconductor epitaxial wafer manufactured by metal organic chemical vapor deposition (MOVPE).

A group of compound semiconductor epitaxial wafers according to the present invention embodied as group III-V compound semiconductor epitaxial wafers is GaAs.
A compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of an s layer, an AlGaAs layer, and an InGaAs layer, wherein the substrate temperature is in the range of 505 ° C. to 565 ° C.
It is a compound semiconductor epitaxial wafer manufactured by metal organic chemical vapor deposition (MOVPE) using G (triethylgallium).

The basic method of manufacturing a compound semiconductor epitaxial wafer according to the present invention is a method of manufacturing a compound semiconductor epitaxial wafer including a Ga compound semiconductor epitaxial layer using metal organic chemical vapor deposition (MOVPE). , Substrate temperature from 505 ° C to 565
This is a method for manufacturing a compound semiconductor epitaxial wafer using TEG (triethylgallium) as a Ga raw material in the range of ° C.

A group of compound semiconductor epitaxial wafers according to the present invention, which are embodied as III-V compound semiconductor epitaxial wafers, use a metal organic chemical vapor deposition (MOVPE) to form a GaAs layer, an AlGa
In a method for manufacturing a compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of an As layer and an InGaAs layer, a substrate temperature is set in a range of 505 ° C to 565 ° C, and TE is used as a Ga raw material.
This is a method for manufacturing a compound semiconductor epitaxial wafer using G (triethylgallium).

Further, the present invention relates to a method for manufacturing a compound semiconductor epitaxial wafer according to the present invention, wherein
The group includes a method of manufacturing a compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of a GaAs layer, an AlGaAs layer, and an InGaAs layer using metal organic chemical vapor deposition (MOVPE). In the above, a substrate having an inclination angle inclined from the (100) plane is used as the substrate, and the substrate temperature is set to 505 ° C. to 565.
This is a method for manufacturing a compound semiconductor epitaxial wafer using TEG (triethylgallium) as a Ga raw material in the range of ° C.

In the present invention, it is desirable to keep the substrate temperature constant during the growth of two or more compound semiconductor epitaxial layers. This is because, if the substrate temperature is changed for each layer, an interval until the substrate temperature becomes constant is required and the growth time becomes longer, and impurities are introduced into the epitaxial layer during the interval.

According to the present invention, the occurrence of harmful step bunching is prevented, so
Since a high-quality compound semiconductor epitaxial wafer for T is obtained, the yield of FET or HEMT devices is greatly improved, and the characteristics of the devices (such as electron transfer speed and noise figure) are improved. Further, in the low temperature range, it is possible to form an epitaxial layer in which carbon and oxygen are less mixed, so that a buffer layer having a high resistance is formed, a leak current of the buffer layer can be reduced, and element characteristics are improved. Also on the surface, effects such as obviating the necessity of forcibly adding oxygen to the epitaxial layer are provided.

[0039]

Embodiments of the present invention will be described below.

An epitaxial wafer for HEMT as described below was manufactured by metal organic chemical vapor deposition (MOVPE) using a substrate temperature of 530 ° C. and TEG (triethyl gallium) as a Ga raw material.

The above-mentioned epitaxial wafer for HEMT is:
Undoped, AlGaAs epitaxial layer, undoped GaAs epitaxial layer, undoped InGaAs epitaxial layer, n-type AlGa
An As epitaxial layer and an n-type GaAs epitaxial layer are formed. This wafer structure is shown in FIG.

The manufacturing conditions of the epitaxial wafer for HEMT of this embodiment are set at the above substrate temperature (530).
° C) and Ga raw material (TEG), except that TMA was used as an Al raw material and TM as an In raw material.
I used AsH ₃ as an As material.

Using the obtained epitaxial wafer,
A HEMT having a gate length of 0.2 μm was manufactured. In this case, no occurrence of step bunching was observed. A
As a result of the FM observation, only irregularities of 5 angstroms (one atomic layer thickness) were observed. Further, it was confirmed that both the undoped AlGaAs layer and the undoped GaAs layer of the buffer layer had a high resistance, and that little carbon was taken in.

The N _F (noise figure) of the obtained HEMT is 0.43 dB on average, and the best one is 0.37 dB.
B. The HEMT yield was 9% for the entire wafer.
5%, and the yield is remarkably improved as compared with the prior art.

[0045]

Comparative Example An example of the prior art for comparison with the example of the present invention will be described below.

An undoped AlGaAs epitaxial layer is formed on a GaAs substrate by metal organic chemical vapor deposition (MOVPE), and an undoped GaAs epitaxial layer is formed on the undoped AlGaAs layer (the above undoped AlGaAs layer and undoped GaAs). Layer as a buffer layer), and then undoped InGa
After forming an As epitaxial layer, an n-type AlGaAs epitaxial layer, and an n-type GaAs epitaxial layer, FIG.
AlGaAs and InGaAs HE as shown in FIG.
An epitaxial wafer for MT was manufactured.

The substrate temperature was set at 600 ° C. As the organometallic compound, TMG (trimethylgallium) was used as a Ga raw material, TMA (trimethylaluminum) was used as an Al raw material, and TMI (trimethylindium) was used as an In raw material. In addition, AsH ₃ (arsine) was used as an As material.

Using the obtained epitaxial wafer,
A HEMT having a gate length of 0.2 μm was manufactured. In this case, as a result of measuring the height of the step bunching, about 30
Angstrom. The buffer layer has a killer concentration of 5E15c for the p-type undoped AlGaAs layer.
m ⁻³ , the undoped GaAs layer was p-type and 5E14 cm ⁻³ .

As a result of measurement of N _F (noise figure) as a characteristic of the obtained HEMT, an average value was 0.5 dB, and the best one was 0.45 dB. The yield of HEMT was 50% of the whole wafer, and 50% was defective.

[0050]

According to the present invention, a high-quality compound semiconductor epitaxial wafer can be obtained. By using such a compound semiconductor epitaxial wafer. Devices such as FETs and HEMTs with high yield and high quality can be obtained.

Further, according to the present invention, a compound semiconductor epitaxial wafer having a small amount of impurities can be obtained by performing epitaxial growth in a low-temperature region, so that the efficiency in wafer production is improved.

[Brief description of the drawings]

FIG. 1 is a schematic diagram of an epitaxial layer configuration of a general FET wafer.

FIG. 2 is a schematic diagram of an epitaxial layer configuration of a general HEMT wafer.

FIG. 3 is a schematic view of a result of a photograph observation of step bunching.

FIG. 4 is a diagram showing a temperature dependency of a growth rate.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Ken Meguro 5-1-1, Hidaka-cho, Hitachi City, Ibaraki Prefecture Hidaka Factory, Hitachi Cable, Ltd.

Claims (6)

[Claims] 1. A compound semiconductor epitaxial wafer including a Ga compound semiconductor epitaxial layer, wherein the substrate temperature is in the range of 505 ° C. to 565 ° C.
A compound semiconductor epitaxial wafer manufactured by metal organic chemical vapor deposition (MOVPE) using EG (triethyl gallium). 2. A GaAs layer, an AlGaAs layer, an InGa
A compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of As layers, wherein the substrate temperature is in a range of 505 ° C. to 565 ° C., and TEG (triethylgallium) is used as a Ga raw material. A compound semiconductor epitaxial wafer manufactured by vapor phase epitaxy (MOVPE). 3. The compound semiconductor epitaxial wafer according to claim 1, wherein each layer has no step bunching with a height difference of 30 angstroms or more. 4. A method of manufacturing a compound semiconductor epitaxial wafer including a Ga compound semiconductor epitaxial layer using metal organic chemical vapor deposition (MOVPE), wherein the substrate temperature is in a range of 505 ° C. to 565 ° C., and TEG is used as a Ga source. A method for producing a compound semiconductor epitaxial wafer using (triethylgallium). 5. A method for manufacturing a compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of a GaAs layer, an AlGaAs layer, and an InGaAs layer using metal organic chemical vapor deposition (MOVPE). , The substrate temperature is set in the range of 505 ° C. to 565 ° C., and TEG (triethyl gallium)
A method for producing a compound semiconductor epitaxial wafer using the method. 6. A method for manufacturing a compound semiconductor epitaxial wafer including two or more compound semiconductor epitaxial layers selected from the group consisting of a GaAs layer, an AlGaAs layer, and an InGaAs layer using metal organic chemical vapor deposition (MOVPE). In the above, a substrate having an inclination angle inclined from the (100) plane is used as the substrate, and the substrate temperature is set to 505 ° C. to 56 ° C.
A method for producing a compound semiconductor epitaxial wafer in the range of 5 ° C. and using TEG (triethylgallium) as a Ga raw material.