JPH11203346A - Parasitic transistor verifying device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a parasitic transistor verifying device capable of easily checking the saturation of a transistor and a latent parasitic transistor. SOLUTION: This device is provided with a circuit simulation executing part 1 for imputing the circuit diagram of a semiconductor circuit and calculating the terminal voltage and wiring voltage of a component including a transistor and resistance constituting a semiconductor circuit, a parasitic transistor detecting part 2 for detecting the saturation of a transistor and a latent parasitic transistor from a relation between the base terminal voltage and collector terminal voltage of the transistor calculated by the circuit simulation executing part 1, and a parasitic transistor outputting means 3 for emphatically displaying the saturation of the transistor and the parasitic transistor on the circuit diagram when they are detected by the parasitic transistor detecting part 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for verifying a parasitic transistor in a semiconductor circuit.

[0002]

2. Description of the Related Art In a layout design of a semiconductor, a pattern of an analog IC includes transistors, resistors, capacitors and other elements formed by an epitaxial layer (hereinafter referred to as an island) formed on a semiconductor substrate by a separation layer. . Usually, the separation layer is connected to the substrate, and the GND (0
v). Due to the relationship between the potential in the island and the potential of the isolation layer, a parasitic transistor not shown in the circuit diagram occurs.

FIG. 8 shows a sectional structure of a simple NPN transistor. An NPN transistor has an N layer as an island and includes an N layer (collector), a P layer (base), and an N layer (emitter) in a P layer, and is surrounded by a P layer isolation layer to form a transistor. .

In the figure, 31 is a collector terminal, 32 is a base terminal, 33 is an emitter terminal, 36 is a separation layer, 37
Is a parasitic PNP transistor, and 38 is a parasitic NPN transistor.

FIG. 9 shows a sectional structure of a simple PNP transistor. Like the PNP transistor, the island is divided into an N layer and a P layer. However, the P layer in the island is an emitter and a collector, and the N layer is a base.

In the figure, 31 is a collector terminal, 32 is a base terminal, 33 is an emitter terminal, 36 is a separation layer, 37
Is a parasitic PNP transistor, and 38 is a parasitic NPN transistor. In the circuit diagram, the NPN transistor is represented by a symbol shown in FIG. 6 and the PNP transistor is represented by a symbol shown in FIG.

In the case of an NPN transistor, the potential of the normal terminal is in the order of collector (31) voltage> base (32) voltage> emitter (33) voltage. For normal operation, the voltage between the base and the emitter is 0. .7v (hereinafter, referred to as
For generality, the operating condition is referred to as a voltage, represented by a symbol B, and a numerical value of B> 0). When the base voltage is higher than the collector voltage (collector voltage + A <base voltage,
A> 0, a symbol that requires generality)
This is called "saturation", and no transistor characteristics for normal operation can be obtained.

In the case of a PNP transistor, the potential of the terminal is usually in the order of emitter (33) voltage> base (32) voltage> collector (31) voltage. Is about 0.7v (about Bv). When the base voltage is lower than the collector voltage (collector voltage−A> base voltage, A> 0), “saturation” occurs.

In the cross section of the NPN transistor shown in FIG. 8, the island potential and the collector potential are the same because the same N layer is connected. When the base voltage is higher than the collector voltage, a current flows from the base to the collector due to the PN connection, and a current leaks to the separation layer (0v). In particular, when the base voltage is higher than the collector voltage by Bv or more, the PNP transistor has a base-emitter relationship and operates as the parasitic PNP transistor 37.

In the cross-sectional view of the PNP transistor shown in FIG. 9, since the N layer having the same island potential and base potential is connected, they have the same potential. When the collector potential is lower than the base potential, a current flows from the collector to the base due to the PN junction, and a current leaks to the separation (0 V). In particular, when the base potential is higher than the collector potential by Bv or more, there is a relation between the base and the emitter of the PNP transistor, and the transistor operates as the parasitic PNP transistor 37. Further, when the island potentials of the NPN transistor and the PNP transistor are lower than 0 V (particularly, when the island potential is equal to or lower than -Bv), the parasitic NPN transistor 38 having the isolation layer as the base terminal is formed.

[0011]

Conventionally, in order to estimate the operation of a semiconductor circuit, in a circuit diagram in which elements such as transistors, resistors and capacitors and wirings are inputted, the elements are represented by a linear model or a non-linear model, and a voltage value is obtained. The operation is verified by performing a circuit simulation that obtains by a computer.

Various circuit simulators based on SPICE have been developed, including "SPICE" developed by UC Berkeley. However, a reduction in saturation cannot be verified by circuit simulation performed using model parameters extracted assuming normal operation of the transistor. Therefore, for a saturated transistor,
A circuit simulation needs to be performed using a saturation model. In addition, since the parasitic transistor is not input in the circuit diagram, the operation of the parasitic transistor cannot be verified by the conventional circuit simulation.

The designer of the IC looks at the layout pattern and empirically determines a place where a parasitic transistor is likely to occur, and for example, widens the isolation width at that place, thereby increasing the distance between the elements. Spreading out prevented current leakage. Therefore, omission of visual check,
Unskilled designers with no experience have problems such as overlooking parasitic transistors.

[0014]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and can perform verification of saturation of a transistor in a design circuit, verification of a parasitic transistor, and a saturation model. It is an object of the present invention to estimate a circuit operation more accurately than in the conventional circuit simulation by applying a parasitic transistor model.

The parasitic transistor verifying device according to the first aspect of the present invention determines the saturation and the parasitic transistor from the result of executing the circuit simulation, and has the following elements. (A) A circuit simulation execution unit that inputs a circuit diagram of a semiconductor circuit and calculates terminal voltages and wiring voltages of components including transistors and resistors constituting the semiconductor circuit. (B) A parasitic transistor detecting section for detecting transistor saturation and potential parasitic transistors from the execution result of the circuit simulation executing section. (C) output means for highlighting on the circuit diagram when saturation of the transistor and the parasitic transistor are detected by the parasitic transistor detection unit.

In the parasitic transistor verifying device according to the second aspect of the present invention, a parasitic transistor detecting section for detecting saturation of the transistor and a potential parasitic transistor from the base terminal voltage and the collector terminal voltage of the transistor calculated by the circuit simulation executing section. It has.

In the parasitic transistor verification device according to the third aspect of the present invention, the saturation of the transistor detected by the parasitic transistor detection unit, and the saturation model and the parasitic transistor model are applied to the parasitic transistor, thereby accurately estimating the circuit operation. Therefore, the circuit simulation is executed again.

In the parasitic transistor verifying device according to the fourth aspect, the parasitic transistor detecting section detects the parasitic transistor from the collector terminal voltage of the NPN transistor and the base terminal voltage of the PNP transistor.

In the parasitic transistor verifying device according to the fifth invention, the parasitic transistor detecting section searches for a terminal voltage of the resistor and an island potential of the resistor, and searches for a terminal having an island potential lower than the terminal voltage of the resistor. In the output means, the target resistance is highlighted, and when the island potential is lower than the terminal voltage of the resistance by a certain value or more, a parasitic transistor model is added.

In the parasitic transistor verification device according to the first and second aspects of the present invention, the circuit designer can recognize the saturation of the transistor and the location of the parasitic transistor by the output means. Prior art document [Japanese Unexamined Patent Publication No. 5-29012
No. 0], the saturation of the transistor is determined only from the magnitude relationship between the collector voltage and the base voltage.
According to the present invention, base voltage> collector voltage cannot be generally regarded as saturated from process conditions such as diffusion concentration, so that the base voltage> collector voltage + A (A is a numerical value of A ≧ 0) is used for the saturation determination.
Thus, generality can be provided, and a transistor determined to be saturated can be highlighted on a circuit diagram. Further, although the prior art document [Japanese Patent Laid-Open No. 5-290120] cannot determine the parasitic transistor, the present invention is characterized in that the parasitic transistor can be determined.

In the parasitic transistor verification device according to the third aspect of the invention, the circuit operation can be more accurately estimated by replacing the transistor saturation with a saturation model or a parasitic transistor model by the output means. Prior art document [Japanese Unexamined Patent Publication No. 7-498
In Japanese Patent Application Laid-Open No. 97-206], the present invention is characterized in that a simulation model is exchanged in accordance with detection of a parasitic transistor, and simulation is executed again, in order to obtain a model parameter of a parasitic transistor.

The parasitic transistor verification device according to the fourth invention can verify a parasitic transistor.

The parasitic transistor verification device according to the fifth aspect of the present invention can verify a parasitic transistor with respect to a resistance element from the relationship between an island potential and a resistance terminal voltage. In the prior art document (Japanese Patent Application Laid-Open No. 6-348781), similarly, a defective portion is detected from the relationship between the island potential and the resistance terminal voltage. However, this invention is characterized in that it is highlighted on the drawing. The purpose is to add a parasitic transistor and execute the simulation again.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1 Embodiment 1 of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 1 denotes a circuit simulation execution unit that calculates the terminal voltage of each component such as a transistor, a resistor, and a capacitor that constitute a semiconductor circuit, and the voltage of a wiring. A parasitic transistor detector 3 searches for a collector voltage, determines transistor saturation, and determines a parasitic PNP transistor. Reference numeral 3 denotes a circuit diagram displayed and output, and a result determined by the parasitic transistor detector 2 is displayed in the circuit diagram. Output means for highlighting above.

Next, an example of the operation of the parasitic transistor verification device according to the present invention will be described with reference to FIG. In FIG. 2, reference numeral 1 denotes a circuit simulation execution unit that calculates the terminal voltage of each component such as a transistor, a resistor, and a capacitor that constitute a semiconductor circuit, and the voltage of a wiring. A parasitic transistor detector 3 searches for a collector voltage, determines transistor saturation, and determines a parasitic PNP transistor. Reference numeral 3 denotes a circuit diagram displayed and output, and a result determined by the parasitic transistor detector 2 is displayed in the circuit diagram. Output means for highlighting above. 4 is N
PN transistor, base voltage of PNP transistor,
A voltage search unit for searching for a collector voltage, a determination unit for determining whether the transistor is an NPN transistor, and a voltage comparison unit for comparing a base voltage and a collector voltage with each other. Reference numeral 8 denotes ending means for judging whether or not to end the transistor search, 9 denotes saturation judgment means, and 10 denotes parasitic PNP transistor judgment means.

The voltage search unit 4 obtains the base voltage and the collector voltage of the NPN transistor and the PNP transistor from the voltages of the respective elements obtained by the circuit simulation execution unit 1 for all the transistors in the circuit diagram. It is determined whether the transistor is an NPN transistor or a PNP transistor. If the transistor is an NPN transistor, the voltage comparator 6 determines whether the transistor is a saturation or parasitic PNP transistor if the transistor is a PNP transistor.

In the voltage comparison section 6, based on the cross-sectional structure of the NPN transistor shown in FIG. 8, when the base potential is higher than the collector potential (when the voltage is equal to or higher than the collector potential + A, A is a numerical value of A ≧ 0). , Is determined to be saturated, and
When the voltage is higher than the collector potential by the operating condition voltage Bv or more (B
If .gtoreq.A.gtoreq.0), it is determined that a parasitic PNP transistor is generated between the base-collector-separation layer.

The saturation and parasitic PN of such a transistor
For the NPN transistor that can be determined to be a P transistor, the output means 3 performs color coding on the circuit diagram and highlighting such as highlighting. In the voltage comparison unit 7, based on the cross-sectional structure of the PNP transistor shown in FIG. 8, when the base potential is lower than the collector potential (collector voltage −Av
In the case of the following voltages, A is determined to be saturated when A is a numerical value of A ≧ 0. When the voltage is lower than the collector potential by the operating condition voltage Bv or more (B ≧ A ≧ 0), the parasitic PNP transistor is connected to the collector. -It is determined to occur between the base and the separation layer.

As described above, conventionally, the saturation of the transistor and the parasitic transistor have been visually checked.
According to the highlighted display, the check can be easily performed, and the omission of the check is extremely reduced. In addition to highlighting on the circuit drawing, a means of recording the detection results in a file is provided, and the circuit designer confirms the contents of the file by specifying the saturation, presence / absence of parasitic transistors, and the location. May be.

Embodiment 2 FIG. In the first embodiment, for the purpose of detecting the saturation of the transistor and the parasitic transistor, the circuit designer can be alerted by highlighting it on the circuit diagram. However, as shown in FIG. In 3, the circuit operation is re-executed using a saturation model for a transistor determined to be saturated and a transistor model including a parasitic PNP for a transistor determined to be a parasitic PNP, thereby more accurately estimating the circuit operation. Circuit malfunction due to saturation and parasitic PNP can be detected by circuit simulation.

In FIG. 3, reference numeral 1 denotes a terminal voltage of each component such as a transistor, a resistor, and a capacitor constituting a semiconductor circuit;
Circuit simulation execution unit that calculates the voltage of the wiring, 2
Is a parasitic transistor detection unit that searches for the base voltage and the collector voltage of the transistor from the result of the circuit simulation, and determines the saturation of the transistor and the parasitic PNP transistor. And output means for highlighting the result determined by the parasitic transistor detector 2 on the circuit diagram. Reference numeral 4 denotes an NPN transistor, a voltage search unit that searches for a base voltage and a collector voltage of the PNP transistor, 5 denotes a determination unit that determines whether the transistor is an NPN transistor, 6, 7
Is a voltage comparing unit for comparing the base voltage and the collector voltage. Reference numeral 8 denotes ending means for judging whether or not to end the transistor search, 9 denotes saturation judging means, and 10 denotes parasitic PNP transistor judging means. 11 is a model replacement means, 12 is a saturation model replacement means, 13 is a parasitic PNP transistor model replacement means, and 14 is a circuit simulation re-execution means.

FIG. 12 shows a model of a normal NPN transistor, FIG. 13 shows an example of a saturation model of the NPN transistor,
FIG. 14 shows an example of a model of an NPN transistor including a parasitic PNP.

Embodiment 3 In the first embodiment, the parasitic transistor detector detects the parasitic PNP transistor.
In the case of (collector potential ≦ 0), current flows from the P layer separation as shown in the cross-sectional view of FIG.
If v (numerical value of B> 0) or less, a parasitic NPN transistor is generated. Similarly, as shown in FIG. 8, when the base potential is 0 or less (base potential ≦ 0), −Bv (B> 0) If
A parasitic NPN transistor occurs.

As shown in FIG. 4, in the parasitic transistor detection unit, NP
The collector potential is searched for the N transistor, and the base potential is searched for the PNP transistor. If the potential is 0 or less and −Bv (the numerical value of B> 0) or less, it is determined that the transistor is a parasitic NPN transistor.

In FIG. 4, reference numeral 1 denotes a terminal voltage of each component such as a transistor, a resistor, and a capacitor constituting a semiconductor circuit;
Circuit simulation execution unit that calculates the voltage of the wiring, 2
a is a parasitic transistor detector that searches for the base voltage and the collector voltage of the transistor from the result of the execution of the circuit simulation, and determines the saturation of the transistor and the parasitic PNP transistor;
This is a voltage search unit for searching for a base voltage and a collector voltage of the P transistor. Reference numeral 15 denotes a discriminating unit, 16 denotes a highlighted display output unit, 17 denotes a discriminating unit, 18 denotes a highlighted display (parasitic NPN transistor) output unit, 19 denotes a discriminating unit, 20 denotes a highlighted display output unit, 21 denotes a discriminating unit, and 22 denotes a highlighted display. (Parasitic NPN transistor) output means 23 is an ending means for judging whether or not to end the transistor search;

For the transistor determined to be a parasitic NPN transistor as in the second embodiment, a circuit simulation may be performed by replacing the transistor with a model including the parasitic NPN transistor. FIG. 15 shows an example of a model of an NPN transistor including a parasitic NPN.

Embodiment 4 FIG. In each of the above embodiments, the parasitic transistor is determined by focusing on the base potential and the collector potential of the transistor in the parasitic transistor detection unit 2, but may be focused on the resistance element.

FIG. 10 is a simple sectional view of the resistor, and FIG. 11 is a simple plan view of the resistor. In the figure, 34 is a resistor terminal, 35 is an island potential terminal, 36 is an isolation layer, and 37 is a parasitic PN.
It is a P transistor.

As shown in FIGS. 10 and 11, when the resistance element is formed of the P layer, the potential of the island of the N layer is normally supplied with the power supply voltage, and there is no leakage of current due to the PN junction. If the power supply voltage cannot be supplied to the island potential due to design, or if the voltage input to the resistor is higher than the island potential, leakage of current from the P layer to the N layer occurs due to the PN junction.

According to the flow shown in FIG. 5, in the parasitic transistor determination unit, based on the result of the circuit simulation,
By comparing the terminal voltage of the resistor and the island potential, if the island potential is lower than the terminal voltage of the resistor, the highlighted display is performed, and further, if -Bv (B> 0), a parasitic PNP transistor is generated. May be detected.

In FIG. 5, reference numeral 1 denotes a terminal voltage of each component such as a transistor, a resistor, and a capacitor constituting a semiconductor circuit;
Circuit simulation execution unit that calculates the voltage of the wiring, 2
Reference numeral b denotes a parasitic transistor detection unit that determines the saturation of the transistor and the parasitic PNP transistor from the result of the execution of the circuit simulation. 24 is a voltage search unit for searching the terminal voltage of the resistor, 25 is an island potential search unit for searching for the island potential of the resistor, 26 and 27 are discriminating units, 3b is a display output unit, and 28 is a highlighted display (parasitic PNP transistor). Means 29, highlighting output means, and 30 means ending means for determining whether or not the resistance search has ended.

Embodiment 5 FIG. In each of the above embodiments, the parasitic transistor is detected separately from the transistor and the resistor. However, as shown in FIG. 16, the parasitic transistors may be determined by combining all of the first to fourth embodiments. May be combined to determine an appropriate transistor. This makes it possible to detect a transistor and a parasitic transistor with respect to a resistor by one flow.

[0043]

According to the first aspect of the present invention, when the parasitic transistor detection section detects the saturation of the transistor and the parasitic transistor, the output means highlights the position on the circuit diagram to determine the saturation of the transistor and the location of the parasitic transistor. Thus, the circuit designer can be accurately recognized.

According to the second aspect of the present invention, when the saturation of the transistor and the parasitic transistor are detected from the relation between the base terminal voltage and the collector terminal voltage of the transistor calculated by the circuit simulation execution unit by the parasitic transistor detection unit, The output means highlighted on the drawing enables the circuit designer to accurately recognize the saturation of the transistor and the location of the parasitic transistor.

According to the third aspect of the present invention, when the parasitic transistor detection section detects the saturation of the transistor and the parasitic transistor, the output means for highlighting the saturation and the location of the parasitic transistor on the circuit diagram is used to determine the location of the transistor and the parasitic transistor. By replacing the transistor saturation and the parasitic transistor with a saturation model and a parasitic transistor model in a circuit that can be accurately recognized by a designer, the circuit operation can be more accurately estimated.

According to the fourth aspect, the case where the transistor saturation and the parasitic transistor are detected by the parasitic transistor detection unit from the relationship between the collector terminal voltage of the NPN transistor and the base terminal voltage of the PNP transistor calculated by the circuit simulation execution unit. In addition, the output means for highlighting on the circuit diagram enables the saturation of the transistor,
The location of the parasitic transistor can be accurately recognized by a circuit designer.

According to the fifth aspect, the parasitic transistor can be verified from the relation between the island potential and the resistance terminal voltage in relation to the resistance element.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a parasitic transistor verification device according to a first embodiment of the present invention.

FIG. 2 is a processing flowchart of the parasitic transistor verification device according to the first embodiment of the present invention;

FIG. 3 is a processing flowchart of the parasitic transistor verification device according to the second embodiment of the present invention;

FIG. 4 is a processing flowchart of the parasitic transistor verification device according to the third embodiment of the present invention;

FIG. 5 is a processing flowchart of the parasitic transistor verification device according to the fourth embodiment of the present invention;

FIG. 6 is a diagram showing an example of a circuit diagram symbol of an NPN transistor.

FIG. 7 is a diagram showing an example of a circuit diagram symbol of a PNP transistor.

FIG. 8 is a diagram illustrating an example of a cross-sectional view of an NPN transistor.

FIG. 9 is an example of a cross-sectional view of a PNP transistor.

FIG. 10 is an example of a sectional view of a resistor.

FIG. 11 is an example of a plan view of a resistor.

FIG. 12 is a diagram illustrating an example of a model of a normal NPN transistor.

FIG. 13 is a diagram illustrating an example of a saturation model of an NPN transistor.

FIG. 14 is a diagram illustrating an example of a model of an NPN transistor including a parasitic PNP.

FIG. 15 is a diagram illustrating an example of a model of an NPN transistor including a parasitic NPN.

FIG. 16 is a processing flowchart of the parasitic transistor verification device according to the fifth embodiment of the present invention;

[Explanation of symbols]

31 collector terminal, 32 base terminal, 33 emitter terminal, 34 resistor terminal, 36 separation layer, 35 island potential terminal, 37 parasitic PNP transistor, 38 parasitic NP
N transistor.

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 21/82 T

Claims (5)

[Claims] 1. A parasitic transistor verification device having the following elements. (A) A circuit simulation execution unit that inputs a circuit diagram of a semiconductor circuit and calculates terminal voltages and wiring voltages of components including transistors and resistors constituting the semiconductor circuit. (B) A parasitic transistor detecting section for detecting transistor saturation and potential parasitic transistors from the execution result of the circuit simulation executing section. (C) output means for highlighting on the circuit diagram when saturation of the transistor and the parasitic transistor are detected by the parasitic transistor detection unit. 2. A circuit according to claim 1, further comprising a parasitic transistor detecting section for detecting a saturation of the transistor and a potential parasitic transistor based on a relation between a base terminal voltage and a collector terminal voltage of the transistor calculated by the circuit simulation executing section. Item 2. The parasitic transistor verification device according to Item 1. 3. A circuit simulation for accurately estimating a circuit operation by applying a saturation model and a parasitic transistor model to the saturation of the transistor detected by the parasitic transistor detection unit and the parasitic transistor. The parasitic transistor verification device according to claim 1, wherein 4. The parasitic transistor according to claim 1, wherein the parasitic transistor detecting unit detects the parasitic transistor from a collector terminal voltage of the NPN transistor and a base terminal voltage of the PNP transistor. Verification device. 5. The parasitic transistor detecting section searches for a terminal voltage of the resistor and an island potential of the resistor, searches for a terminal having an island potential lower than the terminal voltage of the resistor, and highlights the target resistance in the output means. 5. The parasitic transistor verification device according to claim 1, wherein a parasitic transistor model is added when the island potential is lower than a terminal voltage of the resistor by a certain value or more.