JPH06324102A - Support device of layout pattern verification - Google Patents

Abstract

PURPOSE:To allow the automatic judgment and error correction of a wiring short-circuit position by providing layout extracting module for extracting layout information from layout pattern data; wiring layer node analyzing module; wiring short-circuit analyzing module; and wiring short-circuit error output module. CONSTITUTION:A layout pattern data 1 in which the structure of a semiconductor integrated circuit and the information of signal line names are defined is inputted to expand the hierarchical structure of the data 1, and layout information 5 is extracted by a layout information extracting module 7. Further, node information every wiring layer is extracted by a wiring layer node analyzing module 7. According to the node information and the text information capable of recognizing a signal line name, the short-circuit error of a wire is judged by a wiring short-circuit analyzing module 8 when the text information of a different signal line name is present in the wiring layer having the electrically same potential is present, and the error wiring is extracted. The wiring short- circuit information is displayed on an error list 10 by a wiring short-circuit error output module 9.

Description

Detailed Description of the Invention

[0001]

This invention relates to a semiconductor integrated circuit (I
The present invention relates to a layout pattern verification support device for verifying wiring shorts of layout pattern data in C).

[0002]

2. Description of the Related Art FIG. 12 is a block diagram showing a conventional layout pattern verification support device of this type. In the figure, 1 is layout pattern data defining information for recognizing the structure of a semiconductor integrated circuit and a signal line name, 2 is a hierarchical expansion module for expanding the hierarchical structure of the layout pattern data, and 3 is a hierarchical expanded layout. A layout information extraction rule for extracting layout information such as device and circuit connection information from the pattern data, and 4 for extracting layout information 5 including the device and circuit connection information from the layout pattern data hierarchically expanded using this rule. And a layout information extraction module for storing.

Reference numeral 6 is a wiring short circuit analysis rule for analyzing whether or not the wiring is short-circuited based on the text information added to the wiring from the extracted and stored layout information 5, and 8 is a wiring short circuit analysis rule 6. This is a wiring short circuit analysis module that analyzes the wiring short circuit of the layout information 5 by using it and extracts the short circuited wiring as an error when the wiring is short circuited. Reference numeral 9 denotes a wiring short circuit error output module which outputs and stores an error list of wiring short circuits extracted by the wiring short circuit analysis module 8 and an error result for displaying graphics. Further, 10 is an error list output from the wiring short error output module 9, 11 is an error result output from the wiring short error output module 9 similar to the error list 10, and 12 is a graphic display of the error result 11. It is a display module.

Next, a conventional layout pattern verification support device will be described with reference to the flowchart of FIG. The layout pattern data 1 defining the information that can recognize the structure of the semiconductor integrated circuit and the signal line name is input,
The hierarchical structure extraction module 4 expands the hierarchical structure of the layout pattern data 1 by the hierarchical expansion module 2 (step S1), and then uses the layout information extraction rule 3 for extracting layout information such as device and circuit connection information, and the layout information extraction module 4 The layout information 5 including the device, circuit connection information, etc. is extracted according to (step S2). Next, using the wiring short circuit analysis rule 6 from the layout information 5, the wiring short circuit analysis module 8 analyzes and verifies the wiring short circuit based on the text information added on the wiring, and extracts the wiring which becomes the wiring short circuit as an error. (Step S3). FIG. 14 is an example of this wiring short-circuit error. In the case where text information of different signal line names exists in wiring layers having the same electric potential, based on the text information (VDD, VSS) added to each wiring layer. It is determined that a wiring short-circuit error has occurred, and all the wiring that has an error is output as an error. Further, for the wiring short circuit error information extracted by the wiring short circuit analysis module 8, the wiring short circuit error output module 9 outputs the error list 11 and the error result 11 for displaying on the graphics (step S4), and the display module 1
2, the error result is displayed on the graphic.

[0005]

Since the conventional layout pattern verification support device is configured as described above,
When a short circuit occurs in the wiring, all the shorted wirings will be output as an error.As a result, it is not possible to determine which part is shorted, and as a result, visually trace the shorted wiring and find the error location. There was a problem that it took time to correct the error. Further, particularly when the power supply and the GNG (ground) wiring are short-circuited, the error wiring becomes huge and it is very difficult to visually detect the error location.

The present invention has been made in order to solve the above-mentioned problems, and it is possible to automatically determine where a wiring short circuit occurs, and at the same time, to perform a layout pattern verification capable of immediately correcting an error. The purpose is to obtain a support device.

[0007]

A layout pattern verification support apparatus according to claim 1 of the present invention is a layout for extracting layout information from layout pattern data defining information capable of recognizing the structure and signal line name of a semiconductor integrated circuit. An information extraction module, a wiring layer node analysis module that extracts node information for each wiring layer for performing a wiring short circuit analysis from layout information, and a wiring that analyzes a wiring short circuit from the node information of each wiring layer and results in a short circuit error And a wiring short circuit error output module that outputs an error result of the extracted wiring short circuit.

According to a second aspect of the layout pattern verification support apparatus, the wiring short circuit analysis module of the first aspect further includes a back bias analysis module for analyzing node information of a contact portion connected to a back bias wiring layer of a transistor. It is provided.

According to a third aspect of the layout pattern verification support apparatus, the wiring short circuit analysis module of the first aspect includes an area dividing module for dividing a power supply and a GND wiring into wiring permission / prohibition areas and analyzing a short circuit portion of the wiring. It is provided.

[0010]

In the layout pattern verification support apparatus according to the first aspect of the present invention, the wiring layer node analysis module extracts the node information for each wiring layer for the wiring short circuit analysis from the layout information.

Further, in the pattern verification support device according to the second aspect, the back bias analysis module provided in the wiring short circuit analysis module analyzes the node information of the contact portion connected to the back bias wiring layer of the transistor.

Further, in the pattern verification support apparatus according to the third aspect, the area dividing module provided in the wiring short circuit analyzing module divides the power supply and the GND wiring into the wiring permission / prohibition areas and analyzes the wiring short circuit location.

[0013]

【Example】

Example 1. Embodiment 1 of the present invention will be described below with reference to the drawings. First Embodiment FIG. 1 is a block diagram showing a first embodiment of a layout pattern verification support device according to the present invention. In the figure, 1 is layout pattern data defining information for recognizing the structure and signal line name of a semiconductor integrated circuit (IC), 2
Is a hierarchical expansion module for expanding the hierarchical structure of the layout pattern data 1, 3 is a layout information extraction rule for extracting devices, circuit connection information, etc. from the hierarchically expanded layout pattern data, 4 is a layout information rule 3 A layout information extraction module for extracting layout information including devices, circuit connection information, etc. from the hierarchically developed layout pattern data, 5 is layout information extracted and stored by the layout information extraction module 4, and 6 is used for wiring short circuit analysis. A wiring short circuit analysis rule, 7 is a wiring layer node analysis module for extracting the node information of each wiring layer from the upper wiring layer of the device process structure based on the layout information 5, and 8 is the extracted node information for each wiring layer. Use to analyze and verify wiring shorts Wiring short-circuit analysis module for extracting a wiring error, 9 is a wiring short-circuit error output module for outputting a list output of the extracted wiring short-circuit errors and storing an error result, 10 is an error list to be output, 11 is an error for displaying graphics The result.

Next, the operation will be described. Figure 2 here
3 is a flowchart of a process course in the layout pattern verification support device. As in the conventional case,
First, the layout pattern data 1 defining the structure of the semiconductor integrated circuit and the information for recognizing the signal line name is input, and the hierarchical expansion module 2 expands the hierarchical structure of the layout pattern data 1 (step S11). The layout information extraction module 4 extracts layout information 5 including devices, circuit connection information, etc. by using the layout information extraction rule 3 for extracting layout information such as circuit connection information (step S).
12).

Then, according to the layout information 5, the wiring layer node analysis module 7 uses the wiring short circuit analysis rule 6 for extracting the node information from the upper wiring layer of the process structure of the device and performing the wiring short circuit analysis. The node information for each layer is extracted (step S13).
3 and 4 are examples of node information extraction of each wiring layer extracted by this wiring layer node analysis module, in which wiring node information is extracted from the upper wiring layer (in the order of METAL, POLY, NDIFF) of the device. The table information indicating the connection relation of each wiring layer as shown in FIG. 4 is extracted.

Next, by the node information for each wiring layer extracted by the wiring layer node analysis module and the text information capable of recognizing the signal line name, the wiring short circuit analysis module 8 makes the signal lines electrically different in the wiring layer of the same potential. If the text information of the name exists, it is determined that the wiring is short-circuited and the wiring having the error is extracted (step S1).
4). FIG. 5 shows an example of the wiring short circuit error extracted by this wiring short circuit analysis module, which shows Example 1 in (A) and Example 2 in (B). Text information is added so that error locations can be limited. Than the polygon
An error location is searched, and polygons having the same text information are judged to be the same polygon and an error is output. Further, it is possible to output an error only for the wiring layer "NDIFF" by using the fact that there is node information for each wiring layer.

Further, with respect to the wiring short circuit error information extracted by the wiring short circuit analysis module 8, the wiring short circuit error output module 9 outputs an error list 10 and an error result 11 for displaying on the graphics (step S15). The display module 12 displays the error result on the graphics and corrects the error portion (step S16).

Example 2. Next, a second embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing a second embodiment of the layout pattern verification support apparatus according to the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and the description thereof will be omitted. In the figure, 13 indicates from the verification result of the wiring short circuit analysis module 8 that the back bias is used when there is a power supply or GND (ground) wiring that is short-circuited due to the back bias wiring layer (well, substrate) of the transistor. This is a back bias analysis module that analyzes node information of a contact portion connected to a wiring layer (well, substrate) and extracts a wiring short error.

Next, the operation will be described. Figure 7
9 is a flowchart of a process course in the layout pattern verification support device according to the second embodiment. Similar to the case of the first embodiment, first, the layout pattern data 1 defining the structure of the semiconductor integrated circuit and the information that can recognize the signal line name is input, and the hierarchical structure of the layout pattern data 1 is expanded by the hierarchy expansion module 2. (Step S2
1) Next, using the layout information extraction rule 3 for extracting layout information such as device and circuit connection information, the layout information extraction module 4 performs device,
Layout information 5 including circuit connection information and the like is extracted (step S22).

Next, the wiring layer node analysis module 7 uses the wiring short-circuit analysis rule 6 for extracting node information from the upper wiring layer of the device process structure based on the layout information 5 and performing the wiring short-circuit analysis, and the wiring layer node analysis module 7 The node information for each layer is extracted (step S23), and by the extracted node information for each wiring layer and the text information for recognizing the signal line name, the wiring short circuit analysis module 8 makes the wiring layers electrically at the same potential. If text information of different signal line names exists, it is determined that a wiring short-circuit error occurs, and the wiring having the error is extracted (step S2).
4).

Next, using the wiring short-circuit error information extracted by the wiring short-circuit analysis module 8, the power supply and GND (ground) are short-circuited in the back bias wiring layer (well, substrate) of the transistor by the back bias analysis module 13. If so, the node information of the contact portion connected to the back bias wiring layer (well, substrate) is analyzed, and the error portion of the wiring short circuit is extracted (step S25). FIG. 8 is an example of the wiring short circuit error extracted by the back bias analysis module 13, and outputs a portion where the node information of the contact portion to the back bias wiring layer is not normal in terms of device. . For example, although the back bias wiring layer on the Pch transistor side must be a power supply, an error is output when there is a GND (ground) node contact.

Further, the back bias analysis module 13
The wiring short circuit error information extracted by the wiring short circuit error output module 9 outputs the error list 10
The error result 11 for displaying on the graphics is output (step S26), and the error result 11 is displayed on the graphic by the display module 12 to correct the error (step S27).

Example 3. Next, a third embodiment of the present invention will be described with reference to the drawings. FIG. 9 is a block diagram showing a third embodiment of the layout pattern verification support apparatus according to the present invention. The same parts as those in FIGS. 1 and 2 are designated by the same reference numerals and the description thereof will be omitted. In the figure, reference numeral 14 indicates a power supply which is short-circuited in a wiring layer other than the back bias wiring layer (well, substrate) of the transistor based on the verification result of the wiring short circuit analysis module 8 and a power supply when a GND (ground) wiring exists. , GND (ground) wiring is divided into Pch transistor and Nch transistor regions,
It is an area division module that analyzes short-circuited portions of wiring.

Next, the operation will be described. Figure 10
9 is a flowchart of a process course in the layout pattern verification support device according to the third embodiment. As in the case of the first and second embodiments, first, the layout pattern data 1 defining the structure of the semiconductor integrated circuit and the information capable of recognizing the signal line name is input, and the hierarchical expansion module 2 causes the hierarchical structure of the layout pattern data 1 to be input. (Step S31), and then using the layout information extraction rule 3 for extracting layout information such as device and circuit connection information, the layout information extraction module 4 causes the layout information 5 including the device and circuit connection information. Is extracted (step S32).

Then, the wiring layer node analysis module 7 uses the wiring short circuit analysis rule 6 for extracting the node information from the upper wiring layer of the device process structure from the layout information 5 and performing the wiring short circuit analysis. The node information for each layer is extracted (step S33), and the extracted node information for each wiring layer and the text information for recognizing the signal line name enable the wiring short circuit analysis module 8 to electrically change the wiring layer to the same potential. If the text information of the signal line name exists, it is determined that the wiring is short-circuited and the wiring having the error is extracted (step S34).

Next, by using the wiring short-circuit error information extracted by the wiring short-circuit analysis module 8, the power supply and GND (ground) wiring are short-circuited except for the back bias wiring layer (well, substrate) by the area division analysis module 14. In this case, the power supply / GND (ground) wiring is divided into wiring permission / prohibition areas such as the Pch transistor and Nch transistor areas, and the wiring short circuit portion is analyzed and extracted (step S35). FIG. 11 shows an example of the wiring short circuit error extracted by the area division analysis module 14. The Pch transistor area is the power supply wiring permission area and the Nch transistor area is GND.
The (ground) wiring permission area is set, and traces are made from the power supply and GND pads to analyze the short-circuited portion of the wiring, and the short-circuited portion of the wiring is output as an error.

Further, the wiring short-circuit error information extracted by the area division analysis module 14 is output by the wiring short-circuit error output module 9 as an error list 10 and an error result 11 for displaying on graphics (step S36). The display module 12 displays the error result 11 on the graphic and corrects the error (step S37).

In the above embodiment, the power source, G
The module for analyzing the ND (ground) wiring short circuit has been described by dividing it into the back bias analysis module section and the area division analysis module section, but the same applies to these modules as one module. Also, for short circuit analysis other than power supply and GND (ground) wiring, if the wiring permission, the prohibited area, and the permitted wiring layer can be specified, the same verification can be performed.

[0029]

As described above, according to claim 1 of the present invention, a layout information extraction module for extracting layout information from layout pattern data defining information capable of recognizing the structure and signal line name of a semiconductor integrated circuit, Wiring layer node analysis module that extracts node information for each wiring layer to perform wiring short analysis from layout information, and wiring short circuit that analyzes wiring short circuit from node information of each wiring layer and extracts wiring that causes short circuit error It consists of an analysis module and a wiring short error output module that outputs the extracted wiring short error result.
According to claim 2, the wiring short circuit analysis module of claim 1 is provided with a back bias analysis module for analyzing node information of a contact portion connected to the back bias wiring layer of the transistor, and according to claim 3, The wiring short circuit analysis module is equipped with an area dividing module that analyzes power shortages and GND wirings into wiring permission and prohibition areas and analyzes wiring short points, so it can be automatically determined where wiring shorts occur. At the same time, there is an effect that a layout pattern verification support device capable of immediately correcting an error can be obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a layout pattern verification support device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation flow of the layout pattern verification support device of the first embodiment.

FIG. 3 is an extraction diagram for explaining an operation of a wiring layer node analysis module in the layout pattern verification support device according to the first exemplary embodiment.

FIG. 4 is an extraction diagram for explaining the operation of the wiring layer node analysis module in the layout pattern verification support device of the first exemplary embodiment.

FIG. 5 is an error output diagram for explaining the operation of the wiring analysis module in the layout pattern verification support device according to the first exemplary embodiment.

FIG. 6 is a block diagram showing a configuration of a layout pattern verification support device according to a second embodiment of the present invention.

FIG. 7 is a flowchart showing an operation flow of the layout pattern verification support device of the second embodiment.

FIG. 8 is an error output diagram for explaining the operation of the back bias analysis module of the layout pattern verification support device according to the second exemplary embodiment.

FIG. 9 is a block diagram showing a configuration of a layout pattern verification support device according to a third embodiment of the present invention.

FIG. 10 is a flowchart illustrating an operation flow of the layout pattern verification support device according to the third exemplary embodiment.

FIG. 11 is an error output diagram for explaining the operation of the area division analysis module of the layout pattern verification support device according to the third exemplary embodiment.

FIG. 12 is a block diagram showing a configuration of a conventional layout pattern verification support device.

FIG. 13 is a flowchart showing an operation flow of a conventional layout pattern verification support device.

FIG. 14 is an error output diagram for explaining the operation of the wiring short circuit analysis module of the conventional layout pattern verification support device.

[Explanation of symbols]

 1 Layout pattern data 2 Hierarchical expansion module 3 Layout information extraction rule 4 Layout information extraction module 5 Layout information 6 Wiring short analysis rule 7 Wiring layer node analysis module 8 Wiring short analysis module 9 Wiring short error output module 10 Error list 11 Error result 12 Display module 13 Back bias analysis module 14 Area division analysis module

Claims (3)

[Claims] 1. A layout information extraction module for extracting layout information from layout pattern data defining information capable of recognizing a structure of a semiconductor integrated circuit and a signal line name, and each wiring for performing wiring short circuit analysis from the layout information. A wiring layer node analysis module that extracts node information for each layer, a wiring short circuit analysis module that analyzes a short circuit of the wiring from the node information of each wiring layer and extracts a wiring that causes a short circuit error, and the extracted wiring A layout pattern verification support device comprising: a wiring short circuit error output module that outputs a short circuit error result. 2. The layout pattern verification according to claim 1, wherein the wiring short circuit analysis module includes a back bias analysis module that analyzes node information of a contact portion connected to a back bias wiring layer of a transistor. Support device. 3. A power supply, G for the wiring short circuit analysis module.
The layout pattern verification support device according to claim 1, further comprising an area dividing module that divides the ND wiring into wiring permission / prohibition areas and analyzes a short circuit portion of the wiring.