JPH11203133A - Information processing device - Google Patents

Abstract

(57) [Problem] To provide an information processing apparatus capable of repeatedly performing an operation on a data set of a plurality of words with a small amount of hardware. An information processing apparatus fetches an instruction from a first storage unit connected to an instruction fetch unit, and reads and writes data from and to a second storage unit connected to an instruction execution unit. When executing an instruction having an immediate value of a plurality of words, the plurality of immediate values are fetched from the first storage unit 3 using a normal instruction fetch mechanism, and the other data is stored in an address specified by the instruction. For the second storage unit 4
By reading data from the data and executing the operation specified by the instruction on each set of data, it is possible to efficiently execute a repeated operation on a plurality of data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an information processing apparatus for performing a high-speed operation by accessing a plurality of data in a plurality of memories in parallel and performing an operation using the data as an operand.

[0002]

2. Description of the Related Art Data on a plurality of memories is accessed using a plurality of buses (an internal data bus and an internal program bus) connected to the respective memories, and the accessed data is mainly used as a product-sum operation. An information processing apparatus for performing such operations is disclosed in JP-A-7-49854.

In this information processing apparatus, a second memory connected to a program bus operates as an instruction memory or a data memory, and by executing a MOVE instruction,
It has a MACD instruction for loading a block of instructions from an external memory to a second memory, transferring operands to a multiplier using both an internal data bus and an internal program bus, and performing a multiply-accumulate operation between them. Therefore, the product-sum operation can be executed at high speed. Furthermore, by using a combination of a single instruction repeat instruction and a MACD instruction,
Since the product-sum operation and the reading of the operand can be performed in a superimposed manner, the feature is that the filtering process and the like can be performed at high speed.

[0004]

However, in the above-described information processing apparatus, when accessing data to the program bus, the program address used for fetching an instruction held in the program counter is saved on the stack, and the data to the program bus is saved. The data address used for the access is loaded into the program counter to perform the data access. After the data access is completed, an operation of returning a program address used for instruction fetch from the stack is required. Therefore, it is necessary to have a stack of the program counter in the information processing apparatus, which causes a problem that not only increases the hardware scale but also complicates the control.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an information processing apparatus capable of repeatedly performing an operation on a data set of a plurality of words with a small amount of hardware. .

[0006]

According to a first aspect of the present invention, there is provided an information processing apparatus for reading an instruction from a first storage unit using a first bus by an instruction fetch unit. , The instruction execution unit, depending on the instruction to be executed,
An information processing apparatus configured to read data from a second storage unit using a second bus and to perform an arithmetic operation using an arithmetic unit in an instruction execution unit, wherein the information processing device does not include an operation code indicating an instruction type. Having an immediate value of at least a plurality of words, reading the immediate value of the plurality of words using the first bus, reading the data of the plurality of words specified by the operation code using the second bus, It is configured to execute an instruction for performing an operation between an immediate value and data of a plurality of words read using the second bus. As a result, the data of two words can be used as input data for the repetitive operation.

According to a second aspect of the present invention, there is provided an information processing apparatus comprising:
An instruction fetch unit according to claim 1, further comprising: an instruction prefetch means for reading a subsequent instruction from a first bus in advance; and an instruction buffer for holding an instruction read in advance by the instruction prefetch means; In addition to the operation code indicating the type, when executing an instruction that has an immediate value of at least a plurality of words and performs an operation between the immediate value of the plurality of words and the data specified by the operation code, the immediate value of the multi-word The data is read out by the prefetch means, held in the instruction buffer, and supplied from the instruction buffer to the instruction execution unit to perform the operation. Thereby, immediate values of a plurality of words can be efficiently supplied to the instruction execution unit.

According to a third aspect of the present invention, there is provided an information processing apparatus comprising:
3. The information processing apparatus according to claim 2, wherein a bus width of the first bus for reading the instruction is larger than a bus width of the second bus for accessing the data, and the access time of the first bus is equal to or smaller than the first bus. 2 is longer than the access time of the second bus. As a result, immediate values of a plurality of words can be efficiently supplied to the instruction execution unit from the storage unit having a long access time.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a first embodiment of the present invention will be described with reference to FIGS. FIG.
1 shows a block diagram of a main part constituting an information processing apparatus according to the first embodiment of the present invention. In FIG. 1, 1 is an instruction fetch unit, 2 is an instruction execution unit, 3 and 4 are storage units, and 5 and 6 are buses.

The instruction fetch unit 1 is connected to a bus 5, and the storage unit 3 is connected to the bus 5. The instruction fetch unit 1 outputs an instruction address to the bus 5 in response to a request from the instruction execution unit 2, and starts instruction fetch. The storage unit 3 outputs an instruction at a position corresponding to the instruction address on the bus 5 to the bus 5. The instruction fetch unit 1 receives an instruction output to the bus 5 and supplies the instruction to the instruction execution unit 2.

The instruction execution unit 2 interprets the instruction supplied from the instruction fetch unit 1 and performs an operation indicated by the instruction. The operation is, for example, reading data from a register in the instruction execution unit 2, performing addition by an adder in the instruction execution unit 2, and writing the addition result to the register. Further, the instruction execution unit 2 includes a storage unit 4 outside the instruction execution unit 2.
Executes an instruction to exchange data with In response to this instruction, the instruction execution unit 2 reads, for example, a register, outputs the read data to the bus 6 as a data address to start data access, and the storage unit 4 connected via the bus 6 Is output to the bus 6 at the position indicated by the data address output to the
Operates to write the data output to the bus 6 to the register in the instruction execution unit 2 or reads the register, outputs the read data to the bus 6 as a data address, and starts data access. The register is read, and the read data is output to the bus 6 as write data. The storage unit 4 operates to write the write data output to the bus 6 at a position indicated by the data address output to the bus 6. .

FIG. 2 shows a first embodiment of the present invention, which has an immediate value of a plurality of words, reads out the immediate values of the plurality of words using a bus 5, and reads data of a plurality of words specified by an operation code on a bus. 6 shows the configuration of an instruction for performing an operation between an immediate value of a plurality of words and data of a plurality of words read using the bus 6. In FIG. 2, reference numeral 200 denotes an instruction, 201 denotes an operation code, 202 denotes an operand, and 210 to 213 denote immediate values.

The operation code 201 includes the number of immediate values 210 to 213 of a plurality of words included in the instruction 200, that is, the number of repetition operations, the data word length, the type of operation, and the operand 202.
Indicates information such as the type of The operand 202 indicates data used for an operation on the immediate values 210 to 213 of a plurality of words. For example, it is a register number that holds a start address of data of a plurality of words stored in the storage unit 4 accessed via the bus 6 or a plurality of register numbers in the instruction execution unit 2. Here, for the sake of explanation, the storage unit 4
Is specified as an operand 202, and the number of immediate values is four.

FIG. 3 shows, in the first embodiment of the present invention, the four word immediate values 210 to 213 shown in FIG. 2, and the four word immediate values 210 to 213 are read out using the bus 5, The 4-word data specified by the operand 202 is read using the bus 6 and the 4-word immediate values 210 to 21 are read.
6 is a timing chart showing the execution of an instruction 200 for performing an operation between data 3 and data of four words read using the bus 6.

In FIG. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, 300 is a cycle indicating a clock cycle number, 301 is a PC indicating the address of an instruction being executed by the instruction execution unit 2, 302, 303 and 304 are arithmetic unit inputs,
305 is an arithmetic unit output. For the sake of explanation, the arithmetic unit is a product-sum arithmetic unit, and the arithmetic unit input 304 is the output of the product-sum register.

Hereinafter, the first embodiment of the present invention will be described with reference to FIGS.
The information processing apparatus according to the embodiment has an immediate value 210 of four words.
213, the four word immediate values 210 to 213 are read out using the bus 5, the four word data specified by the operand 202 are read out using the bus 6, and the four word immediate values 210 to 213 are obtained. An operation of executing an instruction 200 for performing an operation with four-word data read using the bus 6 will be described.

In FIG. 3, in cycle 1, the instruction A is accessed on the bus 5 and the head word of the instruction A is read from the storage unit 3. Here, the instruction A has four immediate values, reads four data from the address specified by the operand 202, and stores the four data and the immediate two
This is an instruction for multiplying 10 to 213 pairs and performing accumulation on the value of the product-sum register.

In cycle 2, the first word of instruction A is supplied to instruction execution unit 2 by instruction fetch unit 1, and the second word of instruction A is fetched.
Here, for the sake of explanation, the first word of the instruction A includes the opcode 201 and the operand 20 of the instruction 200 shown in FIG.
2 is included. Here, the instruction execution unit 2 decodes the operation code of the instruction A, and the instruction A
The instruction fetch unit 1 recognizes that an instruction to execute a multiply-accumulate operation is performed on the four words of data starting from the address P indicated by and the four immediate values 210 to 213 of the instruction A. Of the data word whose address is P is requested from the bus 6. The instruction fetch unit 1 requests the bus 5 to read the first immediate value 210 of the address A + 1.

In cycle 3, the instruction execution unit 2
In cycle 2, the first immediate value 210 of the instruction A read to the bus 5 is input to the arithmetic unit input 302, and the data word of the address P read to the bus 6 is input to the arithmetic unit input 303.
, And the value Q of the sum-of-products register is input to the calculator input 304 to execute the sum-of-products operation. The product-sum operation result is output to the calculator output 305 in the next cycle. Product-sum operation result R
Is output to the value Q + 1 of the product-sum register in cycle 4.

In cycles 4 and 5, the same operation as in cycle 3 is performed except that the address of the read request for each of buses 5 and 6 is incremented.

In cycle 6, the instruction execution unit 2
Upon detecting the end of the instruction A, the access request for the instruction B following the instruction A is made to the instruction fetch unit 1. In cycle 5, the fourth immediate value 213 of the instruction A read to the bus 5 is input to the arithmetic unit input 302, the data word of the address P + 3 read to the bus 6 is input to the arithmetic unit input 303, and the product The value of the sum register is input to the arithmetic unit input 304 to execute a product-sum operation.

The result of the operation of the instruction A is output as R + 3 to the operation unit output 305 in cycle 7, and the value is written to the product-sum register, thereby completing the execution of the instruction A.

As described above, the information processing apparatus according to the first embodiment of the present invention has four word immediate values 210 to 213.
And read the immediate values 210 to 213 of the four words using the bus 5 and
Read word data using bus 6, read 4 word immediate data 2
The instruction 200 for performing the product-sum operation using the product-sum register and the 4-word data read using the buses 6 and 10 to 213 can be executed at high speed.

It should be understood that the above-described instruction 200
Is executed, the four words of the immediate values 210 to 213 are read out because the four words of the immediate values 210 to 213 form a part of the instruction 200. Therefore, the instruction fetch for counting up the subsequent instruction fetch address in the instruction fetch unit 1 is performed. Since the counter can be used as it is, a stack for saving the instruction fetch counter is not required.

Hereinafter, an information processing apparatus according to a second embodiment of the present invention will be described with reference to FIGS. 2, 4 and 5.

FIG. 4 is a block diagram showing a main part of an information processing apparatus according to a second embodiment of the present invention. 4, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, reference numeral 10 denotes an instruction prefetch unit;
1 is an instruction buffer, and 12 is an instruction buffer output.

FIG. 5 shows, in the second embodiment of the present invention, the four-word immediate values 210 to 213 shown in FIG. The 4-word data specified by the operand 202 is read using the bus 6 and the 4-word immediate values 210 to 21 are read.
6 is a timing chart showing the execution of an instruction 200 for performing an operation between data 3 and data of four words read using the bus 6. 5, the same components as those in FIGS. 3 and 4 are denoted by the same reference numerals. In FIG. 5, the instruction buffer 11
A and the instruction buffer 11B indicate the contents of the instruction buffers of two words inside the instruction buffer 11, respectively.

Hereinafter, the information processing apparatus according to the second embodiment of the present invention has the four-word immediate values 210 to 213 shown in FIG. Read, read four word data specified by operand 202 using bus 6, read four word immediate value 210
An operation of executing an instruction A in the form of an instruction 200 for performing an operation between .about.213 and four-word data read using the bus 6 will be described.

In the information processing apparatus according to the second embodiment, the storage unit 3 connected to the bus 5 performs one access in two bus cycles. However, the configuration is such that two words can be read by one access.
That is, the bus width of the bus 5 is larger than the bus width of the bus 6, and the access time of the bus 5 is longer than the bus access time of the bus 6.

This is a configuration that is often used when it is difficult to improve the access speed compared to the data RAM, especially when the built-in ROM is used as an instruction memory in a general-purpose processor for device control or the like. This is not a limitation of the present invention. The two words read using the bus 5 are stored in the instruction buffer 11 and selectively output from the instruction buffer output 12 to the instruction execution unit 2 as needed.

In FIG. 5, in cycles 1 and 2, the instruction S and its subsequent instruction S + 1 are read out using the bus 5.

In cycle 3, the instruction S and the succeeding instruction S + 1 are sent to the instruction buffer 11A and the instruction buffer 11B.
And the instruction S is output to the instruction execution unit 2 and the instruction S
Decryption and execution are started. Also, the reading of the first two words of the instruction A, which is the instruction following the instruction S + 1, is started.

In cycle 4, the instruction S + 1 is output to the instruction execution unit 2, and the decoding and execution of the instruction S + 1 are started. Further, the read access to the bus 5 started in cycle 3 is completed.

In cycle 5, the instruction A and the subsequent immediate value A + 1 are stored in the instruction buffer 11A and the instruction buffer 11B.
And the instruction A is output to the instruction execution unit 2 and the instruction A
Is started. The instruction execution unit requests the bus 6 to read the address P indicated by the operand of the instruction A. Further, the instruction fetch unit 1 starts reading words following A + 2, which is the subsequent part of the instruction A.

In cycle 6, the instruction execution unit 2
The first immediate value of the instruction buffer output 12 is input to the arithmetic unit input 302.
, And the data word of the address P read to the bus 6 is input to the arithmetic unit input 303, the value Q of the product-sum register is input to the arithmetic unit input 304, and the product-sum operation is executed. The product-sum operation result is output to the calculator output 305 in the next cycle. The product-sum operation result R is output as the value Q + 1 of the product-sum register in cycle 7.

Thereafter, the execution of instruction A can be performed in the same manner. Here, since the instruction A is an instruction having an immediate value of 4 words, the first immediate value fetched in the instruction buffer 11 by the instruction fetch performed on the bus 5 from the cycle 3 is used for the operation in the cycle 6 can do.

However, if the instruction is not an immediate value but an instruction configured to fetch a plurality of words specified by the second operand from the bus 5, at least after decoding the operation code of the instruction A, that is, from cycle 5, Since the access to the address specified by the second operand is started, the operation can be performed with all the operands in cycle 7, and a useless cycle is required. Further, when the instruction A + 1 fetched earlier is discarded, an extra instruction fetch access is required, so that the power consumption is increased.

Therefore, if the instruction A is an instruction having an immediate value of four words, the effects of high speed and low power consumption can be obtained.

As described above, even if the information processing apparatus according to the second embodiment of the present invention is configured to read two instructions from a two-cycle access storage unit, it is possible to read four instructions.
It has word immediates 210 to 213, and its four words immediate 210
To 213 are read out using the bus 5, the 4-word data specified by the operation code is read out using the bus 6, the 4-word immediate values 210 to 213 and the 4-word data read out using the bus 6 are read out. An instruction for performing a product-sum operation using the product-sum register can be executed at high speed.

In the embodiment of the present invention, the storage units 3 and 4 are described as being a RAM or a ROM. However, a configuration using a cache memory may be used, and the present invention is not limited to this. Not something.

[0041]

As described above, according to the present invention, it is possible to perform an iterative operation on a plurality of data at high speed by using an instruction having a plurality of immediate words.

Even in the case of reading instructions in advance, the original instruction fetch unit can be used for reading an immediate word, so that it can be realized with a small amount of hardware and low power consumption. is there.

[Brief description of the drawings]

FIG. 1 is a block diagram of main parts constituting an information processing apparatus according to a first embodiment of the present invention;

FIG. 2 is a configuration diagram of an instruction having an immediate value of a plurality of words according to the first and second embodiments of the present invention;

FIG. 3 is a timing chart showing the operation of the information processing apparatus according to the embodiment;

FIG. 4 is a block diagram of a main part constituting an information processing apparatus according to a second embodiment of the present invention;

FIG. 5 is a timing chart showing the operation of the information processing apparatus according to the embodiment;

[Explanation of symbols]

 Reference Signs List 1 instruction fetch unit 2 instruction execution unit 3, 4 storage unit 5, 6 bus 10 instruction prefetch means 11 instruction buffer 12 instruction buffer output 300 cycle 301 program counter (PC) 302, 303, 304 computing unit input 305 computing unit output

Claims (3)

[Claims] An instruction fetch unit, a first bus connected to the instruction fetch unit, a first storage unit connected to the first bus, and an instruction fetched by the instruction fetch unit. An instruction execution unit to be executed; a second bus connected to the instruction execution unit; and a second storage unit connected to the second bus, wherein the instruction execution unit includes the first bus. A plurality of words from the second bus, read a plurality of words of data from the second bus, execute an instruction to perform an operation using each of the plurality of words of data, and read a plurality of words from the first bus. Is an immediate value forming a part of the instruction. 2. An instruction fetch unit comprising: an instruction prefetch means for reading a subsequent instruction from the first bus in advance; and an instruction buffer for holding the previously read instruction. Read the data of a plurality of words constituting a part of the own instruction, and execute the instruction of performing an operation using the data of the plurality of words. 2. The information processing apparatus according to claim 1, wherein the data is read to an instruction buffer, and the instruction execution unit is supplied with the data of the plurality of words from the instruction buffer. 3. A bus width of the first bus is larger than a bus width of the second bus, and an access time of the first bus is longer than a bus access time of the second bus. The information processing apparatus according to claim 2, wherein