CN118057308A - Instruction processing optimization method and related device - Google Patents

Abstract

The embodiment of the application discloses an instruction processing optimization method and a related device, wherein the method comprises the following steps: determining a target load instruction, wherein the first register comprises a source address offset bit, a destination address offset bit and an iterative computation bit; if the target load instruction is a first load instruction, determining a first source address according to the source address offset and the first load instruction, and determining a first destination address according to an initial destination address and the destination address offset in the second register; acquiring first target data according to a first source address; writing the first target data back to a storage space corresponding to the first target address; and determining a final destination address according to the iterative calculation bit and the initial destination address, and determining that the iterative execution of the first load instruction is finished if the final destination address is the same as the first destination address. Therefore, batch data processing can be realized through parallel processing of the instructions, and the data throughput rate is improved.

Description

Instruction processing optimization method and related device

Technical Field

The present application relates to the technical field of data processing, and in particular to an instruction processing optimization method and related devices.

Background technique

In today's era of big data, batch processing of data is one of the inevitable scenarios in the process of electronic devices implementing data processing through instructions, and the storage and access of data will directly affect the efficiency of data processing. In the existing methods, in order to improve the efficiency of data processing, it is often adopted that: for different scenarios, additional functional unit components are added to the chip of the electronic device, such as adding acceleration units such as graph processing unit (GPU) and neural processing unit (NPU). While adopting this method, while achieving improved processing efficiency, it will lead to an increase in chip resources, and ultimately lead to an expansion of the chip area.

In order to solve the above problems, an instruction processing optimization method is urgently needed.

Summary of the invention

The embodiments of the present application provide an instruction processing optimization method and related devices, which are beneficial to improving the speed of instruction processing of electronic devices, thereby improving the efficiency of batch data loading.

In a first aspect, an embodiment of the present application provides an instruction processing optimization method, which is applied to an electronic device, wherein the electronic device includes a first register and a second register, the first register is used to determine a source address for obtaining target data, the second register is used to determine a destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit;

The method comprises:

Determine a target load instruction, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit;

If the target load instruction is the first load instruction, determining a first source address according to the source address offset and the first load instruction, and determining a first destination address according to the initial destination address in the second register and the destination address offset;

According to the first source address, obtaining first target data;

According to the first destination address, writing the first target data back to the storage space corresponding to the first destination address;

Determine a final destination address according to the iterative calculation bit and the initial destination address, and determine whether the first load instruction has been executed according to the final destination address;

If the final destination address is the same as the first destination address, it is determined that the first load instruction has been executed.

In a second aspect, an embodiment of the present application provides an instruction processing optimization device, which is applied to an electronic device, wherein the electronic device includes a first register and a second register, wherein the first register is used to determine a source address for obtaining target data, and the second register is used to determine a destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit;

The device comprises: a determination unit, an acquisition unit, an execution unit and a judgment unit; wherein,

The determining unit is configured to determine a target load instruction, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit; and is configured to, if the target load instruction is the first load instruction, determine a first source address according to the source address offset bit and the first load instruction, and determine a first destination address according to an initial destination address in the second register and the destination address offset bit;

The acquiring unit is configured to acquire first target data according to the first source address;

The execution unit is configured to write the first target data back to a storage space corresponding to the first destination address according to the first destination address;

The judgment unit is used to determine the final destination address according to the iterative calculation bit and the initial destination address, and to judge whether the first load instruction has been executed according to the final destination address; and to determine that the first load instruction has been executed if the final destination address is the same as the first destination address.

In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor, a memory, a communication interface, and one or more programs, wherein the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps of any method of the first aspect of the embodiment of the present application.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps described in any method of the first aspect of the embodiment of the present application.

In a fifth aspect, an embodiment of the present application provides a computer program device, wherein the computer program device includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps described in any method of the first aspect of the embodiment of the present application. The computer program device can be a software installation package.

It can be seen that in the embodiment of the present application, by determining the target load instruction, the first register includes a source address offset bit, a destination address offset bit and an iterative calculation bit; if the target load instruction is the first load instruction, the first source address is determined according to the source address offset bit and the first load instruction, and the first destination address is determined according to the initial destination address and the destination address offset bit in the second register; the first target data is obtained according to the first source address; the first target data is written back to the storage space corresponding to the first destination address; the final destination address is determined according to the iterative calculation bit and the initial destination address, and if the final destination address is the same as the first destination address, it is determined that the first load instruction is iteratively executed. In this way, batch data processing can be achieved through parallel processing of instructions, providing a higher data throughput rate for electronic devices to perform data processing.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

FIG1A is a schematic diagram of an instruction processing process of a conventional architecture provided in an embodiment of the present application;

FIG1B is a schematic diagram of an instruction execution process of an existing architecture provided by an embodiment of the present application;

FIG1C is a schematic diagram of an architecture of an electronic device implementing instruction optimization processing provided by an embodiment of the present application;

FIG2 is a flow chart of an instruction processing optimization method provided in an embodiment of the present application;

FIG3 is a schematic diagram of a first register structure provided in an embodiment of the present application;

FIG4A is a schematic diagram of the overall flow of an instruction processing optimization method provided by an embodiment of the present application;

FIG4B is a schematic diagram of a process of an electronic device processing a first load instruction provided by an embodiment of the present application;

FIG5 is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

FIG6 is a block diagram of the functional units of an instruction processing optimization device provided in an embodiment of the present application.

Detailed ways

In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, device or equipment that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, devices or equipment.

Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

The electronic device may be a portable electronic device that also includes other functions such as a personal digital assistant and/or a music player function, such as a mobile phone, a tablet computer, a wearable electronic device with a wireless communication function (such as a smart watch, smart glasses), a vehicle-mounted device, etc. Exemplary embodiments of portable electronic devices include but are not limited to portable electronic devices equipped with an IOS system, an Android system, a Microsoft system, or other operating systems. The above-mentioned portable electronic device may also be other portable electronic devices, such as a laptop computer (Laptop), etc. It should also be understood that in some other embodiments, the above-mentioned electronic device may not be a portable electronic device, but a desktop computer.

Especially general-purpose processors have serious defects in big data processing. Therefore, many new architectures are currently proposed, including using GPU/NPU and so on as acceleration units for big data processing.

In the application scenario where electronic devices perform batch data processing through instructions, the existing architecture is to add an accelerator to the original basic control architecture. This accelerator is composed of simple control and batch computing units, such as GPU and NPU. Among them, GPU is another mainstream accelerator independent of the central processing unit (CPU), which is specially used for image data acceleration processing. NPU is a neural network acceleration function for artificial intelligence that has become popular in recent years. These are all self-contained systems without exception, which are completely different from the CPU architecture. These systems have a common feature, that is, loading requires a large amount of data, and the data loading process is often implemented through loading load instructions. The data loading performance of traditional CPUs restricts the speed of data acceleration processing in many fields in current real-life scenarios.

Specifically, as shown in FIG. 1A, FIG. 1A is a schematic diagram of an instruction processing process of an existing architecture provided by the present application scheme. As shown in FIG. 1A, the processor specifically includes a program counter PC, an adder, an instruction cache unit, a register group, a plurality of multiplexers, and a logic arithmetic unit ALU. Among them, the function of the instruction cache unit is to store all 32-bit wide instructions read in, perform instruction fetching operations according to the instruction address in the program counter PC and analyze the instruction type, distinguish and identify each field of the fetched instruction by the instruction type, and finally pass the corresponding part to other modules for subsequent processing. Among them, the instructions specifically include but are not limited to: load instructions and store instructions, etc. The load instruction fetches the data in the memory into the general register, and the store instruction stores the data in the general register into the memory. Each time an instruction is taken out from the instruction cache unit, the program counter automatically increments according to the instruction length through the adder to generate the instruction address required for the next instruction.

Exemplarily, in register-type instructions, opcodes are composed of an opcode (OP) and an auxiliary opcode (OPX), and operands include two source operands (RS) and one target operand (RD); immediate-type instructions are composed of an opcode, a source operand, a target operand, and an immediate number (Const), and the number of bits of the immediate number varies.

For example, the register group includes several registers, each with a width of 32 bits, which are used to store temporary data required for ALU calculations. Unlike the data memory, the data stored in this part of the registers may be overwritten multiple times during the execution of the program, while the data in the data memory can generally only be modified and overwritten by the sw instruction. The register group reads data according to the address corresponding to the opcode and the RS and RT fields, and outputs the address of the RS and RT registers and the data therein, and stores the data in the register corresponding to the RS or RT field when the falling edge of the clock arrives.

Exemplarily, the sign extension bit is used to extend the immediate number and to fill the number of instruction bits. The multiplexer is used to select the corresponding storage space according to the data obtained by instruction decoding, so as to obtain the data pointed to by the instruction. The logical arithmetic component selects the corresponding operand according to the data after instruction decoding, performs calculation according to the operation code and outputs the result and the zero flag bit. It is used to perform logical operations according to the instruction, wherein the logical operations include but are not limited to: addition, subtraction, multiplication and division, etc.

Specifically, please refer to FIG. 1A for a description of the data processing process:

Exemplarily, as shown in FIG. 1A , data processing specifically includes five processes: instruction fetch IF, instruction translation ID, execution EXE, memory access MEM, and write back WB.

Specifically, the instruction fetch operation is to read an instruction from the instruction cache unit (INSTRCACHE). For ease of understanding, the instruction (load, a0, 4 (a5)) is taken as an example.

Furthermore, the instruction translation operation is to decode the instruction.

Furthermore, for the decoded instruction, the corresponding data processing operation is performed on the instruction through the logical arithmetic component. For example, the specific operation performed on the instruction (load, a0, 4(a5)) is: perform an addition operation on the value of the a5 register and the decimal number 4 to obtain the storage address corresponding to the current load instruction, that is, addr=[a5]+4.

Furthermore, according to the address addr determined by the above calculation, a memory access operation is performed to access the storage address corresponding to addr and read data from the address.

Finally, the read data is written back to register a0.

Specifically, please refer to FIG. 1B , which is a schematic diagram of an instruction execution processing process of an existing architecture provided in an embodiment of the present application.

For example, if there are currently three load instructions that need to be processed by the electronic device, as shown in FIG1B , the electronic device performs the above five steps for each instruction: instruction fetch, instruction translation, execution, memory access, and write-back operations.

Among them, in the existing method, when the electronic device processes each load instruction, if the execution result of the previous load instruction has not been executed before the write-back operation, the next load instruction cannot proceed to the memory access stage. That is, the above processing process will cause the instructions to wait for each other, causing a pause, thereby affecting the efficiency of instruction execution. And if the operation corresponding to each load instruction is actually the same operation, but when iterating, it is still necessary to obtain the same load instruction each time and perform the same operation, resulting in redundancy of program code.

In response to the above problems, the present application proposes an instruction processing optimization method and related devices, as shown in FIG1C . FIG1C is a schematic diagram of the architecture of an electronic device provided by the present application for implementing instruction optimization processing.

Exemplarily, as shown in FIG1C, the architecture adds a custom register and a logic arithmetic component for continuous processing of load instructions on the basis of reusing the architecture shown in FIG1A. The specific hardware details are as follows: two custom registers with a bit width of 32-bit are added. Among them, the custom register 1 (i.e., the first register) is used to determine the source address for obtaining the target data, and the custom register 2 (i.e., the second register) is used to determine the destination address for storing the target data. After the electronic device performs the instruction fetch and instruction translation operations described in FIG1A, the two logic arithmetic components simultaneously determine the source address for obtaining the target data and the destination address for writing back the target data according to the data in the custom register 1 and the custom register 2. Further, the target data is obtained from the corresponding position according to the calculation result of the logic arithmetic component and the target data is written back. It should be noted that the current load instruction can be a load instruction that needs to perform data acquisition operations continuously. The logic arithmetic component only needs to determine the source address and destination address of each data acquisition based on the number of consecutive executions and the data in the two custom registers. In this process, there is no need to wait for each other between each repeated data acquisition and write-back operations. Thereby achieving the purpose of continuous processing of load instructions, improving data processing efficiency, and reducing power consumption of electronic devices.

Through the above architecture, the custom registers are flexibly configured in the original CPU architecture of the electronic device, so that the traditional CPU architecture can perform batch data operations. And this architecture is not only set up for specific fields, but also increases the viability of electronic devices in modern application scenarios. At the same time, it provides higher data throughput for current image processing, signal processing, artificial intelligence and other fields, and improves the efficiency of data processing by improving the fluency of instruction execution.

In order to better understand this solution, it will be described in detail below.

Please refer to FIG. 2, which is a flow chart of an instruction processing optimization method provided by an embodiment of the present application, which is applied to an electronic device, wherein the electronic device includes a first register and a second register, wherein the first register is used to determine a source address for obtaining target data, and the second register is used to determine a destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit; as shown in the figure, the instruction processing optimization method includes the following operations:

S201. Determine a target load instruction, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit.

Exemplarily, as shown in Figure 3, Figure 3 is a schematic diagram of a first register structure provided in an embodiment of the present application. As shown in Figure 3, the first register is a 32-bit register, specifically including a type identification bit, an offset bit, and an iteration count bit.

Specifically, the type identification bit C occupies 1 bit and is used to indicate whether the current load instruction is the first load instruction or the second load instruction. The first load instruction is used to indicate that the current load instruction needs to perform data acquisition and data write-back operations multiple times, that is, a pipelined load instruction; the second load instruction is used to indicate that the current load instruction performs data acquisition and data write-back operations once, that is, a normal load instruction.

Exemplarily, after receiving the decoded target load instruction, the electronic device determines whether the target load instruction is the first load instruction or the second load instruction according to the type identification bit in the first register.

S202: If the target load instruction is the first load instruction, determine a first source address according to the source address offset and the first load instruction, and determine a first destination address according to the initial destination address in the second register and the destination address offset.

Exemplarily, in the first register structure diagram shown in Fig. 3, the offset bit occupies 20 bits, wherein the offset bit includes a source address offset bit soffset and a destination address offset bit doffset.

Specifically, the source address offset bit soffset and the destination address offset bit doffset each occupy 10 bits, and the value corresponding to soffset is the source address offset, wherein the source address offset is used to determine each execution of the first load instruction to obtain the address corresponding to the target data. For example: if the first load instruction is (load, x, y), y is the initial source address, and soffset is a, then when the first load instruction is executed for the nth time, its source address is: y+(n-1)a. Furthermore, the electronic device obtains the target data from the corresponding position according to the source address determined each time. Among them, the source address includes the first source address, and the number of source addresses is consistent with the number of times the first load instruction is executed.

Specifically, the value corresponding to Doffset is used to determine the destination address of the memory space to write the target data back each time the first load instruction is executed. For example: if the first load instruction is (load, x, y), x is the initial destination address, and doffset is b, then when the first load instruction is executed for the nth time, its source address is: y+(n-1)b. Furthermore, the electronic device writes back the target data obtained each time the first load instruction is executed to the storage space corresponding to the destination address. Among them, the destination address includes the first destination address, and the number of destination addresses is consistent with the number of times the first load instruction is executed.

It should be noted that the process of determining the source address and the destination address by the electronic device through the above steps is a parallel operation, that is, the source address and the destination address are determined simultaneously. Specifically, the two logical arithmetic components shown in FIG. 1B can be processed in parallel to simultaneously determine the source address for obtaining the target data and the write-back destination address.

Exemplarily, a load instruction (load, a0, a5) is used as an example for detailed description. If the electronic device determines that the current load instruction is the first load instruction according to the type identification bit C, it means that the source address of each data acquisition is [a5] + soffset, that is, the data indicating the acquisition of the target data register address in the load instruction is superimposed with an offset corresponding to the source address shift soffset to obtain the actual source address of the target data. For example: if the value of the a5 register is 8 and soffset is 4, then when the first load instruction is executed for the first time, the source address of the first target data is 8, the source address of the second target data is 12 = 8 + 4, and the source address of the third target data is 16 = 12 + 4, and so on.

Exemplarily, if the current load instruction is the first load instruction, it means that each time the target data is obtained, when the write-back operation is performed, the destination address destAddr storing the target data needs to be superimposed on the initial destination address with an offset corresponding to the destination address shift doffset to obtain the destination address of the actual write-back target data. For example, in the above load instruction, if a0 is 1 and doffset is 5, if the first target data is obtained from the storage space with the storage address 8, the first destination address corresponding to the first target data is 1; the second target data is obtained from the source address 12, and the second target data corresponds to the second destination address of 6=1+(2-1)*5; the third target data is obtained from the storage address 16, and the third target data corresponds to the second destination address of 11=1+(3-1)*5.

It should be noted that, if the above source address and destination address confirmation process is performed continuously, each time the first load instruction is executed, the source address and destination address are the source address and destination address determined in the previous execution with the displacement added thereto.

S203. Acquire first target data according to the first source address.

Specifically, as described in step S202, after the electronic device determines the first source address according to the first load instruction and the source address offset bit in the first register, it performs a memory access operation to obtain the first target data in the storage space corresponding to the first source address.

S204. According to the first destination address, write the first target data back to a storage space corresponding to the first destination address.

Specifically, as described in step S202, after the electronic device determines the first destination address according to the first load instruction and the destination address offset bit in the first register, it performs a write-back operation to store the first target data in the storage space corresponding to the first destination address.

S205: Determine a final destination address according to the iterative calculation bit and the initial destination address, and determine whether the first load instruction has been executed according to the final destination address.

Exemplarily, the first register further includes an iteration calculation bit, wherein the iteration calculation bit occupies 11 bits and is used to indicate the number of iterations required for the current first load instruction.

Specifically, the electronic device determines the number of times the first load instruction needs to be iteratively executed according to the iterative calculation bit of the first register, and determines the initial destination address according to the first load instruction.

Furthermore, the electronic device calculates and determines the final destination address after executing the first load instruction according to the number of iterations, the destination address offset and the initial destination address, and determines whether the iterative execution is completed according to the final destination address.

S206: If the final destination address is the same as the first destination address, it is determined that the first load instruction is executed completely.

Specifically, if the iterative execution of the first load instruction is completed, the destination address determined by the electronic device when the electronic device executes the first load instruction for the last time is consistent with the final destination address.

Exemplarily, the electronic device executes the first load instruction once to determine the first destination address, compares whether the first destination address is the same as the final destination address, and if so, indicates that the current iterative execution process is finished, and if not, continues to execute the first load instruction to obtain the target data.

It can be seen that the instruction processing optimization method described in the embodiment of the present application, the electronic device includes a first register and a second register. Wherein, the electronic device includes a first register and a second register, the first register is used to determine the source address of the target data, the second register is used to determine the destination address of the target data, and the first register includes an offset bit and an iterative calculation bit; determine the target load load instruction, wherein the target load instruction includes any of the following: the first load instruction and the second load instruction, the offset bit includes the source address offset bit and the destination address offset bit; if the target load instruction is the first load instruction, then according to the source address offset bit and the first load instruction, determine the first source address, and according to the initial destination address and the destination address offset bit in the second register, determine the first destination address; according to the first source address, obtain the first target data; according to the first destination address, write the first target data back to the storage space corresponding to the first destination address; determine the final destination address according to the iterative calculation bit and the initial destination address, and judge whether the first load instruction is executed according to the final destination address; if the final destination address is the same as the first destination address, determine that the first load instruction is executed. In this way, batch data processing can be achieved through parallel processing of instructions, providing a higher data throughput rate for CPU to perform data processing.

In a possible example, before determining the target load instruction, the above method may include the following steps: acquiring an instruction and decoding the instruction to obtain instruction data, wherein the instruction data includes type identification data of the instruction; judging the type of the instruction according to the type identification data; if the type of the instruction is a load instruction type, determining the instruction as the target load instruction.

Exemplarily, as described in FIG. 1A and FIG. 1B , the electronic device obtains instructions from an instruction buffer unit, namely, performs an instruction fetch operation.

Furthermore, the electronic device performs instruction decoding operation on the acquired instruction, i.e., instruction translation operation, to obtain instruction data, wherein the instruction data includes type identification data indicating the current instruction type and also includes data indicating the current instruction operation. The instruction type includes but is not limited to: load instruction type and store instruction type, etc.

Furthermore, the electronic device determines the type of the current instruction according to the type identification data. If the current instruction is determined to be a load instruction, it further determines whether the load instruction is the first load instruction or the second load instruction according to the type identification bit C in the first register.

It can be seen that the electronic device performs an instruction fetch operation from the instruction buffer unit, obtains the instruction, and then performs an instruction translation operation on the instruction, and then determines whether the instruction type is a load instruction according to the instruction data obtained by the instruction translation operation, and if so, further determines the type of the load instruction according to the first register.

In one possible example, the first register also includes a type flag bit; for determining the target load instruction, the method may include the following steps: if the type flag bit is 1, determining that the target load instruction is the first load instruction; if the type flag bit is 0, determining that the target load instruction is the second load instruction.

Exemplarily, as shown in the structure of the first register in FIG3 , the first register includes a type identification bit C, which occupies 1 bit. The type identification bit represents the type of the target load instruction through 0/1.

Specifically, the electronic device obtains the type identification bit of the first register. If C is 1, it determines that the first load instruction is the first load instruction; if C is 0, it determines that the first load instruction is the second load instruction. It should be noted that the first load instruction is used to indicate that the target load instruction is a pipeline load instruction, which needs to be executed multiple times. The second load instruction is used to characterize that the target load instruction is a regular load instruction, and it can be processed in the usual way according to the five processing flows of instruction fetch, instruction translation, execution, memory access and write back.

It can be seen that in this example, after the electronic device determines whether the target load instruction is the first load instruction or the second load instruction according to the type identification bit of the first register, it can then correspondingly process the instruction according to the determination result, thereby improving the efficiency of instruction processing.

In one possible example, the instruction data of the target load instruction also includes address data, and the address data includes first address data for obtaining the target data and second address data for writing back the target data; the above method may include the following steps: determining a first address based on the first address data; obtaining the target data from a storage space corresponding to the first address; determining a second address based on the second address data; and storing the target data in a storage space corresponding to the second address.

Exemplarily, after the electronic device performs instruction decoding operation on the target load instruction, the instruction data of the target load instruction obtained includes address data in addition to type identification data indicating that the instruction type is load type, wherein the address data includes first address data for acquiring target data and second address data for writing back target data.

Exemplarily, taking the target load instruction (load, a0, a5) as an example, the parsed instruction data includes type identification data load used to indicate that the instruction type is a load type instruction, and address data a0 and a5, wherein the first address data is a5, which is used to indicate the register address corresponding to the target data; the second address data is a0, which is used to indicate the register address to which the target data is written back.

Furthermore, if the electronic device determines that the target load instruction is a second load instruction, that is, a regular load instruction, the electronic device determines a first address for obtaining the target data according to the first address data, and accesses the storage space corresponding to the first address to obtain the target data; determines a second address for writing back the target data according to the second address data, and writes the target data back to the storage space corresponding to the second address.

It can be seen that in this example, if the current target load instruction is the second load instruction, the electronic device can directly determine the first address that needs to be accessed when executing the second load instruction based on the instruction data corresponding to the second load instruction, and obtain the target data in the storage space corresponding to the first address, and determine the second address corresponding to the target data, and store the target data in the storage space corresponding to the second address. In this way, the first load instruction and the second load instruction can correspond to their respective processing flows and logical arithmetic components, realize personalized processing of instructions, and improve the processing efficiency of instructions.

In one possible example, the final destination address is determined based on the iterative calculation bits and the initial destination address. The method may include the following steps: determining the total number of iterations of the first load instruction based on the iterative calculation bits; determining the displacement of the initial destination address based on the destination address offset bits and the total number of iterations; and determining the final destination address based on the initial destination address and the displacement.

Exemplarily, as described in step S205, the iteration calculation bit in the first register occupies 11 bits, and the iteration calculation bit represents the number of iterations required for the current first load instruction in binary form. The electronic device determines the total number of iterations required to execute the first load instruction based on the data of the iteration calculation bit.

Furthermore, the electronic device determines the displacement relative to the initial destination address each time the first load instruction is executed according to the destination address offset bits stored in the first register.

Further, the electronic device determines the final destination address after executing the first load instruction according to the initial destination address in the first load instruction, the total number of iterations determined by the first register, and the offset corresponding to the destination address. The final destination address is calculated as follows: initial destination address + (total number of iterations - 1) * displacement of the initial destination address.

For example, the first load instruction is (load, a0, a5), the destination address offset bit is 011, and the iterative calculation bit is 11111111. Among them, a0 represents the initial destination address, a5 represents the initial source address, and the initial destination address is stored in the second register. The electronic device determines that the value corresponding to the current binary data is 255 according to the iterative calculation bit, which means that the first load instruction requires a total of 256 iterations, and the displacement of the initial destination address is determined to be 3 according to the destination address offset bit. After executing the first load instruction 256 times, the final destination address is a0+255*3.

It can be seen that in this example, the electronic device determines the total number of iterations of the first load instruction based on the iterative calculation bit, and then determines the displacement of the initial destination address based on the destination address offset bit and the total number of iterations; finally, the final destination address is determined based on the initial destination address and the displacement. In this way, while obtaining the instruction, the electronic device can also determine the final destination address corresponding to the instruction when the first load instruction is iteratively executed. The final destination address can then be used to determine whether the current first load instruction has been executed.

In a possible example, after determining whether the first load instruction has been executed based on the final destination address, the method may include the following steps: if the first destination address is different from the final destination address, determining a second source address based on the first source address and the source address offset bit, wherein the second source address is obtained by shifting the first source address by the source address offset bit; determining a second destination address based on the first destination address and the destination address offset bit, wherein the second destination address is obtained by shifting the first destination address by the destination address offset bit; obtaining second target data based on the second source address; and writing the second target data back to the storage space corresponding to the second destination address based on the second destination address.

Exemplarily, when the electronic device obtains the first load instruction, it can determine the final destination address after iteratively executing the first load instruction according to the first register and the second register. Further, when the electronic device executes the first load instruction once, the first destination address is obtained. It is determined whether the first destination address is the same as the final destination address. If they are the same, it indicates that the current iterative execution is completed; if they are different, the first load instruction is continued to be executed on the current basis.

Furthermore, the electronic device obtains the second source address according to the first source address and the source address offset corresponding to the source address offset bit, and obtains the second destination address according to the first destination address and the destination address offset corresponding to the destination address offset bit. That is, the source address and destination address corresponding to each execution of the first load instruction are the position offset results of the previous execution.

Furthermore, the electronic device obtains the second target data according to the second source address, and writes back the second target data according to the second destination address.

It should be noted that the above-mentioned second source address is one or more source addresses, used to represent the source address corresponding to the target data obtained each time the first load instruction is executed; the second destination address is one or more destination addresses, used to represent the destination address corresponding to the target data written back after each target data is obtained.

It can be seen that in this example, the electronic device determines whether the first load instruction has been executed based on the relationship between the destination address determined by each execution of the first load instruction and the final destination address. If it has not been executed, the source address and destination address of this execution can be determined according to the result of the previous execution, so as to realize the continuous execution of the first load instruction until the execution is completed, and the destination address corresponding to each write-back operation is the destination address of the previous execution shifted by a fixed destination address offset, so as to realize continuous storage of data, thereby ensuring the effective use of storage space and saving storage space.

In a possible example, the method of the present application may include the following steps: determining the number of iterations of the current execution of the first load instruction, wherein the number of iterations is less than or equal to the total number of iterations; if the number of iterations is less than the total number of iterations, determining a third source address and a third destination address based on the instruction data, the number of iterations, the source address offset bits corresponding to the first register, and the destination address offset bits.

For example, during each execution of the first load instruction, the electronic device needs to determine whether the current execution is completed. If the execution is not completed, it needs to be iteratively executed. If the electronic device needs to randomly determine the third source address and the third destination address corresponding to the current execution, it only needs to determine the number of iterations of the current first load instruction execution.

Exemplarily, if the current number of iterations is less than the total number of iterations, the third source address and the third destination address corresponding to the current execution of the first load instruction are determined according to the number of iterations, the source address offset bit and the destination address offset bit combined with the instruction data of the first load instruction. For the specific calculation method, please refer to the content described in step S202, which will not be repeated here. Among them, the third source address and the third destination address are the source address and the destination address corresponding to the execution of the first load instruction in a certain iteration.

It can be seen that in this example, the electronic device can determine the number of iterations of the current execution of the first load instruction; if the number of iterations is less than the total number of iterations, the third source address and the third destination address are determined according to the instruction data, the number of iterations, the source address offset bit and the destination address offset bit corresponding to the first register. In this way, the electronic device can randomly determine the source address and the destination address corresponding to the target data when the first load instruction is executed for the current time without having to completely rely on the result of the previous execution, resulting in a waiting phenomenon for instruction execution, thereby improving the efficiency of instruction processing and data loading.

Please refer to Figure 4A, which is a schematic diagram of the overall flow of an instruction processing optimization method provided in an embodiment of the present application, which is applied to an electronic device, wherein the electronic device includes a first register and a second register, the first register is used to determine a source address for obtaining target data, and the second register is used to determine a destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit; the instruction processing optimization method includes the following operations.

S401, the electronic device fetches instructions from an instruction buffer unit.

S402: The electronic device translates the retrieved instruction.

S403: The electronic device determines whether the current instruction is a load instruction. If not, the electronic device executes steps S410-S412 according to the instruction.

S404: If yes, the electronic device determines whether the load instruction is the first load instruction according to the first register.

S405: If it is the first load instruction, the electronic device calculates the source address of the first load instruction according to the first register through the logical arithmetic component.

S406. The electronic device determines whether the current remaining number of iterations is 0 according to the program counter. If not, it performs a memory access operation on the source address determined by the current execution of the first load instruction. After obtaining the target data, it returns to step S405 and calculates the source address of the next execution of the first load instruction according to the first register.

S407: If yes, perform a memory access operation on the source address determined by the current execution to obtain the target data.

S408: The electronic device determines, according to the first register and the second register, a destination address corresponding to each execution of the first load instruction.

S409: The electronic device writes the target data back to the storage space corresponding to the destination address according to the destination address determined each time.

S410: If the electronic device determines that the current instruction is the second load instruction or another type of instruction, the current instruction is executed to obtain a source address corresponding to the instruction.

S411. The electronic device accesses memory according to the source address obtained in step S410 to obtain data in the storage space corresponding to the source address.

S412: The electronic device writes back the acquired data to the destination address.

It should be noted that the specific description of the above steps S401-S409 can refer to the steps corresponding to steps S201-S206 of the instruction processing optimization method described in Figure 2. Steps S410-S412 are the corresponding processing steps when the electronic device determines that the target load instruction is the second load instruction, which will not be repeated here.

It can be seen that the instruction processing optimization method described in the embodiment of the present application, the electronic device includes a first register and a second register. Wherein, the electronic device includes a first register and a second register, the first register is used to determine the source address for obtaining the target data, the second register is used to determine the destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit; determine the target load instruction, wherein the target load instruction includes any of the following: a first load instruction and a second load instruction, the offset bit includes a source address offset bit and a destination address offset bit; if the target load instruction is the first load instruction, then according to the source address offset bit and the first load instruction, determine the first source address, and according to the initial destination address and the destination address offset bit in the second register, determine the first destination address; according to the first source address, obtain the first target data; according to the first destination address, write the first target data back to the storage space corresponding to the first destination address; determine the final destination address according to the iterative calculation bit and the initial destination address, and judge whether the first load instruction is executed according to the final destination address; if the final destination address is the same as the first destination address, determine that the first load instruction is executed; if the target load instruction is the second load instruction, execute the instruction, memory access and data write-back operations according to the conventional load instruction processing flow. In this way, batch data processing can be achieved through parallel processing of the first load instruction, providing a higher data throughput rate for the CPU to perform data processing. In addition, the electronic device can not only implement pipeline processing of the first load instruction through the customized first register and second register and the logical arithmetic component, but also retain the original work processing flow for the conventional load instruction, that is, the second load instruction. In this way, the internal storage space of the CPU of the electronic device can be maximized, the waste of resources can be reduced, and the energy efficiency ratio can be greatly optimized.

To better understand the processing of the electronic device for the first load instruction in the above steps S201-S206 and steps S401-S409, the following will be further described in conjunction with FIG. 4B, which is a schematic diagram of a process of an electronic device processing the first load instruction provided by an embodiment of the present application. Specifically, as shown in FIG. 4B:

Specifically, after the electronic device performs an instruction fetch operation from the instruction buffer unit, it performs an instruction translation operation on the instruction to obtain instruction data; further, according to the instruction data, it determines that the type of the current instruction is a load instruction type; further, in combination with the first register, it determines that the instruction is the first load instruction, that is, the instruction fetch and translation stage corresponding to FIG4B.

Further, the electronic device determines the total number of iterations of the current first load instruction according to the second register, and then, according to the first load instruction, the first register and the second register, determines the source address and the destination address corresponding to each execution of the first load instruction, that is, the execution stage corresponding to FIG4B .

Furthermore, the electronic device obtains the target data from the storage space corresponding to the source address, which is the memory access phase shown in FIG. 4B .

Furthermore, the electronic device writes the target data back to the storage space corresponding to the destination address determined by the current execution, which is the write-back stage shown in FIG4B .

It should be noted that after the electronic device determines that the current instruction is the first load instruction, the offset bits of the source address and the destination address can be determined according to the first register each time the first load instruction is executed; and the total number of iterations required for the first load instruction can be determined according to the second register. Therefore, the electronic device only needs to obtain the first load instruction in the first instruction fetch operation, and does not need to repeatedly obtain the first load instruction from the instruction buffer unit. In addition, the determination of the source address and the destination address only needs to be calculated according to the first load register and the second load register and the instruction data of the first load instruction, so as to respectively determine the source address required to access the memory and the destination address of the target data to be written back each time the instruction is executed. In this way, each execution of the first load instruction does not need to wait for the previous instruction to be executed to the write-back stage before starting, which can greatly reduce the time cost of iterative execution of instructions. At the same time, a first load instruction (i.e., a pipeline load instruction) is equivalent to repeatedly executing the second load instruction (i.e., a conventional load instruction) n times, that is, a first load instruction can execute n data loading operations, which greatly simplifies the host computer code, thereby reducing the code resource space on the chip, reducing the overall power consumption of the electronic device, greatly saving program code, and improving the efficiency of instruction processing.

Please refer to Figure 5, which is a structural diagram of an electronic device provided in an embodiment of the present application. As shown in Figure 5, the electronic device includes a processor, a memory, a communication interface, and one or more programs, and the one or more programs are stored in the memory and configured to be executed by the processor.

Optionally, when applied to an electronic device of the solution of the present application, the electronic device includes a first register and a second register, the first register is used to determine a source address for acquiring target data, the second register is used to determine a destination address for storing the target data, and the first register includes an offset bit and an iterative calculation bit; determine a target load instruction, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit;

If the target load instruction is the first load instruction, determining a first source address according to the source address offset and the first load instruction, and determining a first destination address according to the initial destination address in the second register and the destination address offset;

According to the first source address, obtaining first target data;

According to the first destination address, writing the first target data back to the storage space corresponding to the first destination address;

Determine a final destination address according to the iterative calculation bit and the initial destination address, and determine whether the first load instruction has been executed according to the final destination address;

If the final destination address is the same as the first destination address, it is determined that the first load instruction has been executed.

It can be seen that the electronic device described in the embodiment of the present application includes a first register and a second register. Among them, the electronic device includes a first register and a second register, the first register is used to determine the source address of the target data, the second register is used to determine the destination address of the target data, and the first register includes an offset bit and an iterative calculation bit; determine the target load load instruction, wherein the target load instruction includes any of the following: a first load instruction and a second load instruction, the offset bit includes a source address offset bit and a destination address offset bit; if the target load instruction is the first load instruction, then according to the source address offset bit and the first load instruction, determine the first source address, and according to the initial destination address and the destination address offset bit in the second register, determine the first destination address; according to the first source address, obtain the first target data; according to the first destination address, write the first target data back to the storage space corresponding to the first destination address; determine the final destination address according to the iterative calculation bit and the initial destination address, and judge whether the first load instruction is executed according to the final destination address; if the final destination address is the same as the first destination address, determine that the first load instruction is executed. In this way, batch data processing can be achieved through parallel processing of instructions, providing a higher data throughput rate for CPU to perform data processing.

In a possible example, before determining the target load instruction, the program includes instructions for executing the following steps:

Obtaining an instruction and decoding the instruction to obtain instruction data, wherein the instruction data includes type identification data of the instruction;

Determining the type of the instruction according to the type identification data;

If the type of the instruction is a load instruction type, the instruction is determined to be the target load instruction.

In a possible example, the first register further includes a type flag bit; the target is determined to load a load instruction, and the program includes instructions for executing the following steps:

If the type identification bit is 1, determining that the target load instruction is the first load instruction;

If the type identification bit is 0, it is determined that the target load instruction is the second load instruction.

In a possible example, the instruction data of the target load instruction further includes address data, and the address data includes first address data for acquiring the target data and second address data for writing back the target data; the above program includes instructions for executing the following steps:

Determine a first address according to the first address data;

Acquire the target data from the storage space corresponding to the first address;

determining a second address according to the second address data;

The target data is stored in the storage space corresponding to the second address.

In a possible example, the determining the final destination address according to the iterative calculation bit and the initial destination address, the program includes instructions for performing the following steps:

Determining a total number of iterations of the first load instruction according to the iteration count bit;

Determining the displacement of the initial destination address according to the destination address offset and the total number of iterations;

The final destination address is determined according to the initial destination address and the displacement.

In a possible example, after determining whether the first load instruction has been executed according to the final destination address, the program includes instructions for executing the following steps:

If the first destination address is different from the final destination address, determining a second source address according to the first source address and the source address offset, wherein the second source address is obtained by shifting the first source address by the source address offset;

Determine a second destination address according to the first destination address and the destination address offset bit, wherein the second destination address is obtained by shifting the first destination address by the destination address offset bit;

According to the second source address, obtaining second target data;

According to the second destination address, the second target data is written back to the storage space corresponding to the second destination address.

In one possible example, the above program includes instructions for executing the following steps:

Determine the number of iterations of the current execution of the first load instruction, wherein the number of iterations is less than or equal to the total number of iterations;

If the number of iterations is less than the total number of iterations, a third source address and a third destination address are determined according to the instruction data, the number of iterations, the source address offset bits corresponding to the first register, and the destination address offset bits.

The above mainly introduces the scheme of the embodiment of the present application from the perspective of the execution process on the method side. It is understandable that, in order to realize the above functions, the electronic device includes a hardware structure and/or software module corresponding to the execution of each function. Those skilled in the art should easily realize that, in combination with the units and algorithm steps of each example described in the embodiment provided herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application.

The embodiment of the present application can divide the functional units of the electronic device according to the above method example. For example, each functional unit can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated unit can be implemented in the form of hardware or in the form of software functional units. It should be noted that the division of units in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

In the case of dividing each functional module according to each function, FIG6 shows a schematic diagram of an instruction processing optimization device. As shown in FIG6, the instruction processing optimization device 600 applied to an electronic device may include: a determination unit 601, an acquisition unit 602, an execution unit 603 and a judgment unit 604; wherein,

The determining unit 601 is configured to determine a target load instruction, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit; and is configured to, if the target load instruction is the first load instruction, determine a first source address according to the source address offset bit and the first load instruction, and determine a first destination address according to an initial destination address in the second register and the destination address offset bit;

The acquisition unit 602 is used to acquire first target data according to the first source address;

The execution unit 603 is used to write the first target data back to the storage space corresponding to the first destination address according to the first destination address;

The judgment unit 604 is used to determine the final destination address according to the iterative calculation bit and the initial destination address, and to judge whether the first load instruction has been executed according to the final destination address; and to determine that the first load instruction has been executed if the final destination address is the same as the first destination address.

It can be seen that the instruction processing optimization device described in the embodiment of the present application determines the target load instruction through the determination unit of the electronic device, wherein the target load instruction includes any one of the following: a first load instruction and a second load instruction, and the offset bit includes a source address offset bit and a destination address offset bit; and, if the target load instruction is the first load instruction, the determination unit determines the first source address according to the source address offset bit and the first load instruction, and determines the first destination address according to the initial destination address and the destination address offset bit in the second register; the acquisition unit acquires the first target data according to the first source address; the execution unit writes the first target data back to the storage space corresponding to the first destination address according to the first destination address; the judgment unit determines the final destination address according to the iterative calculation bit and the initial destination address, and judges whether the first load instruction is executed according to the final destination address; if the final destination address is the same as the first destination address, it is determined that the first load instruction is executed. In this way, batch data processing can be achieved through parallel processing of instructions, providing a higher data throughput rate for CPU to perform data processing.

In a possible example, before determining the target load instruction, the determining unit 601 is specifically used to:

Obtaining an instruction and decoding the instruction to obtain instruction data, wherein the instruction data includes type identification data of the instruction;

Determining the type of the instruction according to the type identification data;

If the type of the instruction is a load instruction type, the instruction is determined to be the target load instruction.

In a possible example, the first register further includes a type flag bit; and the determining unit 601 is specifically configured to:

If the type identification bit is 1, determining that the target load instruction is the first load instruction;

If the type identification bit is 0, it is determined that the target load instruction is the second load instruction.

In a possible example, the instruction data of the target load instruction further includes address data, and the address data includes first address data for acquiring the target data and second address data for writing back the target data; the acquisition unit 602 and the execution unit 603 are specifically used for:

Determine a first address according to the first address data;

Acquire the target data from the storage space corresponding to the first address;

determining a second address according to the second address data;

The target data is stored in the storage space corresponding to the second address.

In a possible example, the determining the final destination address according to the iterative calculation bit and the initial destination address, the execution unit 603 is specifically configured to:

Determining a total number of iterations of the first load instruction according to the iteration count bit;

Determining the displacement of the initial destination address according to the destination address offset and the total number of iterations;

The final destination address is determined according to the initial destination address and the displacement.

In a possible example, after determining whether the first load instruction is executed according to the final destination address, the execution unit 603 is specifically configured to:

If the first destination address is different from the final destination address, determining a second source address according to the first source address and the source address offset, wherein the second source address is obtained by shifting the first source address by the source address offset;

Determine a second destination address according to the first destination address and the destination address offset bit, wherein the second destination address is obtained by shifting the first destination address by the destination address offset bit;

According to the second source address, obtaining second target data;

According to the second destination address, the second target data is written back to the storage space corresponding to the second destination address.

In a possible example, the execution unit 603 is specifically used to:

Determine the number of iterations of the current execution of the first load instruction, wherein the number of iterations is less than or equal to the total number of iterations;

If the number of iterations is less than the total number of iterations, a third source address and a third destination address are determined according to the number of iterations, the source address offset bit corresponding to the first register, and the destination address offset bit.

It should be noted that all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

The electronic device provided in this embodiment is used to execute the above instruction processing optimization method, and thus can achieve the same effect as the above implementation method.

In the case of using integrated units, the electronic device may include a processing module, a storage module and a communication module. Among them, the processing module can be used to control and manage the actions of the electronic device, for example, it can be used to support the electronic device to execute the steps performed by the above-mentioned determination unit 601, acquisition unit 602, execution unit 603 and judgment unit 604. The storage module can be used to support the electronic device to execute stored program codes and data, etc. The communication module can be used to support the communication between electronic devices.

Among them, the processing module can be a processor or a controller. It can implement or execute various exemplary logic boxes, modules and circuits described in conjunction with the disclosure of this application. The processor can also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of digital signal processing (DSP) and a microprocessor, etc. The storage module can be a memory. The communication module can specifically be a device that interacts with other electronic devices, such as a radio frequency circuit, a Bluetooth chip, a Wi-Fi chip, etc.

An embodiment of the present application also provides a computer storage medium, wherein the computer storage medium stores a computer program for electronic data exchange, wherein the computer program enables a computer to execute part or all of the steps of any method recorded in the above method embodiments, and the above computer includes an electronic device.

The embodiment of the present application also provides a computer program device, the computer program device includes a non-transitory computer-readable storage medium storing a computer program, and the computer program is operable to cause a computer to execute some or all of the steps of any method described in the above method embodiment. The computer program device can be a software installation package, and the computer includes an electronic device.

It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

In the several embodiments provided in the present application, it should be understood that the disclosed devices can be implemented in other ways. For example, the device embodiments described above are only schematic, such as the division of the above-mentioned units, which is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, and the indirect coupling or communication connection of devices or units can be electrical or other forms.

The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

If the above-mentioned integrated unit is implemented in the form of a software functional unit and sold or used as an independent device, it can be stored in a computer-readable memory. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software device, and the computer software device is stored in a memory, including a number of instructions to enable a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of the above-mentioned methods of each embodiment of the present application. The aforementioned memory includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

A person skilled in the art may understand that all or part of the steps in the various methods of the above embodiments may be completed by instructing the relevant hardware through a program, and the program may be stored in a computer-readable memory, which may include: a flash drive, a read-only memory, a random access memory, a magnetic disk or an optical disk, etc.

The embodiments of the present application are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for general technical personnel in this field, according to the idea of the present application, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims (10)

1. An instruction processing optimization method is applied to electronic equipment, and is characterized in that the electronic equipment comprises a first register and a second register, wherein the first register is used for determining a source address for acquiring target data, the second register is used for determining a destination address for storing the target data, and the first register comprises a deviation bit and an iterative calculation bit;

The method comprises the following steps:

Determining a target load instruction, wherein the target load instruction comprises any one of the following: a first load instruction and a second load instruction, the offset bits comprising a source address offset bit and a destination address offset bit;

If the target load instruction is the first load instruction, determining a first source address according to the source address offset bit and the first load instruction, and determining a first destination address according to an initial destination address in the second register and the destination address offset bit;

acquiring first target data according to the first source address;

According to the first destination address, the first target data is written back to a storage space corresponding to the first destination address;

determining a final destination address according to the iterative calculation bit and the initial destination address, and judging whether the first load instruction is executed according to the final destination address;

And if the final destination address is the same as the first destination address, determining that the first load instruction is executed.

2. The method of claim 1, wherein prior to the determining the target load instruction, the method further comprises:

Acquiring an instruction, and decoding the instruction to obtain instruction data, wherein the instruction data comprises type identification data of the instruction;

Judging the type of the instruction according to the type identification data;

And if the type of the instruction is a load instruction type, determining the instruction as the target load instruction.

3. The method of claim 2, wherein the first register further comprises a type flag bit; the determining a target load instruction includes:

If the type identification bit is 1, determining the target load instruction as the first load instruction;

and if the type identification bit is 0, determining the target load instruction as the second load instruction.

4. The method of claim 3, wherein the instruction data of the target load instruction further comprises address data, the address data comprising first address data to obtain the target data and second address data to write back the target data; the method further comprises the steps of:

Determining a first address according to the first address data;

Acquiring the target data from a storage space corresponding to the first address;

determining a second address according to the second address data;

And storing the target data into a storage space corresponding to the second address.

5. The method of claim 1, wherein said determining a final destination address from said iteratively calculated bits and said initial destination address comprises:

Determining the total number of iterations of the first load instruction according to the iteration calculation bit;

Determining the displacement of the initial destination address according to the destination address offset and the iteration total number;

And determining the final destination address according to the initial destination address and the displacement.

6. The method of claim 5, wherein after determining whether the first load instruction is executed based on the final destination address, the method further comprises:

If the first destination address is different from the final destination address, determining a second source address according to the first source address and the source address offset bit, wherein the second source address is obtained by shifting the source address offset bit by the first source address;

determining a second destination address according to the first destination address and the destination address offset, wherein the second destination address is obtained by shifting the destination address offset by the first destination address;

Acquiring second target data according to the second source address;

And according to the second destination address, writing the second target data back to a storage space corresponding to the second destination address.

7. The method of claim 5, wherein the method further comprises:

Determining the iteration number of the first load instruction executed at the current time, wherein the iteration number is smaller than or equal to the iteration total number;

If the iteration number is smaller than the iteration total number, determining a third source address and a third destination address according to the instruction data, the iteration number, the source address offset corresponding to the first register and the destination address offset.

8. An instruction processing optimization device applied to an electronic device, wherein the electronic device comprises a first register and a second register, the first register is used for determining a source address for acquiring target data, the second register is used for determining a destination address for storing the target data, and the first register comprises a deviation bit and an iterative calculation bit;

The device comprises: the device comprises a determining unit, an acquiring unit, an executing unit and a judging unit; wherein,

The determining unit is configured to determine a target load instruction, where the target load instruction includes any one of the following: a first load instruction and a second load instruction, the offset bits comprising a source address offset bit and a destination address offset bit; and if the target load instruction is the first load instruction, determining a first source address according to the source address offset and the first load instruction, and determining a first destination address according to an initial destination address in the second register and the destination address offset;

The acquisition unit is used for acquiring first target data according to the first source address;

The execution unit is used for writing the first target data back to a storage space corresponding to the first destination address according to the first destination address;

The judging unit is used for determining a final destination address according to the iterative calculation bit and the initial destination address, and judging whether the first load instruction is executed or not according to the final destination address; and determining that the first load instruction is executed if the final destination address is the same as the first destination address.

9. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-7.

10. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any one of claims 1-7.