JPH11185850A - Connection structure of circuit substrate and judging method for connection state of circuit substrate - Google Patents
Connection structure of circuit substrate and judging method for connection state of circuit substrateInfo
- Publication number
- JPH11185850A JPH11185850A JP9358260A JP35826097A JPH11185850A JP H11185850 A JPH11185850 A JP H11185850A JP 9358260 A JP9358260 A JP 9358260A JP 35826097 A JP35826097 A JP 35826097A JP H11185850 A JPH11185850 A JP H11185850A
- Authority
- JP
- Japan
- Prior art keywords
- circuit board
- signal line
- connection
- connection structure
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 238000000034 method Methods 0.000 title claims description 12
- 239000000758 substrate Substances 0.000 title description 6
- 239000000853 adhesive Substances 0.000 claims abstract description 9
- 230000001070 adhesive effect Effects 0.000 claims abstract description 9
- 239000004973 liquid crystal related substance Substances 0.000 claims description 28
- 230000002093 peripheral effect Effects 0.000 claims description 23
- 238000007689 inspection Methods 0.000 claims description 17
- 229910000679 solder Inorganic materials 0.000 claims description 4
- 238000009616 inductively coupled plasma Methods 0.000 description 24
- 235000010384 tocopherol Nutrition 0.000 description 24
- 235000019731 tricalcium phosphate Nutrition 0.000 description 24
- 239000011521 glass Substances 0.000 description 4
- 230000002950 deficient Effects 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 239000003566 sealing material Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/321—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
- H05K3/323—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/361—Assembling flexible printed circuits with other printed circuits
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Testing Electric Properties And Detecting Electric Faults (AREA)
- Liquid Crystal (AREA)
- Multi-Conductor Connections (AREA)
- Coupling Device And Connection With Printed Circuit (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、2枚の回路基板を
電気的に接続する回路基板の接続構造、及びその接続状
態判断方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board connection structure for electrically connecting two circuit boards, and a method for determining the connection state.
【0002】[0002]
【従来の技術】従来より、2枚の回路基板を電気的に接
続する回路基板の接続構造としては、種々のものが利用
されている。その一例を、図1を参照して説明する。2. Description of the Related Art Conventionally, various types of circuit board connection structures for electrically connecting two circuit boards have been used. One example will be described with reference to FIG.
【0003】図1は、従来の液晶装置の全体構成の一例
を示す平面図である。この図に示す液晶装置1は、液晶
を利用して種々の情報を表示する液晶パネルPを備えて
おり、この液晶パネルPは、間隙を開けて配置された一
対のガラス基板2,3と、これらのガラス基板2,3の
間に挟持された液晶(不図示)と、によって構成されて
いる。FIG. 1 is a plan view showing an example of the overall configuration of a conventional liquid crystal device. The liquid crystal device 1 shown in FIG. 1 includes a liquid crystal panel P that displays various kinds of information using liquid crystal. The liquid crystal panel P includes a pair of glass substrates 2 and 3 arranged with a gap therebetween; And a liquid crystal (not shown) sandwiched between the glass substrates 2 and 3.
【0004】そして、これらのガラス基板2,3の内面
には情報電極や走査電極といった電極がそれぞれ形成さ
れており、該電極はガラス基板2,3の端縁付近にまで
延設されている。また、これらの電極には複数のTCP
(Tape Carrier Package)7を介して周辺回路基板9が
接続されており、周辺回路基板9から液晶パネルPに対
して種々の信号が供給されるようになっている。Electrodes such as information electrodes and scanning electrodes are formed on the inner surfaces of the glass substrates 2 and 3, respectively, and extend to near the edges of the glass substrates 2 and 3. Also, these electrodes have multiple TCPs.
The peripheral circuit board 9 is connected via a (Tape Carrier Package) 7, and various signals are supplied from the peripheral circuit board 9 to the liquid crystal panel P.
【0005】図2は、TCPの詳細構造の一例を示す平
面図であるが、このTCP7は、ポリイミド樹脂からな
るフレキシブルフィルム7aを有しており、このフレキ
シブルフィルム7aには、集積化されチップ化された駆
動回路7bがTAB法(TapeAutomated Bonding法)に
より搭載され、封止材7cで固定されている(図3参
照)。そして、この駆動回路7bからフレキシブルフィ
ルム7aの両端部にかけて直線的に銅配線パターン7
d,7eが形成されている(以下、“入力リード7d”
“出力リード7e”とする)。このうち、入力リード7
dは、図3に示すように、ハンダや異方性導電接着剤
(ACF)等の接続部材10によって周辺回路基板(P
CB基板)9に接続されており、出力リード7eは異方
性導電接着剤(ACF)11によって液晶パネルP(正
確にはその電極)に接続されている。FIG. 2 is a plan view showing an example of the detailed structure of the TCP. The TCP 7 has a flexible film 7a made of a polyimide resin, and the flexible film 7a is integrated into a chip. The mounted drive circuit 7b is mounted by a TAB method (Tape Automated Bonding method) and fixed by a sealing material 7c (see FIG. 3). The copper wiring pattern 7 extends linearly from the drive circuit 7b to both ends of the flexible film 7a.
d, 7e (hereinafter referred to as “input lead 7d”).
"Output lead 7e"). Of these, input lead 7
d, as shown in FIG. 3, the peripheral circuit board (P) is connected by a connecting member 10 such as solder or anisotropic conductive adhesive (ACF).
The output lead 7e is connected to the liquid crystal panel P (more precisely, its electrode) by an anisotropic conductive adhesive (ACF) 11.
【0006】ところで、TCP側入力リード7dのピッ
チは0.2〜0.5mm程度と微小であり、TCP7と周
辺回路基板9との接続時にはそれらの位置合わせを正確
に行う必要がある。そこで、以下のような方法が採られ
ていた。Incidentally, the pitch of the TCP-side input leads 7d is as small as about 0.2 to 0.5 mm, and when the TCP 7 is connected to the peripheral circuit board 9, it is necessary to accurately position them. Therefore, the following method has been adopted.
【0007】すなわち、TCP7においては、図2に示
すように、信号の伝達を目的とはしないリード7f,7
g(以下、“TCP側ダミーリード7f,7g”とす
る)がコ字状に入力リード7dの両側にそれぞれ形成さ
れている。また、周辺回路基板9においては、図4に示
すように、信号の伝達を目的とはしないリード9a,9
b,9c,9d(以下、“基板側ダミーリード9a,9
b,9c,9d”とする)が4本形成されている。これ
らの基板側ダミーリード9a,9b,9c,9dは、互
いに電気的に接続されていない状態に形成されており、
TCP7が適正な接続位置にある状態で、TCP側ダミ
ーリード7f,7gの4つの端部に対向するようになっ
ている。そして、これらの基板側ダミーリード9a,9
b,9c,9dとTCP側ダミーリード7f,7gとは
異方性導電接着剤(ACF)10によって接続されてい
る。また、基板側ダミーリード9a,9b,9c,9d
は、TCP7(適正位置に接続された状態にあるTCP
7)と干渉しない位置にまで延設されており、各端部に
は端子12a,12b,12c,12dが接続されてい
る。That is, in the TCP 7, as shown in FIG. 2, the leads 7f, 7
g (hereinafter, referred to as “TCP-side dummy leads 7f, 7g”) are formed in U-shape on both sides of the input lead 7d. In the peripheral circuit board 9, as shown in FIG. 4, the leads 9a, 9
b, 9c, 9d (hereinafter “substrate-side dummy leads 9a, 9d”).
b, 9c, 9d "). These substrate-side dummy leads 9a, 9b, 9c, 9d are formed in a state where they are not electrically connected to each other.
In a state where the TCP 7 is at an appropriate connection position, the TCP 7 faces four ends of the TCP-side dummy leads 7f and 7g. Then, these substrate-side dummy leads 9a, 9
The b, 9c, 9d and the TCP side dummy leads 7f, 7g are connected by an anisotropic conductive adhesive (ACF) 10. Further, the substrate-side dummy leads 9a, 9b, 9c, 9d
Is TCP7 (TCP in a state where it is connected to an appropriate position)
7), and terminals 12a, 12b, 12c, 12d are connected to respective ends.
【0008】いま、TCP7と周辺回路基板9とが適正
な位置関係で接続されているとすると、隣接する端子1
2a,12bは、基板側ダミーリード9a,9bと異方
性導電接着剤(ACF)10とTCP側ダミーリード7
gとを介して導通された状態となり、他方の端子12
c,12dも導通された状態となっているはずである。
したがって、これらの隣接する端子(12a,12b又
は12c,12d)間の抵抗値を測定することで、周辺
回路基板9とTCP7とが良好に接続されたか否かが判
断できる。Now, assuming that the TCP 7 and the peripheral circuit board 9 are connected in a proper positional relationship, the adjacent terminals 1
2a and 12b are substrate-side dummy leads 9a and 9b, anisotropic conductive adhesive (ACF) 10, and TCP-side dummy leads 7;
g and the other terminal 12
c and 12d should also be in a conductive state.
Therefore, by measuring the resistance value between these adjacent terminals (12a, 12b or 12c, 12d), it can be determined whether the peripheral circuit board 9 and the TCP 7 have been connected well.
【0009】[0009]
【発明が解決しようとする課題】ところで、従来の方法
では、接続状態を判断するのは基板側ダミーリード9
a,9b,9c,9dとTCP側ダミーリード7f,7
gとについてであり、TCP側入力リード7dと周辺回
路基板側配線との接続状態を直接に判断するものではな
い。したがって、これらダミーリードの接続状態が良好
であっても、TCP側入力リード7dと周辺回路基板側
配線との接続状態が良好でない場合もあった。In the conventional method, the connection state is determined only by the board-side dummy leads 9.
a, 9b, 9c, 9d and TCP side dummy leads 7f, 7
g, but does not directly determine the connection state between the TCP-side input lead 7d and the peripheral circuit board-side wiring. Therefore, even when the connection state of these dummy leads is good, the connection state between the TCP-side input lead 7d and the wiring on the peripheral circuit board side may not be good.
【0010】また、TCP7にはダミーリード7f,7
gを別途設ける必要があり、TCP7が大型化して実装
上の障害になることが考えられ、TCP7のコストアッ
プという問題も引き起こしていた。The TCP 7 has dummy leads 7f, 7f.
g needs to be provided separately, and it is considered that the TCP 7 becomes large in size, which may be a hindrance in mounting, causing a problem of an increase in the cost of the TCP 7.
【0011】そこで、本発明は、2つの信号線の接続状
態を判断できる回路基板の接続構造及び接続状態判断方
法を提供することを目的とするものである。SUMMARY OF THE INVENTION It is an object of the present invention to provide a circuit board connection structure and a connection state determination method capable of determining a connection state between two signal lines.
【0012】また、本発明は、第2の回路基板の大型化
を防止できる回路基板の接続構造を提供することを目的
とするものである。It is another object of the present invention to provide a circuit board connection structure which can prevent the second circuit board from being enlarged.
【0013】[0013]
【課題を解決するための手段】本発明は上記事情を考慮
してなされたものであり、表面に第1の信号線が形成さ
れた第1の回路基板と、該第1の信号線に対向するよう
に第2の信号線が形成された第2の回路基板と、これら
第1及び第2の信号線を電気的に接続する接続部材と、
を備えた回路基板の接続構造において、前記第1の信号
線が、その接続部において一の部分と他の部分とに電気
的に絶縁された状態に分断され、かつ、前記一の部分と
他の部分とが共に前記接続部材を介して前記第2の信号
線に接続されている、ことを特徴とする。SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has a first circuit board having a first signal line formed on a surface thereof, and a first circuit board opposed to the first signal line. A second circuit board on which a second signal line is formed, a connecting member for electrically connecting the first and second signal lines,
In the connection structure of a circuit board provided with, the first signal line is divided into one part and another part in a state where the first signal line is electrically insulated from the other part at the connection part, and Are connected to the second signal line via the connection member.
【0014】また、本発明は、第1の回路基板の表面に
形成された第1の信号線、及び該第1の信号線に対向す
るように第2の回路基板に形成されると共に前記第1の
信号線に接続部材を介して電気的に接続された第2の信
号線の両信号線が適正に接続されているか否かを判断す
る接続状態判断方法において、前記第1の信号線が、一
の部分と他の部分とに電気的に絶縁された状態に分断さ
れたものであり、前記一の部分又は前記他の部分のいず
れか一方から任意の波形の信号を入力すると共に、その
他方において信号波形を測定し、かつ、前記入力した信
号波形と前記測定した信号波形との比較から、前記第1
の信号線と前記第2の信号線との接続状態を判断する、
ことを特徴とする。Further, according to the present invention, a first signal line formed on a surface of a first circuit board, and a second signal board formed on the second circuit board so as to face the first signal line, and In a connection state determining method for determining whether or not both signal lines of a second signal line electrically connected to one signal line via a connecting member are properly connected, the first signal line may be connected to the first signal line. , Which is divided into one part and another part in an electrically insulated state, and a signal of an arbitrary waveform is input from any one of the one part or the other part, and Measuring the signal waveform and comparing the input signal waveform with the measured signal waveform,
Judge the connection state between the signal line and the second signal line,
It is characterized by the following.
【0015】さらに、本発明は、第1の回路基板の表面
に形成された第1の信号線、及び該第1の信号線に対向
するように第2の回路基板に形成されると共に前記第1
の信号線に接続部材を介して電気的に接続された第2の
信号線の両信号線が適正に接続されているか否かを判断
する接続状態判断方法において、前記第1の信号線が、
一の部分と他の部分とに電気的に絶縁された状態に分断
されたものであり、前記一の部分と前記他の部分との間
の抵抗値を測定し、かつ、該測定した抵抗値から前記第
1の信号線と前記第2の信号線との接続状態を判断す
る、ことを特徴とする。Further, according to the present invention, a first signal line formed on a surface of a first circuit board, and a second signal board formed on a second circuit board so as to face the first signal line, and 1
In a connection state determining method for determining whether or not both signal lines of a second signal line electrically connected to a signal line via a connecting member are properly connected, the first signal line includes:
One part and the other part are separated in an electrically insulated state, a resistance value between the one part and the other part is measured, and the measured resistance value The connection state between the first signal line and the second signal line is determined from the following.
【0016】[0016]
【発明の実施の形態】以下、図5乃至図7を参照して、
本発明の実施の形態について説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIGS.
An embodiment of the present invention will be described.
【0017】図5は、本発明に係る回路基板の接続構造
の一実施の形態を示す側面図である。本実施の形態に係
る回路基板の接続構造20は、表面に第1の信号線21
が形成された第1の回路基板22と、該第1の信号線2
1に対向するように第2の信号線23が形成された第2
の回路基板25と、を備えており、これらの第1及び第
2の信号線21,23は接続部材26によって電気的に
接続されている。また、前記第1の信号線21は、一の
部分21aと他の部分21bとに電気的に絶縁された状
態に分断されており、これらの一の部分21aと他の部
分21bとが共に前記接続部材26を介して前記第2の
信号線23に接続されている。FIG. 5 is a side view showing one embodiment of a circuit board connection structure according to the present invention. The connection structure 20 of the circuit board according to the present embodiment has a first signal line 21 on the surface.
Formed on the first circuit board 22 and the first signal line 2
2 in which the second signal line 23 is formed so as to face
And the first and second signal lines 21 and 23 are electrically connected by a connection member 26. Further, the first signal line 21 is divided into one part 21a and another part 21b so as to be electrically insulated from each other, and the one part 21a and the other part 21b are both separated from each other. It is connected to the second signal line 23 via a connection member 26.
【0018】図6は、第1の回路基板22の構造を示す
平面図であるが、同図に示すように、前記第1の回路基
板22に一の補助信号線27を形成し、かつ、該一の補
助信号線27が、前記一の部分21aに電気的に接続さ
れると共に前記第2の回路基板25と干渉しない位置
(適正位置に接続された状態にあるTCP25と干渉し
ない位置。以下同じ)にまで延設されたようにするとよ
い。この場合、前記一の補助信号線27における前記第
2の回路基板25と干渉しない位置に第1検査用端子2
8を配置するとよい。FIG. 6 is a plan view showing the structure of the first circuit board 22. As shown in FIG. 6, one auxiliary signal line 27 is formed on the first circuit board 22, and A position where the one auxiliary signal line 27 is electrically connected to the one portion 21a and does not interfere with the second circuit board 25 (a position which does not interfere with the TCP 25 which is connected to an appropriate position. The same). In this case, the first inspection terminal 2 is located at a position on the one auxiliary signal line 27 where the first inspection terminal 2 does not interfere with the second circuit board 25.
8 should be arranged.
【0019】また、前記第1の回路基板22に他の補助
信号線29を形成し、かつ、該他の補助信号線29が、
前記他の部分21bに電気的に接続されると共に前記第
2の回路基板25と干渉しない位置にまで延設されたよ
うにするとよい。この場合、前記他の補助信号線29に
おける前記第2の回路基板25と干渉しない位置に第2
検査用端子30を配置するとよい。Further, another auxiliary signal line 29 is formed on the first circuit board 22, and the other auxiliary signal line 29 is
It is preferable that the second circuit board 25 is electrically connected to the other portion 21b and extends to a position where it does not interfere with the second circuit board 25. In this case, the second auxiliary signal line 29 is located at a position where it does not interfere with the second circuit board 25.
Inspection terminals 30 may be arranged.
【0020】なお、接続部材26としては、異方性導電
接着剤やハンダを用いることができる。As the connecting member 26, an anisotropic conductive adhesive or solder can be used.
【0021】また、前記第1の回路基板22としては、
図7に示すように、液晶素子Pの周辺に配置された周辺
回路基板を挙げることができ、前記第2の回路基板25
としては、前記周辺回路基板22と前記液晶素子Pとの
間に配置されたフレキシブルな回路基板を挙げることが
できる。The first circuit board 22 includes:
As shown in FIG. 7, a peripheral circuit board arranged around the liquid crystal element P can be mentioned.
For example, a flexible circuit board disposed between the peripheral circuit board 22 and the liquid crystal element P can be used.
【0022】次に、上記回路基板の接続構造20におい
て第1の信号線21と第2の信号線23との接続状態を
判断する接続判断方法の一実施の形態について説明す
る。Next, an embodiment of a connection judging method for judging the connection state between the first signal line 21 and the second signal line 23 in the connection structure 20 of the circuit board will be described.
【0023】上記回路基板の接続構造20において、前
記一の部分又は前記他の部分のいずれか一方(21a又
は21b)から任意の波形の信号を入力すると共に、そ
の他方(21b又は21a)において信号波形を測定
し、これらの波形(前記入力した信号波形、及び前記測
定した信号波形)を比較する。In the connection structure 20 of the circuit board, a signal having an arbitrary waveform is inputted from one of the one part or the other part (21a or 21b), and a signal is inputted from the other part (21b or 21a). The waveforms are measured, and these waveforms (the input signal waveform and the measured signal waveform) are compared.
【0024】ここで、前記第1の信号線21と前記第2
の信号線23とが適切に接続された状態であれば、前記
一の部分21aと前記他の部分21bとは前記第2の信
号線23を介して導通された状態にあるため前記2つの
波形(前記入力した信号波形、及び前記測定した信号波
形)は同じになる。したがって、これら2つの波形の比
較から、前記第1の信号線21と前記第2の信号線23
との接続状態が判断できる。Here, the first signal line 21 and the second
And the other portion 21b are in a state of conduction through the second signal line 23 when the two signal lines 23 are appropriately connected to each other. (The input signal waveform and the measured signal waveform) are the same. Therefore, from the comparison of these two waveforms, the first signal line 21 and the second signal line 23
Can be determined.
【0025】なお、前記一の部分21aと前記他の部分
21bとの間の抵抗値を測定することによって両信号線
21,23の接続状態を判断しても良い。The connection between the two signal lines 21 and 23 may be determined by measuring the resistance between the one part 21a and the other part 21b.
【0026】すなわち、前記第1の信号線21と前記第
2の信号線23とが適切に接続された状態であれば上述
のように前記一の部分21aと前記他の部分21bとは
導通状態にあることから、測定された抵抗値(一の部分
21aと他の部分21bとの間の抵抗値)は、 一の部分21aのラインor配線抵抗値と、 一の部分21aと第2の信号線23との間の接続抵
抗値(接続部材26の抵抗値)と、 一の部分21aと他の部分21bとの間の第2の信
号線23のラインor配線抵抗値と、 他の部分21bと第2の信号線23との間の接続抵
抗値(接続部材26の抵抗値)の抵抗値と、 他の部分21bのラインor配線抵抗値と、 の総和に等しいはずであり、このうちは既知であ
ることから、及びを算出でき、上述のように接続状
態を判断できる。That is, if the first signal line 21 and the second signal line 23 are properly connected, the one portion 21a and the other portion 21b are in a conductive state as described above. , The measured resistance value (the resistance value between the one part 21a and the other part 21b) is the line or wiring resistance value of the one part 21a, the one part 21a and the second signal A connection resistance value between the line 23 (resistance value of the connection member 26), a line or wiring resistance value of the second signal line 23 between one part 21a and another part 21b, and another part 21b. It should be equal to the sum of the resistance value of the connection resistance value (the resistance value of the connection member 26) between the second signal line 23 and the line or wiring resistance value of the other portion 21b. Since it is known, and can be calculated, and the connection state can be determined as described above. It can be.
【0027】次に、本実施の形態の効果について説明す
る。Next, effects of the present embodiment will be described.
【0028】本実施の形態によれば、第1の信号線21
と第2の信号線23との接続状態を判断でき、不良品の
チェックができる。According to the present embodiment, the first signal line 21
The connection state between the signal line and the second signal line 23 can be determined, and defective products can be checked.
【0029】また、本実施の形態に係る回路基板の接続
構造20は、このように信号線21,23の接続状態を
判断できるものでありながら、該接続状態の判断のため
の機構(従来のTCP側ダミーリード7g,7fに相当
するもの)を前記第2の回路基板25の側に何ら設ける
必要がなく、第2の回路基板25の大型化を防止でき
る。Further, the circuit board connection structure 20 according to the present embodiment is capable of determining the connection state of the signal lines 21 and 23 as described above, while providing a mechanism for determining the connection state (the conventional structure). There is no need to provide any TCP-side dummy leads 7g and 7f) on the second circuit board 25 side, so that the second circuit board 25 can be prevented from being enlarged.
【0030】さらに、上記回路基板の接続構造20を駆
動している状態で前記一の部分21a又は前記他の部分
21bをモニターすることにより、該駆動状態において
信号線21,23に入力される信号をモニターできる。Further, by monitoring the one portion 21a or the other portion 21b while the connection structure 20 of the circuit board is being driven, the signals input to the signal lines 21 and 23 in the driven state are monitored. Can be monitored.
【0031】[0031]
【実施例】(実施例1)本実施例においては、上述した
回路基板の接続構造を用いて図7に示す液晶装置40を
作成し、かつその接続状態を上述した方法によりチェッ
クした。Embodiment 1 In this embodiment, a liquid crystal device 40 shown in FIG. 7 was prepared using the above-described circuit board connection structure, and the connection state was checked by the above-described method.
【0032】図中の符号Pは液晶パネル(液晶素子)で
あり、符号22は、液晶パネルPの周辺に配置した第1
の回路基板としての周辺回路基板である。また、符号2
5は、周辺回路基板22と液晶パネルPとの間に配置し
た第2の回路基板としてのフレキシブルな回路基板(以
下、“TCP”とする)である。Reference numeral P in the figure denotes a liquid crystal panel (liquid crystal element), and reference numeral 22 denotes a first liquid crystal panel disposed around the liquid crystal panel P.
Is a peripheral circuit board as a circuit board. Also, reference numeral 2
Reference numeral 5 denotes a flexible circuit board (hereinafter, referred to as “TCP”) as a second circuit board disposed between the peripheral circuit board 22 and the liquid crystal panel P.
【0033】なお、周辺回路基板22の表面には、図6
に示すように配線(第1の信号線)21を形成し、TC
P25の表面には、配線21に対向するように入力リー
ド(第2の信号線)23を形成した。また、配線21
は、入力リード23に対向する部分において一部を分断
し、互いに電気的に絶縁された状態の接続端子21aと
接続端子21bとを形成した。また、TCP25の出力
リードは、液晶パネル側の電極に接続した。さらに、T
CP25には、図2に示したものと同様に駆動回路25
bを搭載した。The surface of the peripheral circuit board 22 is
The wiring (first signal line) 21 is formed as shown in FIG.
An input lead (second signal line) 23 was formed on the surface of P25 so as to face the wiring 21. The wiring 21
The connection terminal 21a and the connection terminal 21b are partially cut off at a portion facing the input lead 23, and are electrically insulated from each other. The output lead of the TCP 25 was connected to an electrode on the liquid crystal panel side. Furthermore, T
The CP25 includes a driving circuit 25 similar to that shown in FIG.
b.
【0034】本実施例においては、図6に示すように、
一の部分としての接続端子21aには信号配線31を接
続し、この信号配線31には不図示の制御回路からの各
種信号を入力するようにした。In this embodiment, as shown in FIG.
A signal wiring 31 is connected to the connection terminal 21a as one part, and various signals from a control circuit (not shown) are input to the signal wiring 31.
【0035】また、周辺回路基板22の表面には、接続
端子21aに電気的に接続された上でTCP25と干渉
しない位置にまで延設された補助配線(一の補助信号
線)27を形成し、補助配線27の端部には検査用チェ
ックパターン(第1検査用端子)28を接続した。On the surface of the peripheral circuit board 22, an auxiliary wiring (one auxiliary signal line) 27 which is electrically connected to the connection terminal 21a and extends to a position where it does not interfere with the TCP 25 is formed. An inspection check pattern (first inspection terminal) 28 was connected to an end of the auxiliary wiring 27.
【0036】さらに、周辺回路基板22の表面には、他
の部分としての接続端子21bに電気的に接続された上
でTCP25と干渉しない位置にまで延設された補助配
線(他の補助信号線)29を形成し、補助配線29の端
部には検査用チェックパターン(第2検査用端子)30
を接続した。Further, on the surface of the peripheral circuit board 22, an auxiliary wiring (another auxiliary signal line) which is electrically connected to the connection terminal 21b as another part and extends to a position which does not interfere with the TCP 25 ) 29 is formed, and an inspection check pattern (second inspection terminal) 30 is provided at the end of the auxiliary wiring 29.
Connected.
【0037】なお、周辺回路基板22の表面は、ソルダ
ーレジスト42にて被覆し、接続端子21a,21bや
検査用端子28,30の部分のみを開口させた。The surface of the peripheral circuit board 22 was covered with a solder resist 42, and only the connection terminals 21a and 21b and the inspection terminals 28 and 30 were opened.
【0038】また、TCP側の入力リード23と、周辺
回路基板側の接続端子21a,21bとは、接続部材と
しての異方性導電接着剤(ACF)26によって電気的
に接続した。なお、この接続は、TCP25の上方から
同時に熱圧着することによって行った。The input lead 23 on the TCP side and the connection terminals 21a and 21b on the peripheral circuit board side were electrically connected by an anisotropic conductive adhesive (ACF) 26 as a connection member. This connection was made by thermocompression bonding from above TCP 25 at the same time.
【0039】次に、信号配線31から接続端子21aに
所定波形の信号を入力すると共に、検査用チェックパタ
ーン30において信号波形を測定した。そして、これら
の波形(入力した信号波形、及び測定した信号波形)を
比較し、配線21と入力リード23との接続状態を判断
した。 (実施例2)上述した構造の液晶装置40において、検
査用チェックパターン28と検査用チェックパターン3
0との間の抵抗値を測定し、配線21と入力リード23
との接続状態を判断した。Next, a signal having a predetermined waveform was input from the signal wiring 31 to the connection terminal 21a, and a signal waveform was measured in the check pattern 30 for inspection. Then, by comparing these waveforms (the input signal waveform and the measured signal waveform), the connection state between the wiring 21 and the input lead 23 was determined. (Embodiment 2) In the liquid crystal device 40 having the above-described structure, the inspection check pattern 28 and the inspection check pattern 3
A resistance value between 0 and the wiring 21 and the input lead 23 is measured.
The connection status with was determined.
【0040】[0040]
【発明の効果】以上説明したように、本発明によると、
第1の信号線と第2の信号線との接続状態を判断でき、
不良品のチェックができる。As described above, according to the present invention,
The connection state between the first signal line and the second signal line can be determined,
Defective products can be checked.
【0041】また、本発明に係る回路基板の接続構造
は、このように信号線の接続状態を判断できるものであ
りながら、該接続状態の判断のための機構(従来のTC
P側ダミーリード7g,7fに相当するもの)を前記第
2の回路基板の側に何ら設ける必要がなく、第2の回路
基板の大型化を防止できる。Further, the circuit board connection structure according to the present invention is capable of determining the connection state of the signal line as described above, while providing a mechanism for determining the connection state (conventional TC board).
There is no need to provide any P-side dummy leads 7g, 7f) on the side of the second circuit board, and it is possible to prevent the second circuit board from being enlarged.
【図1】従来の液晶装置の全体構成の一例を示す平面
図。FIG. 1 is a plan view showing an example of the overall configuration of a conventional liquid crystal device.
【図2】TCPの詳細構造の一例を示す平面図。FIG. 2 is a plan view showing an example of a detailed structure of TCP.
【図3】従来の液晶装置における、液晶パネルと周辺回
路基板とTCPとの接続状態等を説明するための側面
図。FIG. 3 is a side view for explaining a connection state and the like between a liquid crystal panel, a peripheral circuit board, and a TCP in a conventional liquid crystal device.
【図4】従来の液晶装置における、周辺回路基板とTC
Pとの接続状態等を説明するための平面図。FIG. 4 shows a peripheral circuit board and a TC in a conventional liquid crystal device.
FIG. 3 is a plan view for explaining a connection state with P and the like.
【図5】本発明に係る回路基板の接続構造の一実施の形
態を示す側面図。FIG. 5 is a side view showing one embodiment of a circuit board connection structure according to the present invention.
【図6】本発明にて用いる第1の回路基板の構造を示す
平面図。FIG. 6 is a plan view showing the structure of a first circuit board used in the present invention.
【図7】本発明を適用した液晶装置全体の構成を示す
図。FIG. 7 is a diagram showing a configuration of an entire liquid crystal device to which the present invention is applied.
20 回路基板の接続構造 21 配線(第1の信号線) 21a 接続端子(一の部分) 21b 接続端子(他の部分) 22 周辺回路基板(第1の回路基板) 23 入力リード(第2の信号線) 25 フレキシブルな回路基板(第2の回路基板) 26 異方性導電接着剤(接続部材) 27 補助配線(一の補助信号線) 28 検査用チェックパターン(第1検査用端子) 29 補助配線(他の補助信号線) 30 検査用チェックパターン(第2検査用端子) 40 液晶装置 P 液晶パネル(液晶素子) Reference Signs List 20 connection structure of circuit board 21 wiring (first signal line) 21a connection terminal (one part) 21b connection terminal (other part) 22 peripheral circuit board (first circuit board) 23 input lead (second signal) 25) Flexible circuit board (second circuit board) 26 Anisotropic conductive adhesive (connection member) 27 Auxiliary wiring (one auxiliary signal line) 28 Inspection check pattern (first inspection terminal) 29 Auxiliary wiring (Other auxiliary signal lines) 30 Check pattern for inspection (second inspection terminal) 40 Liquid crystal device P Liquid crystal panel (liquid crystal element)
Claims (10)
回路基板と、該第1の信号線に対向するように第2の信
号線が形成された第2の回路基板と、これら第1及び第
2の信号線を電気的に接続する接続部材と、を備えた回
路基板の接続構造において、 前記第1の信号線が、その接続部において一の部分と他
の部分とに電気的に絶縁された状態に分断され、かつ、 前記一の部分と他の部分とが共に前記接続部材を介して
前記第2の信号線に接続されている、 ことを特徴とする回路基板の接続構造。A first circuit board having a first signal line formed on a surface thereof; a second circuit board having a second signal line formed so as to face the first signal line; A connection member for electrically connecting the first and second signal lines, wherein the first signal line is connected to one portion and another portion at the connection portion. The circuit board is divided into an electrically insulated state, and both the one part and the other part are connected to the second signal line via the connection member. Connection structure.
形成し、かつ、 該一の補助信号線が、前記一の部分に電気的に接続され
ると共に前記第2の回路基板と干渉しない位置にまで延
設された、 ことを特徴とする請求項1に記載の回路基板の接続構
造。2. An auxiliary signal line is formed on the first circuit board, and the one auxiliary signal line is electrically connected to the one portion and is connected to the second circuit board. The circuit board connection structure according to claim 1, wherein the connection structure extends to a position where no interference occurs.
回路基板と干渉しない位置に第1検査用端子を配置し
た、 ことを特徴とする請求項2に記載の回路基板の接続構
造。3. The circuit board connection structure according to claim 2, wherein a first inspection terminal is arranged at a position in the one auxiliary signal line that does not interfere with the second circuit board.
形成し、かつ、 該他の補助信号線が、前記他の部分に電気的に接続され
ると共に前記第2の回路基板と干渉しない位置にまで延
設された、 ことを特徴とする請求項1乃至3のいずれか1項に記載
の回路基板の接続構造。4. An auxiliary signal line is formed on the first circuit board, and the other auxiliary signal line is electrically connected to the other portion and is connected to the second circuit board. The connection structure for a circuit board according to any one of claims 1 to 3, wherein the connection structure extends to a position where no interference occurs.
回路基板と干渉しない位置に第2検査用端子を配置し
た、 ことを特徴とする請求項4に記載の回路基板の接続構
造。5. The circuit board connection structure according to claim 4, wherein a second inspection terminal is arranged at a position in the other auxiliary signal line which does not interfere with the second circuit board.
る、 ことを特徴とする請求項1乃至5のいずれか1項に記載
の回路基板の接続構造。6. The circuit board connection structure according to claim 1, wherein the connection member is an anisotropic conductive adhesive.
の回路基板の接続構造。7. The circuit board connection structure according to claim 1, wherein the connection member is solder.
に配置された周辺回路基板であり、かつ、 前記第2の回路基板が、前記周辺回路基板と前記液晶素
子との間に配置されたフレキシブルな回路基板である、 ことを特徴とする請求項1乃至7に記載の回路基板の接
続構造。8. The first circuit board is a peripheral circuit board arranged around a liquid crystal element, and the second circuit board is arranged between the peripheral circuit board and the liquid crystal element. The circuit board connection structure according to claim 1, wherein the connection structure is a flexible circuit board.
の信号線、及び該第1の信号線に対向するように第2の
回路基板に形成されると共に前記第1の信号線に接続部
材を介して電気的に接続された第2の信号線の両信号線
が適正に接続されているか否かを判断する接続状態判断
方法において、 前記第1の信号線が、一の部分と他の部分とに電気的に
絶縁された状態に分断されたものであり、 前記一の部分又は前記他の部分のいずれか一方から任意
の波形の信号を入力すると共に、その他方において信号
波形を測定し、かつ、 前記入力した信号波形と前記測定した信号波形との比較
から、前記第1の信号線と前記第2の信号線との接続状
態を判断する、 ことを特徴とする接続状態判断方法。9. A first circuit board formed on a surface of a first circuit board.
And a second signal line formed on the second circuit board so as to face the first signal line and electrically connected to the first signal line via a connection member. A connection state determination method for determining whether or not both signal lines are properly connected, wherein the first signal line is divided into a state in which one part and another part are electrically insulated. A signal having an arbitrary waveform is input from one of the one part and the other part, and a signal waveform is measured in the other part, and the input signal waveform and the measured signal waveform are A connection state between the first signal line and the second signal line is determined from the comparison.
1の信号線、及び該第1の信号線に対向するように第2
の回路基板に形成されると共に前記第1の信号線に接続
部材を介して電気的に接続された第2の信号線の両信号
線が適正に接続されているか否かを判断する接続状態判
断方法において、 前記第1の信号線が、一の部分と他の部分とに電気的に
絶縁された状態に分断されたものであり、 前記一の部分と前記他の部分との間の抵抗値を測定し、
かつ、 該測定した抵抗値から前記第1の信号線と前記第2の信
号線との接続状態を判断する、 ことを特徴とする接続状態判断方法。10. A first signal line formed on a surface of a first circuit board, and a second signal line opposed to the first signal line.
Connection state determination for determining whether or not both signal lines of a second signal line formed on the circuit board and electrically connected to the first signal line via a connection member are properly connected. The method, wherein the first signal line is divided into one part and another part so as to be electrically insulated from each other, and a resistance value between the one part and the other part. Measure
And a connection state between the first signal line and the second signal line is determined from the measured resistance value.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9358260A JPH11185850A (en) | 1997-12-25 | 1997-12-25 | Connection structure of circuit substrate and judging method for connection state of circuit substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9358260A JPH11185850A (en) | 1997-12-25 | 1997-12-25 | Connection structure of circuit substrate and judging method for connection state of circuit substrate |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH11185850A true JPH11185850A (en) | 1999-07-09 |
Family
ID=18458371
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9358260A Withdrawn JPH11185850A (en) | 1997-12-25 | 1997-12-25 | Connection structure of circuit substrate and judging method for connection state of circuit substrate |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH11185850A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006126294A (en) * | 2004-10-26 | 2006-05-18 | Toshiba Matsushita Display Technology Co Ltd | Planar display device |
JP2010060813A (en) * | 2008-09-03 | 2010-03-18 | Hitachi Displays Ltd | Display apparatus |
CN105929319A (en) * | 2016-04-20 | 2016-09-07 | 浪潮电子信息产业股份有限公司 | Test equipment connection method based on anisotropic conductive adhesive |
-
1997
- 1997-12-25 JP JP9358260A patent/JPH11185850A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006126294A (en) * | 2004-10-26 | 2006-05-18 | Toshiba Matsushita Display Technology Co Ltd | Planar display device |
JP2010060813A (en) * | 2008-09-03 | 2010-03-18 | Hitachi Displays Ltd | Display apparatus |
US8836675B2 (en) | 2008-09-03 | 2014-09-16 | Japan Display Inc. | Display device to reduce the number of defective connections |
CN105929319A (en) * | 2016-04-20 | 2016-09-07 | 浪潮电子信息产业股份有限公司 | Test equipment connection method based on anisotropic conductive adhesive |
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