JPH11185478A - Memory element, logic circuit and data processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory element enabling the high speed read or write of data. SOLUTION: The memory element 10 comprises a first and second output data buses DBO1, DBO2 and first and second input data buses DVI1, DBI2. Address converter circuit 12 sends a row address signal RA to a row decoder 13 and first and second column address signals CA1, CA2 to a column decoder 14, based on a first and second address signals AD1, AD2. The row decoder 13 selects a word line WL and the column decoder 14 selects two data lines DL. I/O control circuit 15 connects the selected to data lines DL to the first and second output data buses DBO1, DBO2 or input data buses DBI1, DBI2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory device, a logic circuit, and a data processing device having the same.

[0002]

2. Description of the Related Art Data processing such as expansion and compression of audio data and image data is performed by, for example, combining a memory element and a logic circuit. As the memory element, a DRAM (dynamic random access memory), an SRAM (static random access memory), or the like is used. A large amount of data is stored in a memory element, and a logic circuit performs processes such as addition, subtraction, and comparison with data read from the memory element.

A logic circuit specifies an address indicating a location where data is stored in a memory element in order to read data from the memory element. When a plurality of data are required for data processing, the logic circuit must sequentially specify addresses at which all necessary data are stored. For example, addresses 10 and 5 in the memory element
When reading data stored at address 0, addresses 10 and 50 are sequentially specified as addresses.

FIG. 9 is a block diagram showing a configuration of a conventional memory device. As shown in FIG.
Are the memory cell array 110 and the address conversion circuit 12
0, row decoder 130, column decoder 140 and I / O
An (input / output) control circuit 150 is included.

The memory cell array 110 includes 2 ^{N + M} memory cells arranged in a matrix of 2 ^N rows and 2 ^M columns. Here, N and M are each an arbitrary integer. 2 ^N word lines (row selection lines) are arranged corresponding to 2 ^N rows of memory cells. Also, 2 ^M data lines (column selection lines) are arranged corresponding to 2 ^M columns of the memory cells. Each memory cell is connected to a corresponding word line and a corresponding data line. In FIG. 9,
Only one word line WL, one data line DL and one memory cell MC connected to them are shown.

The address conversion circuit 120 receives an address signal AD from the logic circuit 400. Address conversion circuit 120 applies a row address signal RA to row decoder 130 and a column address signal CA to column decoder 140 based on address signal AD.

Row decoder 130 has a row address signal RA
Is decoded, and one word line WL in the memory cell array 110 is selected. Column decoder 140 decodes column address signal CA, and stores 1 in memory cell array 110.
One data line DL is selected. As a result, the memory cell MC at the intersection of the selected word line WL and the selected data line DL is selected.

The I / O control circuit 150 is supplied with a read signal for controlling data reading and a write signal for controlling data writing from the logic circuit 400 via the control line CL. The I / O control circuit 150 provides data read from the selected memory cell MC to the data bus DB in response to the read signal. The data on the data bus DB is
Input to 0. In response to the write signal, the I / O control circuit 150 converts the data supplied from the logic circuit 400 to the data bus DB to the selected memory cell MC.
Write to.

In this manner, data is read from or written to one selected memory cell MC in the memory cell 110. In the memory element 100,
Actually, a plurality of memory cell arrays 110 are provided corresponding to one byte of data, and one byte of data is read or written at the same time.

FIG. 10 is a block diagram showing a configuration of a conventional processor as an example of a logic circuit.

The processor 200 includes an SRAM or D
A memory element 100 constituted by a RAM is connected. The memory element 100 in FIG. 10 has an address signal input terminal A for inputting an address signal, a data input terminal DI for inputting data, and a data output terminal DO for outputting data.

The processor 200 has an ALU (Arithmetic).
and Logic Unit) 210, register 22
0 and the program counter 230. The instruction memory 300 is composed of a ROM (Read Only Memory). A program is stored in the instruction memory 300, and the processor 200 operates based on the program in the instruction memory 300.

The program counter 230 indicates the address in the instruction memory 300 where the next instruction to be executed is stored. The instruction is read from the instruction memory 300 based on the address specified by the program counter 230 and interpreted by the register 220.

When reading data from the memory element 100, the ALU 210 supplies an address signal AD to an address signal input terminal A of the memory element 100 and a read signal to a control signal input terminal (not shown). . Thus, data is read from a predetermined address in the memory element 100 to the data output terminal DO.

The ALU 210 includes a memory element 100
When writing data to the memory device 100,
, An address signal AD to the address signal input terminal A, data to the data input terminal DI, and a write signal to the control signal input terminal (not shown). Thereby, the data at the data input terminal DI is written to a predetermined address in the memory element 100.

[0016]

In the above-mentioned conventional memory element 100, one data is read from one memory cell array 110 in one read operation, and one byte of data is read as a whole of the memory element 100. It is. Therefore, the memory cell array 110 is used for data processing.
When a plurality of bytes of data are required, it is necessary to read the data one byte at a time.

For example, 10 of memory cell array 110
When reading the data stored in the addresses of address 50 and address 50, address 10 and address 50 are sequentially specified as addresses, so that
It is necessary to sequentially read the data at address and the data at address 50. Therefore, when a large amount of data needs to be read from the memory element 100, the data processing time becomes long.

An object of the present invention is to provide a memory element capable of reading or writing a plurality of data at high speed.

Another object of the present invention is to provide a logic circuit capable of performing data processing at high speed.

Still another object of the present invention is to provide a data processing circuit having a logic circuit and a memory element capable of performing data processing at high speed.

[0021]

Means for Solving the Problems and Effects of the Invention (1)
First invention A memory element according to a first invention comprises a plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and at least two of the plurality of data lines based on at least two selection signals. And a selection circuit for simultaneously selecting two data lines.

In the memory device according to the present invention, at least two of the plurality of data lines are simultaneously selected by the selection circuit based on at least two selection signals. Therefore, a plurality of data can be read or written at the same time.

(2) Second invention The memory element according to the second invention is the same as the memory element according to the first invention, except that at least two data buses and at least two data lines selected by the selection circuit are provided. And a connection circuit for connecting each to at least two data buses.

In this case, it is possible to simultaneously access at least two memory cells via at least two data buses.

(3) Third invention In the memory device according to the third invention, in the configuration of the memory device according to the first and second inventions, the selection circuit includes at least two decoding circuits for decoding at least two selection signals, respectively. One decoder.

Thus, at least two selection signals are respectively decoded by different decoders, and at least two data lines are selected.

(4) Fourth Invention A memory device according to a fourth invention comprises a plurality of word lines, a plurality of data lines provided so as to intersect the plurality of word lines, and a plurality of word lines and a plurality of word lines. A memory cell array including a plurality of memory cells provided at an intersection with a data line; at least two data buses; and a first selecting one of a plurality of word lines of the memory cell array in response to a first selection signal. One selection circuit, a second selection circuit for simultaneously selecting at least two of the plurality of data lines of the memory cell array in response to at least two second selection signals, and a second selection circuit.
And a connection circuit for connecting at least two data lines selected by the selection circuit to at least two data buses.

In the memory device according to the present invention, the first
, One word line in the memory cell array is selected, and at least two data lines in the memory cell array are simultaneously selected in response to at least two second selection signals. Thereby, at least two memory cells on one word line are simultaneously selected. Therefore, a plurality of data can be read or written at the same time.

(5) Fifth Invention A memory device according to a fifth invention is the memory device according to the fourth invention, wherein at least two address buses receiving at least two address signals and at least two address buses are provided. An address conversion circuit for providing a first selection signal to the first selection circuit based on at least two address signals on the bus and providing at least two second selection signals to the second selection circuit It is.

In this case, one word line in the memory cell array is selected based on at least two address signals, and at least two data lines are simultaneously selected, whereby at least two memory cells on one word line are selected. Selected at the same time.

(6) Sixth invention A memory device according to a sixth invention is the memory device according to the fifth invention, wherein each of at least two address signals is a first selection signal and a second selection signal. Signals in parallel, the address conversion circuit supplies a first selection signal included in one of the at least two address signals to the first selection circuit, and a second selection signal included in the at least two address signals. To the second selection circuit.

In this case, since the first selection signal and at least two second selection signals are applied simultaneously, it is possible to access at least two memory cells in the memory cell array at a higher speed.

(7) Seventh invention A memory device according to a seventh invention is the memory device according to the fifth invention, wherein each of at least two address signals has a first selection signal and a second selection signal. The signals are time-division multiplexed, and the address conversion circuit supplies the first selection signal multiplexed to one of the at least two address signals to the first selection circuit at a first timing, A second selection signal multiplexed with at least two address signals at a timing of 2 is supplied to a second selection circuit.

In this case, since the first selection signal and at least two second selection signals are provided in a time-division manner, the number of signal lines of the address bus is reduced.

(8) Eighth Invention The memory device according to the eighth invention is the memory device according to any one of the fourth to seventh inventions, wherein the second selection circuit comprises at least two second memories. At least two decoders for respectively decoding the selection signals of.

Thus, at least two second selection signals are respectively decoded by different decoders, and at least two data lines are selected.

(9) Ninth Invention A memory device according to a ninth invention is the memory device according to any one of the fourth to seventh inventions, wherein
One data bus includes at least two input data buses and at least two output data buses.

In this case, data can be read from at least two memory cells in the memory cell array via at least two output data buses, and at least two memory cells in the memory cell array can be read via at least two input data buses. Data can be written to two memory cells. This makes it possible to independently control the reading and writing of data.

(10) Tenth invention A memory device according to a tenth invention is a memory device according to the fourth to eighth inventions, wherein at least two data buses are at least two input / output data buses. Is included.

In this case, data can be read from and written to at least two memory cells in the memory cell array via at least two input / output data buses. Thereby, the number of signal lines of the data bus is reduced.

(11) Eleventh Invention A logic circuit according to an eleventh invention has at least two address buses for simultaneously outputting at least two address signals.

In this case, at least two pieces of data can be read from and written to the memory element at the same time. Thus, data processing can be performed at high speed.

(12) Twelfth Invention A data processing circuit according to a twelfth invention is directed to a logic circuit according to the eleventh invention which simultaneously outputs at least two address signals, and at least two address signals from the logic circuit. The first accessed by the selection signal based on
To a memory element according to any one of the tenth to tenth aspects.

In this case, the logic circuit can simultaneously read and write at least two data from and to the memory element. Thus, data processing can be performed at high speed.

(13) Thirteenth Invention A data processing circuit according to a thirteenth invention is the same as the data processing circuit according to the twelfth invention, except that the logic circuit and the memory element are formed on a common chip. is there.

Thus, a small data processing circuit capable of performing data processing at high speed is realized.

[0047]

FIG. 1 is a block diagram showing a configuration of a data processing circuit according to an embodiment of the present invention.

The data processing circuit shown in FIG.
0, a processor 20, and an instruction memory 30. These memory element 10, processor 20 and instruction memory 30 are formed on a common chip CH.

The memory element 10 includes the memory cell array 1
1, address conversion circuit 12, row decoder 13, column decoder 14, I / O (input / output) control circuit 15, first and second output data buses DBO1, DBO2, first and second input data bus DBI1, DBI2 and control line CL are included.

The memory cell array 11 has 2^NRow and 2
^M2 arranged in a matrix in columns ^{N + M}Memory cells
including. Here, N and M are arbitrary integers, respectively.
is there. Memory cell 2^N2 for a row^NBook word line
(Row selection lines) are arranged. In addition, 2 of the memory cells
^M2 for columns^MData lines (column selection lines)
Have been. Each memory cell has a corresponding word line and pair
It is connected to the corresponding data line. Note that FIG.
Word lines WL, two data lines DL and
Only two connected memory cells MC are shown.

On the other hand, the processor 20 has an ALU (Arithm
etic and Logic Unit; 21, register 2
2 and a program counter 23. The instruction memory 30 is composed of a ROM (Read Only Memory). A program is stored in the instruction memory 30, and the processor 20 operates based on the program in the instruction memory 30.

The program counter 23 of the processor 20
Is an instruction memory 3 in which an instruction to be executed next is stored.
Indicates an address within 0. The instruction is read from the instruction memory 30 based on the address specified by the program counter 23 and interpreted by the register 22.

The ALU 21 has first and second address buses 211 and 212. When the instruction interpreted by the register 22 requires access (data reading or writing) to two memory cells MC on the same word line WL in the memory cell array 11, the first And second address bus 21
The first address signal AD1 and the second address signal AD2 are supplied to the address conversion circuit 12 of the memory element 10 via the first and second signals 212.

When reading data, the processor 20
From the control line CL to the I / O control circuit 15 of the memory element 10.
A read signal is provided via the control line CL from the processor 20 to the I / O control circuit 15 of the memory element 10 at the time of writing data.
And data are applied to second input data buses DBI1 and DBI2, respectively.

Address conversion circuit 12 of memory element 10
Supplies the row address signal RA to the row decoder 13 based on the first address signal AD1 and the first column address signal CA1 to the column decoder 14. Further, the address conversion circuit 12 supplies a second column address signal CA2 to the column decoder 14 based on the second address signal AD2.

Row decoder 13 decodes row address signal RA and selects one word line WL in memory cell array 11. Column decoder 14 decodes first and second column address signals CA1 and CA2, respectively.
Two data lines DL in the memory cell array 11 are simultaneously selected. Thereby, one selected word line WL
And two memory cells MC at the intersection of the selected two data lines DL are selected at the same time.

At the time of reading data, the I / O control circuit 15 responds to a read signal given from the processor 20 via the control line CL to read the data read from the two selected memory cells MC. It is applied to the first and second output data buses DBO1 and DBO2, respectively.
First and second output data buses DBO1, DBO2
The above data is input to the processor 20.

At the time of writing data, the processor 20
To the first and second input data buses DBI1, DB
Data is output on I2. The I / O control circuit 15
In response to a write signal applied from processor 20 via control line CL, data applied to first and second input data buses DBI1 and DBI2 is written to each of two selected memory cells MC.

In this manner, data can be read from or written to two memory cells MC on the same word line WL in the memory cell array 11 at the same time. The memory element 10 is actually provided with a plurality of memory cell arrays 11 corresponding to one byte of data. Therefore, in the memory element 10 of the present embodiment, data of 2 bytes can be read or written at the same time.

The instruction interpreted by the register 22 of the processor 20 is applied to one memory cell MC in the memory cell array 11 or a memory cell MC on a different word line WL.
Access (read or write data)
When the ALU 21 requires the address conversion circuit 12 of the memory element 10 via one address bus,
To the column decoder 14 and the I / O control circuit 15 from the processor 20 via the control line CL so that one address signal is supplied to the data bus and only one output data bus or one input data bus is supplied with data. Control.

In this embodiment, the row decoder 13 corresponds to a first selection circuit, the column decoder 14 corresponds to a second selection circuit, the row address signal RA corresponds to a first selection signal,
The first and second column address signals CA1 and CA2 are
Corresponds to the selection signal.

FIG. 2 is a block diagram showing an example of the address conversion circuit 12 in the memory element 10 of FIG. 1, and FIG.
3 is a signal waveform diagram showing an operation of the address conversion circuit 12 of FIG.

The address conversion circuit 12 has a first address signal AD1, a second address signal AD2, and a row signal RO.
And column signal CO. First address signal A
A row address signal RA and a first column address signal CA1 are multiplexed on D1, and a row address signal RA and a second column address signal CA2 are multiplexed on a second address signal AD2.
Are multiplexed. In this case, the second address signal A
The row address signal RA multiplexed on D2 is not used.

As shown in FIG. 3, first, address conversion circuit 12 outputs first address signal AD1 as row address signal RA in response to the fall of row signal RO. Next, the address conversion circuit 12 outputs the first address signal AD1 as the first column address signal CA1 every time the column signal CO falls, and outputs the second address signal A1.
D2 is output as the second column address signal CA2.

FIG. 4 is a block diagram showing another example of the address conversion circuit 12 in the memory element 10 of FIG.

The address conversion circuit 12 is supplied with an (N + M) -bit first address signal AD1 and an (N + M) -bit second address signal AD2. Address conversion circuit 12 outputs N bits of first address signal AD1 as row address signal RA, and outputs M bits as first column address signal CA1. The address conversion circuit 12 outputs M bits of the second address signal AD2 as a second column address signal CA2. The N bits of the second address signal AD2 are not used.

FIG. 5 is a circuit diagram showing a configuration of column decoder 14 and I / O control circuit 15 in memory element 10 of FIG.

As shown in FIG. 5, column decoder 14 includes a first decoder 141 and a second decoder 142. First decoder 141 decodes first column address signal CA1 provided from address conversion circuit 12, and outputs first switching signal SEL1. Second decoder 142 decodes second column address signal CA2 provided from address conversion circuit 12, and outputs second switching signal SEL2.

The I / O control circuit 15 includes switches SW1,
SW2, SW3, SW4, SW5, and SW6. The switches SW1 and SW2 are connected to the first and second input data buses DBI1 and DBI2, respectively. ON / OFF of the switches SW1 and SW2 is controlled by a control signal CT based on a read signal and a write signal.

The switch SW3 is connected between the switch SW1 and 2 ^M data lines DL1 to DLm in the memory cell array 11, and the switch SW4 is connected between the switch SW2 and the data lines DL1 to DLm. Also,
The switch SW5 is connected between the first output data bus DBO1 and the data lines DL1 to DLm.
6 is a second output data bus DBO2 and a data line DL1.
To DLm. Switches SW3, S
W5 is switched by a first switching signal SEL1 output from the first decoder 141. Switch S
W4,6 are the second output from the second decoder 142
Is switched by the switching signal SEL2.

When reading data, the switches SW1 and SW2 are turned off in response to the control signal CT. Further, the switches SW3 and SW are switched by the first switching signal SEL1.
5 is switched to any one of the data lines DL1 to DLm, and the switches SW4 and SW6 are switched to any one of the data lines DL1 to DLm by the second switching signal SEL2. Thereby, the selected two data lines are connected to the first and second output data buses DBO1 and DBO2, respectively.

When writing data, the switches SW1 and SW2 are turned on in response to the control signal CT. Further, the switches SW3 and SW are switched by the first switching signal SEL1.
5 is switched to any one of the data lines DL1 to DLm, and the switches SW4 and SW6 are switched to any one of the data lines DL1 to DLm by the second switching signal SEL2. Thereby, the selected two data lines are connected to the first and second input data buses DBI1 and DBI2, respectively.

FIG. 6 shows AL in processor 20 of FIG.
It is a block diagram showing an example of operation of U21.

In the example of FIG. 6, the ALU 21
2 and the first signal A1 and the second signal A2
Through the first address bus 2 as the first address signal AD1 and the second address signal AD2, respectively.
11 and the second address bus 212.

FIG. 7 shows AL in processor 20 of FIG.
It is a block diagram which shows the other example of operation | movement of U21.

In the example shown in FIG.
1 is provided with a 2k-bit first signal B1 and a 2k-bit second signal B2. Here, k is an arbitrary integer. The ALU 21 outputs the upper k bits of the first signal B1 and the upper k bits of the second signal B2 to the first address bus 211 as the first address signal AD1, and outputs the lower k bits of the first signal B1. The lower k bits of the second signal B2 are output to the second address bus 212 as a second address signal AD2.

In the first embodiment, the memory element 1
0, the processor 20 and the instruction memory 30 are formed on a common chip CH. However, only the instruction memory 30 may be formed on another chip.
0, the processor 20, and the instruction memory 30 may be formed on separate chips.

In the first embodiment, the memory element 10
Are configured to be able to simultaneously access two memory cells MC in the memory cell array 11, but an arbitrary number of three or more memory cells MC in the memory cell array 11
May be configured to be simultaneously accessible.

FIG. 8 is a block diagram showing a configuration of a data processing circuit according to the second embodiment of the present invention.

The data processing circuit shown in FIG.
a and a logic circuit 40. The memory cell element 10a and the logic circuit 40 are formed on a common chip CH.

8 differs from memory element 10 of FIG. 1 in that first and second input data buses DBI1 and DBI2 and first and second output data buses DBO1 and DBO2 are replaced. Are provided with first and second input / output data buses DB1 and DB2. The configuration of the other parts of the memory element 10a in FIG. 8 is the same as the configuration of the memory element 10 in FIG. The logic circuit 40 may be the processor 20 of FIG.
Other circuits may be used.

When data is read from or written to the memory element 10a, the logic circuit 40 sends the first data to the address conversion circuit 12 of the memory element 10 via the first and second address buses 211 and 212. And the second address signal AD2.

At the time of reading data, the logic circuit 4
0 gives a read signal to the I / O control circuit 15 of the memory element 10a via the control line CL. At the time of writing data, the processor 20 controls the I / O of the memory element 10a.
A write signal is supplied to the control circuit 15 via the control line CL, and the first and second input / output data buses DB1 and DB1 are provided.
Data is given to DB2.

In the memory element 10, the memory element 1 of FIG.
Similarly to the case of 0, one word line WL in the memory cell array 11 is selected and two data lines DL are simultaneously selected. Thereby, two memory cells MC at the intersection of the selected one word line WL and the selected two data lines DL are simultaneously selected.

At the time of reading data, data read from the selected two memory cells MC are respectively responsive to a read signal applied from logic circuit 40 through control line CL. It is provided to input / output data buses DB1 and DB2. Data on the first and second input / output data buses DB1 and DB2 is input to the logic circuit 40.

At the time of writing data, first and second input / output data buses DB 1 and DB 1 are provided in response to a write signal applied to logic circuit 40 through control line CL.
The data given to B2 is written to each of the two selected memory cells MC.

In this way, data can be read or written to two memory cells MC on the same word line WL in the memory cell array 11 at the same time. Actually, the memory element 10a is provided with a plurality of memory cell arrays 11 corresponding to one byte of data. Therefore, the memory element 10a of the present embodiment
In this case, two bytes of data can be read or written at the same time.

In this embodiment, when data is accessed only for one memory cell MC in the memory cell array 11 of the memory element 10a, only one input / output data bus DB1 or DB2 is effectively used. Column decoder 1 via the control line CL from the logic circuit 40.
4 and the I / O control circuit 15 may be controlled.

In the second embodiment, the memory element 10a and the logic circuit 40 are formed on a common chip CH. However, the memory element 10a and the logic circuit 40 may be formed on separate chips.

In the second embodiment, the memory element 10
a is configured to be able to simultaneously access two memory cells MC in the memory cell array 11, but an arbitrary number of three or more memory cells M in the memory cell array 11
C may be configured to be simultaneously accessible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a data processing circuit according to a first embodiment of the present invention.

FIG. 2 is a block diagram illustrating an example of an address conversion circuit in the memory device of FIG. 1;

FIG. 3 is a signal waveform diagram illustrating an operation of the address conversion circuit of FIG. 2;

FIG. 4 is a block diagram showing another example of the address conversion circuit in the memory device of FIG. 1;

FIG. 5 shows a column decoder and I in the memory device of FIG. 1;
FIG. 3 is a circuit diagram illustrating a configuration of an / O control circuit.

FIG. 6 is a block diagram illustrating an example of an operation of an ALU in the processor of FIG. 1;

FIG. 7 is a block diagram showing another example of the operation of the ALU in the processor of FIG. 1;

FIG. 8 is a block diagram illustrating a configuration of a data processing circuit according to a second embodiment of the present invention.

FIG. 9 is a block diagram showing a configuration of a conventional memory element.

FIG. 10 is a block diagram illustrating a configuration of a conventional processor.

[Explanation of symbols]

 10, 10a Memory element 11 Memory cell array 12 Address conversion circuit 13 Row decoder 14 Column decoder 15 I / O control circuit 20 Processor 21 ALU 22 Register 23 Program counter 30 Instruction memory 40 Logic circuit 211 First address bus 212 Second address Bus DBI1 First input data bus DBI2 Second input data bus DBO1 First output data bus DBO2 Second output data bus DB1 First input / output data bus DB2 Second input / output data Bus AD1 First address signal AD2 Second address signal RA Row address signal CA1 First column address signal CA2 Second column address signal WL Word line DL Data line MC Memory cell

Claims (13)

[Claims] 1. A plurality of data lines, a plurality of memory cells connected to the plurality of data lines, and a selection for simultaneously selecting at least two of the plurality of data lines based on at least two selection signals. And a circuit. 2. The semiconductor device according to claim 1, further comprising: at least two data buses; and a connection circuit that connects the at least two data lines selected by the selection circuit to the at least two data buses. 2. The memory element according to 1. 3. The memory device according to claim 1, wherein the selection circuit includes at least two decoders for decoding the at least two selection signals, respectively. 4. A plurality of word lines, a plurality of data lines provided to cross the plurality of word lines, and a plurality of data lines provided at intersections of the plurality of word lines and the plurality of data lines. A memory cell array including memory cells; at least two data buses; a first selection circuit for selecting one of the plurality of word lines of the memory cell array in response to a first selection signal; A second selection circuit for simultaneously selecting at least two of the plurality of data lines of the memory cell array in response to the second selection signal; and the at least two data lines selected by the second selection circuit.
A connection circuit for connecting one data line to each of the at least two data buses. 5. At least two address buses for receiving at least two address signals, and applying the first selection signal to the first selection circuit based on the at least two address signals on the at least two address buses. Giving and said at least two second
5. The memory device according to claim 4, further comprising: an address conversion circuit that supplies the selection signal of (a) to the second selection circuit. 6. The address conversion circuit according to claim 6, wherein each of the at least two address signals includes the first selection signal and the second selection signal in parallel, and the address conversion circuit includes one of the at least two address signals. The first selection signal included in the at least two address signals is supplied to the first selection circuit, and the second selection signal included in the at least two address signals is supplied to the second selection circuit. Item 6. The memory element according to item 5. 7. The first selection signal and the second selection signal are multiplexed on each of the at least two address signals in a time-division manner, and the address conversion circuit is configured to execute the at least two address signals at a first timing. The first selection signal multiplexed to one of the address signals is supplied to the first selection circuit, and the second selection signal multiplexed to the at least two address signals at a second timing. 6. The method according to claim 5, wherein a selection signal is supplied to said second selection circuit.
A memory element according to claim 1. 8. The apparatus according to claim 4, wherein said second selection circuit includes at least two decoders for respectively decoding said at least two second selection signals.
The memory element according to any one of the above. 9. The data bus according to claim 4, wherein said at least two data buses include at least two input data buses and at least two output data buses.
9. The memory element according to any one of 8. 10. The at least two data buses,
9. The memory device according to claim 4, comprising at least two input / output data buses. 11. A logic circuit having at least two address buses for simultaneously outputting at least two address signals. 12. The logic circuit according to claim 11, which outputs at least two address signals simultaneously, and is accessed by a selection signal based on said at least two address signals from said logic circuit.
A data processing circuit, comprising: the memory element according to any one of Claims 10 to 10. 13. The data processing circuit according to claim 12, wherein said logic circuit and said memory element are formed on a common chip.