JPH07114794A - Semiconductor memory device - Google Patents

Abstract

(57) [Abstract] [Purpose] Dynamically turn on / off the switch circuit for dividing the memory cell array according to the address.
By performing the control, the load capacitance of the bit line is reduced, the power consumption of the semiconductor memory device is reduced, and the read / write speed is increased. [Structure] A row decoder 100 which receives an address,
A memory cell array 102, 108 in which a memory cell array composed of memory cells connected to word lines which are output signal lines of the row decoder 100 is divided into two in units of rows.
And a switch circuit 103 for connecting or disconnecting bit lines of memory cells in series between memory cell arrays adjacent to each other, and a control circuit 107 for generating a control signal for the switch circuit 103. It is a storage device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device which speeds up reading in a computer system.

[0002]

2. Description of the Related Art In recent years, in the industrial fields of electronics, information, communication, etc., semiconductor memory devices have been used as means for storing programs or data in electronic equipment, computers and the like. A conventional semiconductor memory device will be described below with reference to the drawings.

FIG. 6 is a block diagram of a conventional semiconductor memory device. For example, an example of a conventional circuit configuration can be referred to in "Principles of CMOS VLSI Design" translated by Takashi Tomizawa, pages 306 to 312. Reference numeral 20 is a memory cell array whose basic unit is a storage means MC for holding data. Here, in order to simplify the explanation, it is assumed that the entire memory cell array configuration has a configuration in which the number of rows × the number of columns is 4 × 3, and the data width is 3 bits per word. Reference numeral 21 is a row decoder which decodes the address ADDR and generates a signal for word selection on the word lines WL0, WL1, WL2, WL3.
A read / write circuit 22 performs a read / write operation between the memory cell MC corresponding to one word and the data bus DATA under the control of the write enable signal WE and the read enable signal RE. It is assumed that the bit line precharge circuit / equalize circuit and the sense amplifier are included in the read / write circuit 22. The bit line connected to the memory means MC is B
0, XB0, B1, XB1, B2, XB2.

The operation of the semiconductor memory device configured as described above will be described below. Write operation when the write enable signal WE is "HIGH",
The read operation is performed when the read enable signal RE is "HIGH". Address ADDR to row decoder 21
It is assumed that the word line WL0 is activated by decoding at. When the read operation is performed, the data of one word held in the storage means MC connected to the word line WL0 is read to the bit lines B0, XB0, B1, XB1, B2, XB2, and the read / write circuit 22 It is driven to read data to the data bus DATA. On the other hand, when a write operation is performed, one word of write data is driven from the data bus DATA by the read / write circuit 22, and the bit lines B0, XB0, B1, XB1, B2, and XB.
One word of data is written to the storage means MC via 2.

[0005]

However, in the above configuration, the load capacity of the bit line increases due to the increase in the number of memory cells in the column direction forming the memory cell array as the storage capacity of the semiconductor memory device increases. To do. Therefore, there is a problem that the power consumption on the bit line increases and the access time for reading / writing data to / from the memory cell via the bit line increases, which impedes the speedup.

In view of the above problems, the present invention provides a semiconductor memory device capable of reducing the load capacitance of the bit line to reduce the power consumption and the reading speed.

[0007]

In order to solve the above-mentioned problems, a semiconductor memory device of the present invention has a memory cell connected to a row decoder which receives an address and a word line which is an output signal line of the row decoder. Between the memory cell arrays formed by dividing the memory cell array configured by the above into k (k ≧ 2) row units, and between the memory cell arrays adjacent to each other (between the i-th memory cell array and the i + 1-th cell, 1 ≦ i ≦ k−
In 1)), there are provided k−1 switch circuits for connecting or disconnecting the bit lines of the memory cells in series, and a control circuit for generating a control signal for the switch circuits.

Further, the arrangement of the k divided memory cell arrays is designed to be programmable corresponding to addresses.

Preferably, a part of the address is input to the control circuit.

[0010]

According to the present invention, the switch circuit for dividing the memory cell array is dynamically ON / OFF-controlled according to the address by the above-mentioned configuration, thereby reducing the load capacitance of the bit line and reducing the load of the semiconductor memory device. The power consumption and the reading speed can be increased.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor memory device according to an embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a semiconductor memory device. Here, a case where a memory cell array is divided into two as a circuit configuration will be described taking a random access memory (RAM) as an example.

Reference numeral 100 denotes a row decoder which receives an address ADDR, and 102 and 108, which are memory cell arrays each composed of a storage means for holding read / write data, which are respectively allocated based on an address space of a memory map. Storage means for reading / writing the memory cell arrays 102 and 108 is selected according to the output result of the row decoder 100. A switch circuit 103 divides the memory cell arrays 102 and 108.
The memory cell array is divided by connecting or disconnecting the bit lines inside the memory cell arrays 102 and 108 by the switch circuit 103. Reference numeral 104 is a precharge circuit / equalize circuit for precharging / equalizing the bit line, 105 is a sense amplifier for amplifying a signal change of the bit line, and 106 is between the output of the sense amplifier 105 and the data bus DATA. It is an input / output buffer for drive control of read / write data. A control circuit 107 receives a part of the address ADDR and generates a control signal CNT for the switch circuit 103. For example, if the memory space of the semiconductor memory device is divided into two by memory mapping, the address A
The control signal CNT can be generated using the MSB of DDR. Reference numeral 101 is an equalizing circuit for performing only the equalizing operation of the memory cell array 102 independently of the precharge circuit / equalizing circuit 104 when the memory cell arrays 102 and 108 are separated by the switch circuit 103. The equalizing circuit 101 need not be provided if the configuration of the control circuit 107 that controls the switch circuit 103 is changed and the precharge circuit / equalizing circuit 104 is used.

In the following description, the case where the equalizing circuit 101 is provided will be described. FIG. 2 is a block diagram of a semiconductor memory device corresponding to the block diagram of FIG. Here, a case where the memory cell array is divided into two will be described. The components 100 to 107 are the same as those in the configuration of FIG. Reference numerals 102 and 108 denote memory cell arrays having a storage unit MC for holding data as a basic unit.
Here, in order to simplify the explanation, it is assumed that the entire memory cell array configuration has a row number × column number of 4 × 3 and a data width of 1 word is 3 bits. 100 is the address ADD
R is decoded and word lines WL0, WL1, WL2, WL
3 is a row decoder for generating a signal for word selection. Here, word lines WL0, WL1, WL2, WL3
Addresses ADDR that are activated are 00, 01, 10 and 11. Reference numeral 103 denotes a switch circuit for dividing the memory cell arrays 102 and 108, which is composed of a switch element SW. The separated bit lines are B0, XB0, B1, XB1, respectively.
B2, XB2 and C0, XC0, C1, XC1, C2, X
This is indicated by C2. Reference numeral 104 is a precharge circuit / equalize circuit for precharging / equalizing the bit line, 105 is a sense amplifier for amplifying a signal change of the bit line, and 106 is between the output of the sense amplifier 105 and the data bus DATA. It is an input / output buffer for drive control of read / write data. 10
7 is a switch circuit 1 using a part of the address ADDR as an input
03 is a control circuit for generating the control signal CNT03. Here, by using the MSB of the address ADDR to generate the control signal CNT, the memory cell array 10
The case of dividing into 2 and 108 is shown and can be realized by an inverter.

FIG. 3 is a circuit diagram of the switch element SW which constitutes the switch circuit 103. The one-bit switch element SW corresponding to the bit lines B0 and C0 and the output signal CNT of the control circuit 107 is shown. Two types of switch elements are shown as examples. 302 is a CMOS switch, 301
Is an inverter for controlling the PMOS, 303 is an NM
It is an OS switch.

The operation of the semiconductor memory device of the present invention configured as above will be described below with reference to the timing chart of FIG.

The write enable signal WE is "HIG
In case of "H", write operation, read enable signal R
The read operation is performed when E is "HIGH". In the first cycle, data is written to the memory cell MC corresponding to the address 00 of the address ADDR, and the data is read in the next cycle. In these cycles, since the MSB of the address ADDR is 0, the control circuit 107
Output signal CNT of "NO" becomes "HIGH", and the switch circuit 103 is turned on. Therefore, each bit line, for example, B0 and C0, operates while being connected. This is called a normal access cycle. Address AD in the third cycle
Data is written in the memory cell MC corresponding to the address 10 of DR, and the data is read in the next cycle. In these cycles, since the MSB of the address ADDR is 1, the output signal CNT of the control circuit 107 becomes "LOW" and the switch circuit 103 is turned off. Therefore, each bit line, for example B0 and C0, operates in a disconnected state. This is called a high speed access cycle.

The operation of each cycle will be described below. In the normal access cycle, the precharge signal PRC is set to "HIG" to prepare for a write or read operation.
H ”, and the precharge circuit / equalize circuit 104
Thus, each bit line is equalized at the same time as precharge. The timing diagram shows B0, XB0, C0, and XC0. Since the address ADDR is the address 00, the word line WL0 is activated by the decoding by the row decoder 21. Write enable WE is "H"
During the "IGH" period, the data on the data bus DATA is written to the memory cell MC via the input / output buffer 106 and the bit line. The timing diagram shows the case where the "LOW" data is written to the memory cell. Read the data written in the cycle Address A
Since DDR is at address 00, the word line WL0 is activated by being decoded by the row decoder 21. While the read enable RE is "HIGH", the data held in the memory cell MC is taken out to the bit line, amplified by the sense amplifier 105, and read from the input / output buffer 106 to the data bus DATA. In the above writing / reading, since each bit line is connected by the switch circuit 103, the load capacitance of the bit line is affected by all the memory cells.

Next, in the high-speed access cycle in which each bit line operates in the state where it is disconnected by the switch circuit 103, the precharge signal PRC becomes "HIGH" to prepare for the write or read operation, and the precharge circuit / equalize circuit 104 is provided. Each bit line B0, X
B0, B1, XB1, B2 and XB2 are equalized at the same time as precharge. On the other hand, the equalizing circuit 101 causes the bit lines C0, XC0, C1, XC1, C2, X
C2 is only equalized. Since the address ADDR is the address 10, the word line WL2 is activated by decoding it by the row decoder 21. While the write enable WE is “HIGH”, the data on the data bus DATA is written to the memory cell MC via the input / output buffer 106 and the bit line. The timing diagram shows the case where "LOW" data is written in the memory cell. Read the data written in the next cycle. Since the address ADDR is the address 10, the word line WL2 is activated by decoding it by the row decoder 21. While the read enable RE is "HIGH", the data held in the memory cell MC is taken out to the bit line, amplified by the sense amplifier 105, and read from the input / output buffer 106 to the data bus DATA.

In the above writing / reading, since each bit line is disconnected by the switch circuit 103, the load capacitance of the bit line is affected only by half of all memory cells. Therefore, in the high-speed access cycle, low power consumption and high speed related to precharge, and low power consumption and high speed related to writing / reading can be achieved.

FIG. 5 shows a memory map of the semiconductor memory device. The memory cell array 102 of the semiconductor memory device corresponding to the normal access cycle is allocated to the normal access space. On the other hand, the high speed access space corresponds to the memory cell array 1 of the semiconductor memory device corresponding to the high speed access cycle.
Assign to 08. By dynamically turning on / off the switch circuit 103 in accordance with the address in this way, a high-performance memory system can be configured according to the access time for reading or writing the requested data.

As described above, according to the present embodiment, by providing the switch circuit for connecting or disconnecting the bit line between the memory cell arrays and the control circuit thereof, the load capacitance of the bit line is reduced and the semiconductor memory device. Power consumption and read / write speed can be reduced.
Further, in an actual layout, this switch circuit and its control circuit can be constructed so as to be negligibly small compared to the entire area of the semiconductor memory device, so that the performance can be improved with a simple configuration.

In the above description, the memory cell array is divided into two. Further, by providing a switch circuit between each of the plurality of memory cell arrays and providing a control circuit corresponding to the switch circuit, the switch circuit can be applied to the case of dividing into a large number as well as the case of dividing into two. The effects of lower power consumption and higher read / write speed are further increased. In the above description, RA
Similarly, the read-only memory (ROM) is also provided with a switch circuit and a control circuit for connecting or disconnecting the bit line between the memory cell arrays, so that the load capacity of the bit line can be reduced. Therefore, the power consumption of the semiconductor memory device can be reduced and the reading speed can be increased.

[0023]

As described above, according to the present invention, the memory cell array formed by dividing each word of the memory cell array into at least two corresponding to the address and the switch circuit for connecting or disconnecting the bit line. By providing a control circuit for generating the control signal and an equalize circuit connected to the bit line, load capacity of the bit line can be reduced, power consumption of the semiconductor memory device can be reduced, and reading speed can be increased. You can

[Brief description of drawings]

FIG. 1 is a block diagram of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a semiconductor memory device according to the same embodiment.

FIG. 3 is a circuit diagram of a switch element of the semiconductor memory device in the example.

FIG. 4 is a timing diagram of the semiconductor memory device in the embodiment.

FIG. 5 is a memory map diagram of the semiconductor memory device in the embodiment.

FIG. 6 is a configuration diagram of a conventional semiconductor memory device.

[Explanation of symbols]

 100 row decoder 101 equalizing circuit 102, 108 memory cell array 103 switch circuit 104 precharge circuit / equalizing circuit 105 sense amplifier 106 input / output buffer 107 control circuit 301 inverter 302 CMOS switch 303 NMOS switch

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location G11C 17/00 309 J

Claims (3)

[Claims] 1. A memory cell array composed of a row decoder which receives an address and a memory cell connected to a word line which is an output signal line of the row decoder is divided into k (k ≧ 2) row units. Between the memory cell array adjacent to each other (between the i-th memory cell array and the i + 1-th memory cell (1 ≦ i ≦ k−1)),
A semiconductor memory device comprising: k-1 switch circuits for connecting or disconnecting bit lines of memory cells in series; and a control circuit for generating a control signal for the switch circuits. 2. The semiconductor memory device according to claim 1, wherein k divided memory cell arrays are arranged in a programmable manner corresponding to addresses. 3. The semiconductor memory device according to claim 1, wherein a part of the address is input to a control circuit.