JPH11183925A - Liquid crystal device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal device in which no disconnection occurs even if signal lines composing a closed circuit is made to run in a lower layer side of a sealing material containing a gap material as a seal lower wiring. SOLUTION: On a lower layer side of a seal material GS on the side of an active matrix substrate AM, signal wiring (a lower layer side wiring 3b, an upper layer side wiring 6b) are positively made to run therethrough, and this area is made as seal material forming area GA. Here, grooves 110 are formed beforehand in an area corresponding to an area for forming the lower layer side wiring 3b and the upper layer side wiring 6b, and the upsurges of film thickness of the wiring are absorbed in the grooves for offsetting them, and the whole seal material forming area GA is flattened. As a result, stress applied from the gap material G is distributed, and disconnection is prevented from occurring in the lower layer side of the seal material GS.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal device using an active matrix substrate. More specifically, the present invention relates to a structure of a seal material forming region serving as a base in a region where a seal material containing a gap material for bonding an active matrix substrate and a counter substrate is formed.

[0002]

2. Description of the Related Art In an active matrix substrate used for a liquid crystal device, a plurality of scanning lines and a plurality of data lines are formed on a substrate such as a quartz substrate or a non-alkaline glass in a direction intersecting with each other. A plurality of pixels are arranged in a matrix. The area where these pixels are arranged in a matrix is the screen display area. The active matrix substrate and the opposing substrate are bonded to each other with a predetermined cell gap separated by a gap material-containing sealing material formed outside the screen display area. Flatness as a seal material forming region is required for a portion to be a base region of the seal material.

Therefore, conventionally, as shown in FIG. 17, in the active matrix substrate AM, outside the screen display area 21, a portion where the data lines X are drawn from the screen display area 21 to the data line driving circuit 22, and a screen. Since a large number of scanning lines Y from the display area 21 to the scanning line driving circuit 23 are arranged in parallel and form a substantially flat area, this area can be used as the sealing material forming area GA. is there. In this case, for example, the lead-out portion of the data line X and the lead-out portion of the scanning line Y may be used as they are as the under-seal wiring constituting the sealing material forming area GA.
As shown in FIGS. 3A and 3B, for example, the scanning line Y is a lower wiring 3b made of a polysilicon film, and the lower wiring 3b is connected to the upper wiring made of an aluminum film via a first interlayer insulating film 4. By forming the wiring under the seal in a two-layer structure by overlapping the wiring 6b, the sealing material forming area GA is made one step higher than the surroundings, and each wiring is arranged with a wiring adjacent thereto with a slight gap therebetween. There is. With this configuration, as shown in FIG. 19B, when the active matrix substrate AM and the opposing substrate OP are bonded together with the sealing material GS containing the gap material G, the active material is included in the sealing material GS on each wiring. Since the gap material G that has been placed thereon can be used, the cell gap between the active matrix substrate AM and the opposing substrate OP can be controlled.

[0004]

As shown in FIG. 19B, in the gap control structure utilizing the fact that the portion corresponding to the wiring under the seal protrudes one step higher when viewed from the surroundings,
Since the stress from the gap material G is concentrated on the wiring under the seal, cracks tend to occur in the wiring under the seal. Nevertheless, if the wiring under the seal is a dummy wiring that does not constitute a closed circuit to the last, even if a disconnection occurs, there is no problem in displaying.

However, when a wire such as a data line X or a scanning line Y, which itself constitutes a closed circuit as a signal line, is used as the under-seal wire, if the above-described disconnection occurs, the display is displayed. There is a problem that line defects occur.
Such a problem occurs even when the under-sealed wiring is formed of a single layer of wiring. However, when the under-sealed wiring has a two-layer structure, the portion corresponding to the under-sealed wiring protrudes higher by that amount, so that disconnection may occur. It tends to occur.

[0006] In view of the above problems, an object of the present invention is to provide:
It is an object of the present invention to provide a liquid crystal device in which a disconnection does not occur even when a signal line forming a closed circuit is used as a lower wiring of a seal and passes through a lower layer of a seal material containing a gap material.

[0007]

In order to solve the above-mentioned problems, the present invention provides a liquid crystal display device in which liquid crystal is sealed between a first substrate and a second substrate, and a pixel electrode formed in a matrix on the first substrate. A pixel circuit having: a driving circuit portion formed around the pixel region; and a first wiring formed between the pixel region and the driving circuit portion.
The substrate is a liquid crystal device that is bonded to the wiring formed on the first substrate with a sealing material containing a gap material, and the first wiring and the sealing material are formed on the first substrate. And a first insulating film having a concave portion is arranged in a region where the first wiring overlaps with the first insulating film, and the first wiring is disposed on the concave portion of the first insulating film. According to the present invention, in the formation region of the sealing material, since the wiring is formed in the concave portion of the insulating film, the bulge corresponding to the film thickness of the wiring is relaxed and absorbed by the depth of the groove, It is possible to make the uppermost layer of the sealing material forming region of the first substrate flat. For this reason, a sealing material containing a gap material is applied to the surface of the sealing material forming region, and the stress from this sealing material is dispersed and applied to the sealing material forming region, so that it concentrates on the wiring formed under the sealing material. Can be prevented. Therefore, it is not necessary to use a flattening technique with low manufacturing efficiency.

[0008] In the present invention, the first substrate may be arranged in the concave portion in a region overlapping with the sealing material.
A wiring, a second insulating film disposed on the first wiring, and a second wiring disposed on the second insulating film so as to overlap the first wiring.

According to the present invention, the second insulating film has a concave portion,
The second wiring is disposed on a concave portion of the second insulating film. According to such a configuration, the first and second wirings are formed on the insulating film having the concave portions, respectively, and thus can be planarized.

The present invention is characterized in that the first wiring and the second wiring overlapping each other via the interlayer insulating film are connected via a contact hole formed in the interlayer insulating film. . As described above, by connecting the first wiring and the second wiring in the seal formation region,
Since the wiring resistance can be reduced and a redundant wiring structure is provided, a signal can be transmitted even if one of the first wiring and the second wiring is disconnected.

According to the present invention, a liquid crystal is sealed between a first substrate and a second substrate, and a plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines are provided on the first substrate, A transistor connected to a scan line and a data line, a pixel region including a pixel electrode connected to the transistor, a driving circuit portion formed around the pixel region, and a portion between the pixel region and the driving circuit portion. And a first wiring formed on the first substrate and the second substrate are bonded to each other on the wiring formed on the first substrate by a sealing material containing a gap material. A first insulating film having a concave portion in a region where the first wiring and the sealing material overlap with each other on the first substrate, wherein the first wiring is formed of the first insulating film of the first insulating film; It is characterized by being arranged on a concave portion. According to the present invention, in the formation region of the sealing material, the wiring is formed in the concave portion of the insulating film, so that the bulge corresponding to the thickness of the wiring is relaxed and absorbed by the depth of the groove. It is possible to make the uppermost layer of the sealing material forming region of the substrate flat. For this reason, a sealing material containing a gap material is applied to the surface of the sealing material forming region, and the stress from this sealing material is dispersed and applied to the sealing material forming region, so that the stress is concentrated on the wiring formed under the sealing material. Can be prevented.

According to the present invention, the first wiring is a wiring formed simultaneously with one of the data line and the scanning line, and the second wiring is a wiring of the data line and the scanning line. The wiring is formed simultaneously with the other signal line. According to such a configuration, the number of manufacturing steps can be reduced by forming the first wiring and the second wiring simultaneously with the data line or the scanning line.

According to the present invention, the driving circuit includes a data line driving circuit for supplying an image signal to each of the plurality of data lines, and a scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines. And a portion where the data line is drawn from the screen display area to the data line driving circuit and a portion where the scanning line is drawn from the screen display area to the scanning line driving circuit constitute the under-seal wiring. It is characterized by doing. In the case of such a configuration, each of the portion for leading the data line from the pixel region to the data line driving circuit and the portion for leading the scanning line from the pixel region to the scanning line driving circuit is provided with the seal. By forming in the formation area, the seal formation area can be effectively used.

According to the present invention, a liquid crystal is sealed between a first substrate and a second substrate, and a plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines are provided on the first substrate, A transistor connected to a scanning line and a data line; a pixel region including a pixel electrode connected to the transistor; a driving circuit portion formed around the pixel region; And a first wiring formed therebetween.
The method for manufacturing a liquid crystal device, wherein the first substrate and the second substrate are bonded to each other on the wiring formed on the first substrate by a sealing material containing a gap material, Forming a first insulating film on the substrate;
Forming a concave portion in the insulating film; forming a first wiring in the concave portion of the first insulating film; and forming one of the scanning line and the source line using the same material as the first wiring. And a process. According to the structure of the present invention, one of the scanning line and the data line and the signal line can be formed at the same time, and the signal line is formed in the concave portion of the insulating film. It is possible.

[0015]

Embodiments of the present invention will be described with reference to the drawings.

(Overall Configuration of Liquid Crystal Device) FIGS. 1 and 2
1A is a plan view of a liquid crystal device to which the present invention is applied, and FIG.

As shown in these figures, the liquid crystal device LP
Is a rectangular screen display area 21 in which pixels to be described later are formed in a matrix, a data line driving circuit 22 formed in an area outside the screen display area 21, and a screen display area 2.
The active matrix substrate AM includes a pair of scanning line drive circuits 23 formed on both sides of the active matrix substrate 1 and an opposing substrate OP disposed opposite to the active matrix substrate AM.

The opposing substrate OP and the active matrix substrate AM are formed along the outer peripheral edge of the screen display area 21 in an area corresponding to between the screen display area 21 and the data line driving circuit 22 and the scanning line driving circuit 23. The sealing material GS containing the gap material is bonded with a predetermined cell gap therebetween, and the liquid crystal LC is sealed in an inner region of the sealing material GS. Here, the sealing material GS
Is partially interrupted, the liquid crystal injection port 241 is formed by the interrupted portion. For this reason, in the liquid crystal device LP, after the opposing substrate OP and the active matrix substrate AM are bonded to each other, if the inside region of the sealing material GS is set to a reduced pressure state, the liquid crystal LC can be injected from the liquid crystal injection port 241 under reduced pressure. After filling the
1 is closed by a sealant 242. As the sealing material GS, an epoxy resin or various ultraviolet curable resins can be used, and as the gap material to be mixed therein, a cylindrical or spherical glass fiber having a diameter of about 2 μm to about 6 μm can be used.

Here, since the opposing substrate OP is smaller than the active matrix substrate AM, the peripheral portion of the active matrix substrate AM is bonded so as to protrude from the outer peripheral edge of the opposing substrate OP. Therefore, the sealing material GS is
When viewed from the counter substrate OP, it is formed along the outer peripheral edge of the substrate, but when viewed from the active matrix substrate AM, it is formed considerably inside from the outer peripheral edge of the substrate. Therefore, the scanning line driving circuit 23 and the data line driving circuit 22 are located outside the opposing substrate OP, and do not oppose the opposing substrate OP.

In the active matrix substrate AM, a metal film such as an aluminum film, a metal silicide film, an ITO film, etc., to which a constant power supply, a modulated image signal, various signals, etc. are inputted, is provided on a side portion on the side of the data line driving circuit 22. A large number of external input / output terminals 25 made of the conductive film are formed. From these external input / output terminals 25, the scanning line driving circuit 23
A plurality of signal lines 28 made of a low-resistance metal film such as an aluminum film or a metal silicide film for driving the data line driving circuit 22 are respectively routed.

The opposing substrate OP includes an opposing electrode 51 made of an ITO film opposed to a pixel electrode of each pixel formed on the side of the active matrix substrate AM with the liquid crystal LC interposed therebetween and surrounding each pixel. A black matrix BM1 made of the formed light shielding film is formed. Also,
The light shielding film BM2 for parting the display screen is also formed on the counter substrate OP along the inner peripheral edge of the sealant GS.

On the outer peripheral portion of the active matrix substrate AM, the screen display area 21 of the formation area of the sealing material GS is formed.
The upper and lower conductive terminals 33 are formed in a region corresponding to the corners of the above, and the upper and lower conductive terminals 33 are formed on the upper and lower conductive terminals 33 by the upper and lower conductive members 31 formed of silver dots balls sandwiched between the active matrix substrate AM and the opposing substrate OP. From the common potential line 32 of the matrix substrate AM to the counter electrode 5 of the counter substrate OP
1 is supplied with a common potential.

(Configuration of Active Matrix Substrate and Screen Display Area) FIG. 3 is a block diagram of an active matrix substrate with a built-in drive circuit used in the liquid crystal device of the present embodiment.

In FIG. 3, a dashed-dotted line L1 indicates a position defining the screen display area 21, and a dashed-dotted line L2 indicates a formation area of the sealing material GS.

In the active matrix substrate AM, a plurality of pixels PX are formed in a matrix by a plurality of scanning lines Y and a plurality of data lines X on a transparent substrate 10 such as a quartz substrate or non-alkali glass. Any pixel P
As shown in FIG. 4, X is also formed with a pixel switching thin film transistor 60 (hereinafter, referred to as TFT) connected to the scanning line Y and the data line X, as shown in FIG. 4. The basic structure of this TFT 60 is the same as the structure of a conventional TFT, and will be described in detail in the manufacturing method.
The pixel electrode 9a forms a liquid crystal cell with the liquid crystal LC interposed between the counter electrode 51 of P and the P counter electrode 51. Note that, for the liquid crystal cell, the storage capacitor C is utilized by using the gate line and the capacitor line Z in the preceding stage.
An AP is configured. TFT6 for pixel switching
0 denotes a gate electrode which is a part of the scanning line Y and the data line X
And a second contact penetrating the first interlayer insulating film and the second interlayer insulating film, the source region being electrically connected to the source electrode which is a part of the first interlayer insulating film via the first contact hole 5a of the first interlayer insulating film. A drain region to which a pixel electrode 9a made of an ITO film is electrically connected via a hole 8a.

(Configuration of Driving Circuit) Referring again to FIG. 3, the data line driving circuit 22 provided on the active matrix substrate AM has an X-side shift register circuit and a buffer circuit. Between the screen display area 21 and T, which operates based on a signal output from the X-side shift register circuit via the buffer circuit.
Sampling circuit 2 with FT (analog switch)
24, and 6 corresponding to each image signal developed into 6 phases.
The image signal lines VID1 to VID6 are configured.
Note that the data line driving circuit 22, the image signal lines VID1 to VID
The ID6 and the sampling circuit 224 are used to supply a signal from the X-side shift register circuit to the sampling circuit 224, and a sampling drive signal line 64 for connecting the image signal lines VID1 to VID6 and the sampling circuit 224. The circuit is connected to the wiring 65. For this reason, the sampling circuit 22
4 indicates that each TFT operates based on a signal output from the data line driving circuit 22, and the image signal lines VID1 to VID6
Can be taken into the data line X at a predetermined timing and supplied to each pixel PX.

The scanning line driving circuit 23 formed on the active matrix substrate AM also includes a Y-side shift register circuit and a buffer circuit.

In the active matrix substrate AM of the present embodiment, a region overlapping with the light shielding film BM2 for parting the display screen on the side opposite to the side where the data line driving circuit 22 is formed with respect to the screen display region 21. A reset drive circuit 80 for appropriately performing an inversion drive method in which the polarity of an image signal is inverted for each row is also configured.

(Reset Drive Circuit) FIG. 5 is a timing chart showing a reset (precharge) operation performed in the liquid crystal device shown in FIG.

In the liquid crystal device LP using the active matrix substrate AM, for example, when an inversion driving method in which the polarity of an image signal is inverted for each row is performed, as shown in FIG. The image signal supplied to the TFT 60 is written into the liquid crystal cell via the TFT 60 while the polarity is inverted every horizontal scanning period. Therefore, the potential of the pixel electrode of the pixel switching TFT is as shown in FIG. It changes as shown in B). That is, since the polarity of the image signal is inverted every horizontal scanning period, the potential of the pixel electrode greatly changes, and charging and discharging from the data line X to the image signal lines VID1 to VID6 are repeated accordingly. Such a charge / discharge has a relatively low sampling rate in the display based on the NTSC standard, so that it does not easily affect the quality of the display.
When the display is performed by the TSC, the sampling rate is high, which causes noise or the like in the display.

Therefore, in the present embodiment, as shown in FIG.
In a region opposite to the data line driving circuit 22 with respect to the screen display region 21, a reset potential is applied to each of the data lines X prior to the supply of an image signal to the data lines X using a horizontal retrace interval or the like. , A reset signal supply switch circuit 83,
In addition, a reset drive circuit 80 including a reset drive signal line 86 for driving the reset potential supply / discharge switch circuit 83 is formed, and charging / discharging from the data line X is almost completed at the reset potential. According to this configuration, as shown in FIG. 5C, a reset potential having a predetermined polarity is applied from the reset signal lines 81 and 82 immediately before an image signal is supplied to the data line X. For this reason, the charge and discharge from the data line X can be almost completed before the image signal is supplied to the data line X, so that the temporal change in the potential of the pixel electrode is small as shown in FIG. The charge / discharge amount from the data line X can be suppressed. Therefore, the image signal lines VID1 to VID
Since the fluctuation of the potential of D6 can be prevented, it is possible to suppress generation of noise in display.

Further, in the active matrix substrate AM of the present embodiment, a constant potential line 84 is formed in a region outside the reset signal lines 81 and 82 in parallel with the reset signal lines 81 and 82. Signal lines 81, 8
2, a capacitor 85 is formed. The constant potential line 84 is set to, for example, the same potential as the potential of the counter electrode 51 of the counter substrate OP bonded to the active matrix substrate AM, like the capacitance wiring Z and the like, and this potential is shown in FIGS. ) Corresponds to an intermediate potential of the amplitude of the image signal and the reset signal. As described above, in the active matrix substrate AM of the present embodiment, the reset signal lines 81 and 82
Since the capacitor 85 is formed between the reset signal lines 81 and 82, the time constant of the reset signal lines 81 and 82 is large.
Therefore, when a reset potential is applied to each data line X, it is possible to more reliably prevent a signal from flowing to another data line X via the reset signal lines 81 and 82. Therefore, even in a liquid crystal device of a type in which a reset potential is applied to each of the data lines X prior to the supply of an image signal to the data lines X, horizontal crosstalk or the like due to signal wraparound does not appear, and display is not performed. The quality can be improved.

(Structure of Sealing Material Forming Area) In the active matrix substrate AM having such a structure, the sealing material GS is formed in a region indicated by a dashed line L2 in FIG. In forming the sealing material GS, in this embodiment, FIG.
As will be described in detail with reference to FIG. 13, a signal line constituting a closed circuit for performing a display operation of the liquid crystal device LP is passed through a lower layer region of the sealing material GS on the active matrix substrate AM side. Thereby, this region is substantially flattened as a sealing material forming region.

FIG. 6 is an enlarged view of a corner portion (circular region L11 in FIG. 1) of the liquid crystal device LP. FIG. 7 is an explanatory diagram of a sealing material forming region around the data line driving circuit shown in FIG. FIGS. 8A and 8B respectively show B-
It is sectional drawing in the B 'line, and sectional drawing in the CC' line. FIG. 9 is a diagram showing the periphery of the scanning line driving circuit shown in FIG.
It is explanatory drawing of the sealing material formation area | region of. FIG. 10 (A),
(B) is a cross-sectional view taken along line BB 'of FIG. 9,
It is sectional drawing in the CC 'line.

First, as shown in FIG. 6, in the active matrix substrate AM of the present embodiment, the data line driving circuit 22 and the screen display area 21 of the area outside the screen display area 21 are arranged.
Between the sampling circuit 224 and the image signal line VI.
A sealing material GS containing a gap material is formed in a region corresponding to D1 to VID6. For this reason, a plurality of columns of sampling drive signal lines 64 (data lines from the screen display area 21 to the data line drive circuit 22) connecting and connecting the data line drive circuit 22 and the sampling circuit 224 are provided in the lower layer side region of the sealing material GS. X is connected to the image signal lines VID1 to VID6 and the sampling circuit 224 by the image signal sampling wiring 65 (the part where the data lines X are drawn from the screen display area 21 to the data line driving circuit 22). Are passed in parallel as wiring under the region where the is formed.

As shown in FIG. 7, the periphery of the data line driving circuit 22 is enlarged.
4 and the reset signal line 81 and the reset drive signal line 8 of the reset drive circuit 80 at equal intervals on both sides of the region where the image signal sampling wiring 65 is formed.
The reset signal line 81 and the reset drive signal line 86 also pass through the lower layer side area of the seal material GS as a seal lower wiring.

Each pixel PX formed in a matrix is
Of the pixels at the outer edge, the characteristics are not stable,
The dummy pixel PX 'not used for display overlaps with the light blocking film BM2 for parting.

Here, the sampling signal drive signal line 6
4. As shown in FIGS. 7 and 8A, the image signal sampling wiring 65, the reset signal line 81, and the reset driving signal line 86 have a portion corresponding to the under-seal wiring passing under the seal material GS. , An upper layer wiring 6b formed of an aluminum film (conductive film) formed simultaneously with the data line X. The upper layer wiring 6b is formed of a lower layer formed of a polysilicon film (conductive film) formed simultaneously with the scanning line Y. It overlaps with the side wiring 3b via the first interlayer insulating film 4. The lower wiring 3b and the upper wiring 6b are electrically connected at a plurality of locations via a plurality of contact holes 5b of the first interlayer insulating film 4 to form a redundant wiring structure.

As described above, the lower layer wiring 3b and the upper layer wiring 6b have a two-layer structure and are arranged with a slight gap between adjacent wirings. In this embodiment, as shown in FIG. 8 (B), a section taken along the line CC ′ in FIG. 7 is used as the sealing material forming area GA. (Lower layer wiring 3b and upper layer wiring 6
In a region overlapping with b), a plurality of rows of grooves 110 recessed on the substrate surface
(Recess). Therefore, even if the under-seal wiring (the lower-layer wiring 3b and the upper-layer wiring 6b) is formed in a region corresponding to the lower layer side of the sealing material GS, the swell corresponding to the film thickness of the under-seal wiring does not exceed the depth of the groove 110. Therefore, the outermost layer (the surface of the second interlayer insulating film 7) of the sealing material forming area GA is flat. Therefore, the sealing material G containing the gap material G on the surface of the sealing material forming area GA.
Even if S is applied and the active matrix substrate AM and the opposing substrate OP are bonded by the sealing material GS, the stress from the gap material G is dispersed and applied to the sealing material forming area GA. It does not concentrate on the wiring 3b and the upper wiring 6b). Therefore, the signal lines (sampling signal drive signal lines 6
4. Even if the image signal sampling wiring 65, the reset signal line 81, and the reset drive signal line 86) pass through the lower layer of the sealing material GS containing the gap material G, no disconnection occurs, so that no display line defect or the like occurs.

In the portion corresponding to the wiring under the seal, the wiring has a two-layer structure, so that the electric resistance is small and disconnection occurs in one of the lower wiring 3b and the upper wiring 6b. In this case, signals and potentials can be transmitted and supplied, and there is no problem in displaying.

As shown in FIG. 6, between the scanning line driving circuit 23 and the screen display area 21, a sealing material is provided in an area corresponding to a portion where the scanning line Y is drawn from the screen display area 21 to the scanning line driving circuit 23. GS is formed. Therefore, in the lower layer side region of the sealing material GS, the scanning line Y passes in parallel as a sealing lower wiring.

As shown in an enlarged view of the periphery of the data line driving circuit 22 in FIG. 9, a reset signal line 82 of a reset driving circuit 80 passes through a position adjacent to the scanning line Y. 82 also passes through the lower layer side area of the sealing material GS as a wiring under the seal.

Here, a portion of the scanning line Y corresponding to the under-seal wiring passing under the sealing material GS is made of a polysilicon film (conductive film) as shown in FIGS. 9 and 10A. The lower-layer wiring 3b is provided with an upper-layer wiring 6b made of an aluminum film (conductive film) formed simultaneously with the data line X.
Overlap through. In the scanning line Y, the lower wiring 3b and the upper wiring 6b are electrically connected at a plurality of locations via a plurality of contact holes 5b of the first interlayer insulating film 4 to form a redundant wiring structure. .

On the other hand, as shown in FIGS. 9 and 10A, the reset signal line 82 has a portion corresponding to an under-seal wiring passing under the seal material GS, as shown in FIGS.
Is formed as an upper layer wiring 6b made of an aluminum film (conductive film) formed at the same time as the above.
The lower wiring 3 b made of a polysilicon film (conductive film) formed at the same time as the scanning line Y overlaps with the first interlayer insulating film 4 interposed therebetween. Also in the reset signal line 82, the lower wiring 3b and the upper wiring 6b are electrically connected at a plurality of locations via a plurality of contact holes 5b of the first interlayer insulating film 4 to form a redundant wiring structure. ing.

As described above, the lower layer wiring 3b and the upper layer wiring 6b also have a two-layer structure around the scanning line driving circuit 23 and are arranged with a slight gap between adjacent wirings. Is used as the sealing material forming area GA to which the sealing material GS is to be applied. In the present embodiment, as shown in FIG. In the region GA, a plurality of rows of grooves 110 (recesses) that are recessed on the substrate surface are formed in a region overlapping with each of the under-seal wirings (the lower wiring 3b and the upper wiring 6b). Therefore, the under-seal wiring (the lower-layer wiring 3b and the upper-layer wiring 6b) is provided in a region corresponding to the lower layer of the sealing material GS.
Is formed, the bulge corresponding to the thickness of the wiring under the seal is reduced and absorbed by the depth of the groove 110, so that the outermost layer (the surface of the second interlayer insulating film 7) of the seal material forming region GA is formed. It is flat. For this reason, even if the sealing material GS containing the gap material G is applied to the surface of the sealing material forming area GA, and the active matrix substrate AM and the opposing substrate OP are bonded by the sealing material GS, the stress from the gap material G may be increased. Are added to the sealing material forming area GA in a dispersed manner, so that they are not concentrated on the wiring under the seal. Therefore, even if the signal lines (scanning line Y and reset signal line 82) constituting the closed circuit pass through the lower layer side of the sealing material GS containing the gap material G, no disconnection occurs, so that a display line defect or the like occurs. do not do.

In the portion corresponding to the wiring under the seal, the wiring has a two-layer structure, so that the electric resistance is small and disconnection occurs in one of the lower wiring 3b and the upper wiring 6b. In this case, signals and potentials can be transmitted and supplied, and there is no problem in displaying.

FIG. 11 is an enlarged view of a corner portion (circular region L12 in FIG. 1) of the liquid crystal device LP. FIG.
FIG. 12 is an explanatory diagram of a seal material forming region around a reset circuit shown in FIG. 11. 13A, 13B, and 13C are a cross-sectional view taken along a line DD ′, a cross-sectional view taken along a line EE ′, and a cross-sectional view taken along a line FF ′ in FIG. 12, respectively.

As shown in FIG. 11, the scanning line driving circuit 23
Is formed between the reset signal lines 81 and 82 constituting the reset driving circuit 80 and the constant potential line 84 in a region on the side opposite to the side of the data line driving circuit 22 in the periphery of FIG. As described with reference to FIG. 12, the upper layer wiring 6b and the lower layer wiring 3b as electrodes constituting the capacitor 85 pass through the lower layer region of the material GS as the sealing lower wiring.

As shown in FIGS. 12 and 13 (A) and (B), reset signal lines 81 and 82 and constant potential line 84
Are wirings made of a polysilicon film formed simultaneously with the scanning lines Y. Of the two wirings forming the capacitor 85, the lower wiring 3b is only a constant potential line 84.
Are extended portions projecting toward the reset signal lines 81 and 82 from the reset signal lines 81 and 82 and the scanning lines Y.
And an electrode layer made of a polysilicon film formed at the same time. On the other hand, the upper layer side wiring 6b is an electrode layer made of an aluminum layer formed simultaneously with the data line X, and the contact hole 5
b and are electrically connected. Here, the reason why the electrode layer electrically connected to the reset signal lines 81 and 82 via the contact holes 5b is used as the upper layer side wiring 6b is because the reset signal lines 81 and 82 are at the same layer position. This is because the upper wiring 6b electrically connected to the reset signal line 82 extends toward the constant potential line 84 without being electrically connected to the reset signal line 81. In this embodiment, the capacitor 85 includes the first interlayer insulating film 4 as a dielectric film at a portion where the upper layer wiring 6b and the lower layer wiring 3b overlap.

In this region, utilizing the fact that the lower wiring 3b and the upper wiring 6b constituting the capacitor 85 have a two-layer structure and are arranged with a slight gap between adjacent wirings,
The sealing material forming area GA on which the sealing material GS is to be applied.
However, in this embodiment, FIG.
As shown in the cross section taken along line FF ′, a plurality of rows recessed on the surface of the substrate 10 in a region of the surface of the substrate 10 overlapping with each of the under-seal wirings (the lower-layer wiring 3b and the upper-layer wiring 6b) in the sealing material forming area GA. Grooves 110 are formed. Therefore, even if the under-seal wiring (the lower-layer wiring 3b and the upper-layer wiring 6b) is formed in a region corresponding to the lower layer of the sealing material GS, the bulge corresponding to the film thickness of the under-seal wiring is formed in the groove 1.
Since it is relaxed and absorbed at a depth of 10, the outermost layer (the surface of the second interlayer insulating film 7) of the sealing material forming area GA is flat. Therefore, a sealing material GS containing a gap material G is applied to the surface of the sealing material forming area GA, and the sealing material GS
The active matrix substrate AM and the opposing substrate OP
Even if they are bonded to each other, the stress from the gap material G is dispersed and applied to the sealing material forming area GA, so that the stress is not concentrated on the wiring under the seal. Therefore, the signal lines (the lower layer wiring 3b and the upper layer wiring 6b forming the capacitor 85) forming the closed circuit are sealed with the sealing material GS containing the gap material G.
Since no disconnection occurs even through the lower layer side, a predetermined capacity can be reliably obtained. In addition, since the sealing material forming area GA having substantially the same height is formed in any of the four sides of the screen display area 21, the cell gap can be accurately controlled.

Moreover, since the capacitor 85 is formed in the formation region of the sealing material GS, which was a dead space in the related art, no matter how large the capacity of the capacitor 85 is, the size of the active matrix substrate AM is large. It is not necessary to reduce the size of the screen display area 21.

In any configuration of the active matrix substrate AM, in a configuration in which a solid aluminum layer or the like is used as the sealing material forming area GA, the photo-curing sealing material GS is irradiated with ultraviolet rays to be photo-cured. In this case, light must be irradiated from the opposing substrate OP, and there is a restriction that a quartz substrate or the like having a very high light transmittance must be used as the opposing substrate OP. Since the sealing material GS is formed in the wiring forming region, even if light is irradiated from the side of the active matrix substrate AM, the light reaches the sealing material GS through the gap between the wirings and can be cured. Therefore, the requirement for the light transmittance of the opposing substrate OP can be relaxed, and the opposing substrate OP has an advantage that an inexpensive glass substrate such as neoceram can be used. Further, in the case of the thermosetting sealing material GS, it is unavoidable that the substrate is distorted due to heat at the time of curing. However, according to the present invention, the heating which causes such distortion is caused. There is an advantage that a photocurable sealing material GS that does not require the use of a sealing material can be used.

In this embodiment, as shown in FIGS. 3 and 6, a sampling circuit 224 and an image signal line VI are provided between the data line driving circuit 22 and the screen display area 21.
The sealing material GS is formed in an area corresponding to the area between D1 and VID6, and the sampling circuit 224 is located inside the sealing material GS. Therefore, in view of the structure shown in FIG. 17, the formation area of the data line drive circuit 22 can be expanded in the portion outside the seal member 80 by the amount of the sampling circuit 224 formed in the portion inside the seal member GS. Therefore, according to the present embodiment, for the purpose of enhancing the display quality of the liquid crystal display panel, the data line drive circuit 22 has an increased on-current (operating speed) due to the expansion of the channel width of the TFT constituting the data line drive circuit 22. Improvement), or introduction of a large-scale circuit. Conversely, since the peripheral portion of the active matrix substrate can be reduced, a liquid crystal display panel having a narrower peripheral portion while having a display area of the same size can be configured. Further, if the entire data line driving circuit 22 is formed inside the sealing material GS, the liquid crystal may be deteriorated due to the influence of the potential of the DC component applied thereto. In this embodiment, only the sampling circuit 224 is used. Is arranged inside the sealing material GS, so that the liquid crystal is not deteriorated. Moreover, since the sampling circuit 224 is covered with the light shielding film BM2 for parting the display screen, the display quality is not degraded even if the alignment of the liquid crystal is disturbed.

(Method of Manufacturing Active Matrix Substrate)
When the sealing material forming area GA is configured in this manner, the manufacturing process of the pixel switching TFT 60, the scanning line Y, and the data line X is used as it is. The manufacturing method will be described with reference to FIGS. These drawings are cross-sectional views showing the steps of a method for manufacturing the active matrix substrate of the present embodiment. In each of the drawings, the left side thereof has a cross section taken along line AA ′ of FIG.
T section), and the central part is BB 'in FIG. 7 or FIG.
A cross section taken along line (sealing material forming area GA / wiring under seal) is shown on the right side, and a cross section taken along line CC ′ in FIG. 7 or 9 (sealing material forming area GA / wiring under seal) is shown. . The step of forming the lower wiring 3b and the upper wiring 6b constituting the capacitor 85 includes:
Since it is basically the same as the method described below, the description is omitted.

First, as shown in FIG. 14A, on the surface of a transparent substrate 10 made of a glass substrate such as a quartz substrate or an alkali-free glass substrate, a lower wiring layer is formed in the sealing material forming area GA. A wet etching or a dry etching is applied to a region where 3b is to be formed, and a groove 110 is formed there. However, the pixel TFT portion is kept flat. In forming the groove 110, the substrate 10 may be etched.
Conversely, the lower wiring layer 3 is formed in the sealing material forming area GA.
A configuration may be adopted in which a silicon oxide film or the like is formed on both sides of the region where b is to be formed and this portion is raised, and as a result, the groove 110 is formed in the region where the lower wiring layer 3b is to be formed.

Next, on either side of the pixel TFT portion and the under-seal wiring portion, directly on the entire surface of the substrate 10 or on the entire surface of the underlying protective film formed on the surface of the substrate 10.
The thickness is about 500 Å to about 2000 Å, preferably about 100 Å by a low pressure CVD method or the like.
After a semiconductor film 1 made of a 0 Å polysilicon film is formed, it is patterned by photolithography as shown in FIG.
An island-shaped semiconductor film 1a (active layer) is formed on the side of the FT section. On the other hand, the semiconductor film 1
Is completely removed. The above-described semiconductor film is formed by depositing an amorphous silicon film and then performing thermal annealing at a temperature of 600 ° C. to 700 ° C. for 1 hour to 8 hours to form a polysilicon film or after depositing the polysilicon film. Alternatively, a method may be used in which silicon is implanted, made amorphous, and then recrystallized by thermal annealing to form a polysilicon film.

Next, as shown in FIG. 14C, a gate oxide film 2 having a thickness of about 600 angstroms to about 1500 angstroms is formed on the surface of the semiconductor film 1a by a thermal oxidation method or the like (gate oxide film formation). Process). As a result, the thickness of the semiconductor film 1a is about 300 angstroms to about 1500 angstroms, and preferably 350 angstroms to about 450 angstroms.

Next, as shown in FIG. 14D, after a polysilicon film 3 for forming the scanning lines Y and the like is formed on the entire surface of the substrate 10, the polysilicon film 3 is formed by photolithography using FIG. As shown in E), patterning is performed to form a gate electrode as a part of the scanning line Y on the pixel TFT portion side. On the other hand, in the sealing material forming area GA, the polysilicon film is left as the lower wiring 3b.

Next, as shown in FIG.
On the side of the FT section and the N-channel TFT section of the drive circuit,
Using the gate electrode as a mask, about 0.1 × 10 ¹³ / cm ²
A low concentration impurity ion 100 (phosphorous ion) is implanted at a dose of about 10 × 10 ¹³ / cm ² ,
On the side of the FT portion, a lightly doped source region 1b and a lightly doped drain region 1c are self-aligned with the gate electrode.
To form Here, since it is located immediately below the gate electrode, a portion where the impurity ions 100 are not introduced becomes a channel region in which the semiconductor film 1a remains. When the ion implantation is performed in this manner, impurities are also introduced into the polysilicon film formed as the gate electrode and the polysilicon film formed as the lower wiring 3b in the sealing material forming region GA. , They will be more conductive.

Next, as shown in FIG.
In the FT area, a resist mask 1 wider than the gate electrode is used.
02 to form a high concentration impurity ion 101 (phosphorus ion) from about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10 ¹⁵ / c.
The implantation is performed at a dose of m ² to form a high-concentration source region 1d and a high-concentration drain region 1e.

Instead of these impurity introduction steps, high-concentration impurities (phosphorous ions) are implanted in a state where a resist mask 102 wider than the gate electrode is formed without implanting low-concentration impurities. A region and a drain region may be formed. It is needless to say that a high-concentration impurity (phosphorus ion) may be implanted on the gate electrode to form a source region and a drain region having a self-aligned structure.

Although not shown, in order to form a P-channel TFT portion of the peripheral drive circuit, the screen display area and the N-channel TFT portion are covered and protected with a resist, and about 0 .1 × 10 ¹⁵ / c
By implanting boron ions at a dose of m ² to about 10 × 10 ¹⁵ / cm ² , P-channel source / drain regions are formed in a self-aligned manner. Note that N channel TF
Similarly to the formation of the T portion, a low concentration impurity (boron ion) is introduced at a dose of about 0.1 × 10 ¹³ / cm ² to about 10 × 10 ¹³ / cm ^{2 using} the gate electrode as a mask. ,
After forming a low-concentration region in the polysilicon film, a mask wider than the gate electrode is formed, and a high-concentration impurity (boron ion) is added at about 0.1 × 10 ¹⁵ / cm ² to about 10 × 10
The source region and the drain region having an LDD structure (lightly doped drain structure) may be formed by implantation at a dose of ¹⁵ / cm ² . Alternatively, a source region and a drain region having an offset structure may be formed by implanting high-concentration impurities (boron ions) in a state where a mask wider than the gate electrode is formed without implanting low-concentration impurities. . Through these ion implantation steps, it is possible to implement CMOS, and it is possible to integrate the peripheral drive circuit into the same substrate.

Next, as shown in FIG. 15A, the thickness of the gate electrode and the lower wiring 3b is reduced to about 50
After forming a first interlayer insulating film 4 made of an NSG film (silicate glass film containing neither boron nor phosphorus) having a thickness of 00 Å to about 15,000 Å, FIG.
As shown in FIG. 5B, on the pixel TFT portion side, the first interlayer insulating film 4 is formed using photolithography technology.
A contact hole 5a is formed in a portion corresponding to the source region 1d.
To form In the sealing material forming area GA, a plurality of contact holes 5b are formed in a portion corresponding to the lower layer wiring 3b.
To form

Next, as shown in FIG. 15C, a low-resistance conductive film such as an aluminum film 6 for forming the data line X is formed on the surface side of the first interlayer insulating film 4 by a sputtering method or the like. After that, as shown in FIG. 15D, the aluminum film 6 is patterned by using the photolithography technique, and in the pixel TFT portion, a source electrode is formed as a part of the data line X, and the sealing material forming area GA is formed. Then, upper layer wiring 6
b is formed.

Next, as shown in FIG. 16A, a thickness of about 5000 Å to about 5,000 Å is formed on the surface side of the source electrode and the upper wiring 6 b under a low temperature condition of, for example, about 500 ° C. by a CVD method or the like. After forming a second interlayer insulating film 7 made of a 15000 Å PSG film (silicate glass film containing boron or phosphorus) or the like, FIG.
As shown in FIG. 6B, on the pixel TFT portion side, a portion of the first interlayer insulating film 4 and the second interlayer insulating film 7 corresponding to the drain region 1e by using a photolithography technique and a dry etching method. Contact hole 8a
To form

Next, as shown in FIG. 16C, an ITO film 9 (In) having a thickness of about 1500 angstroms for forming a drain electrode is formed on the surface side of the second interlayer insulating film 7.
16D, the ITO film 9 is patterned using a photolithography technique, and a pixel electrode 9a is formed in a pixel TFT portion, and a seal under the seal is formed as shown in FIG. In the wiring section, the ITO film 9 is completely removed. Here, the pixel electrode 9
As a, not limited to the ITO film, SnO _X film or a ZnO _X
It is also possible to use a transparent electrode material made of a high-melting metal oxide such as a film, and if these materials are used,
The step coverage in the contact hole 8a is also practical.

As described above, if the lower layer wiring 3b and the upper layer wiring 6b are formed in the pixel TFT portion using the process of forming the pixel switching TFT 60, the scanning line Y, and the data line X, the sealing material is formed. The region GA can be formed with the minimum required number of steps.

(Other Embodiments) In the above-described embodiment, the under-seal wiring constituting the seal material forming area GA is formed by one wiring layer. However, the lower side of the seal material GS containing the gap material is used. Even if the present invention is applied to an active matrix substrate having a configuration in which one signal wiring passes as a seal-under wiring, there is an advantage that disconnection of the signal wiring can be prevented.

[0069]

As described above, in the liquid crystal device according to the present invention, in the surface of the substrate serving as the base of the active matrix substrate, the groove is formed in the region where the seal material is formed and overlaps with each under-seal wiring. As a result, the surface of the substrate is depressed accordingly. Therefore, even if the wiring under the seal is passed through the area corresponding to the lower layer side of the seal material, the bulge corresponding to the thickness of the wiring under the seal is relaxed and absorbed by the depth of the groove. Become flat. For this reason, the stress from the gap material is dispersed and applied to the seal material forming region, and is not concentrated on the wiring under the seal. Therefore, no disconnection occurs even when the signal line forming the closed circuit passes through the lower layer of the sealing material containing the gap material, so that a display line defect does not occur.

[Brief description of the drawings]

FIG. 1 is a plan view of a liquid crystal device to which the present invention is applied.

FIG. 2 is a cross-sectional view taken along line HH ′ of FIG.

3 is a block diagram of an active matrix substrate with a built-in drive circuit used in the liquid crystal device shown in FIG.

FIG. 4 is a plan view of a pixel switching TFT formed on the active matrix substrate shown in FIG.

FIG. 5 is a timing chart showing a reset (precharge) operation performed in the liquid crystal device shown in FIG.

FIG. 6 is an explanatory diagram showing an enlarged area indicated by L11 in FIG. 1;

FIG. 7 is an explanatory diagram of a sealing material forming region around the data line driving circuit shown in FIG. 6;

8A and 8B are a cross-sectional view taken along line BB 'and a cross-sectional view taken along line CC' in FIG. 7, respectively.

FIG. 9 is an explanatory diagram of a seal material forming region around the scanning line driving circuit shown in FIG. 6;

FIGS. 10A and 10B are respectively BB ′ of FIG. 9;
It is sectional drawing in the line, and sectional drawing in the CC 'line.

FIG. 11 is an explanatory diagram showing an enlarged area indicated by L12 in FIG. 1;

FIG. 12 is an explanatory diagram of a seal material forming region around a reset circuit shown in FIG. 11;

13 (A), (B) and (C) respectively show FIG.
3 is a sectional view taken along line DD ′, a sectional view taken along line EE ′, and a sectional view taken along line FF ′.

14 is a process sectional view illustrating the method of manufacturing the active matrix substrate illustrated in FIG.

FIG. 15 is a process cross-sectional view showing a process performed after FIG. 14;

16 is a process cross-sectional view showing a process performed after FIG.

FIG. 17 is an explanatory view showing a corner portion of a conventional active matrix substrate.

18 is an explanatory diagram of a seal material forming region around a scanning line driving circuit of the active matrix substrate shown in FIG.

FIGS. 19A and 19B are respectively Q-Q in FIG.
It is sectional drawing in the Q 'line, and sectional drawing in the RR' line.

[Explanation of symbols]

 3b Lower layer wiring of sealing material forming area 4 First interlayer insulating film 6b Upper layer wiring of sealing material forming area 7 Second interlayer insulating film 10 Substrate 21 Screen display area 22 Data line driving circuit 23 Scanning line driving circuit 60 Pixel switching TFT 64 sampling drive signal line 65 image signal sampling wiring 80 reset drive circuit 85 capacitor 110 substrate groove AM active matrix substrate G gap material GS seal material containing gap material GA seal material formation area LP liquid crystal device OP counter substrate VID1 VID6 Image signal line X Data line Y Scan line

Claims (11)

[Claims] A liquid crystal is sealed between a first substrate and a second substrate, and a pixel region having pixel electrodes formed in a matrix on the first substrate and a pixel region surrounding the pixel region are provided. And a first wiring formed between the pixel region and the driving circuit, wherein the first substrate and the second substrate are formed on the first substrate. What is claimed is: 1. A liquid crystal device, comprising: a liquid crystal device bonded to a wiring by a sealing material containing a gap material; a first insulating film having a concave portion in a region where the first wiring and the sealing material overlap on the first substrate; Wherein the first wiring is disposed on the concave portion of the first insulating film. 2. The first substrate according to claim 1, wherein the first substrate has a first wiring disposed in the concave portion and a second insulating film disposed on the first wiring in a region overlapping the sealing material. And a second wiring disposed on the second insulating film so as to overlap the first wiring. 3. The liquid crystal device according to claim 2, wherein the second insulating film has a concave portion, and the second wiring is disposed in the concave portion of the second insulating film. 4. The semiconductor device according to claim 3, wherein the first wiring and the second wiring overlapping each other via the interlayer insulating film are connected via a contact hole formed in the first insulating film. A liquid crystal device. 5. A liquid crystal is sealed between a first substrate and a second substrate. A plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, and the scanning lines are provided on the first substrate. A pixel region including a transistor connected to the data line and a pixel electrode connected to the transistor; a driving circuit portion formed around the pixel region; and a driving circuit portion between the pixel region and the driving circuit portion. And a first wiring formed, wherein the first wiring
The substrate and the second substrate are liquid crystal devices that are bonded together on the wiring formed on the first substrate with a sealing material containing a gap material, and the first substrate includes the first substrate and the second substrate. A liquid crystal device, comprising: a first insulating film having a concave portion in a region where a wiring and the seal material overlap; and the first wiring is disposed on the concave portion of the first insulating film. 6. The first substrate according to claim 5, wherein the first substrate has a first wiring disposed in the concave portion and a second insulating film disposed on the first wiring in a region overlapping with the sealing material. And a second wiring disposed on the second insulating film so as to overlap the first wiring. 7. The liquid crystal device according to claim 6, wherein the second insulating film has a concave portion, and the second wiring is disposed on the concave portion of the second insulating film. 8. The method according to claim 6, wherein the first wiring and the second wiring overlapping each other via the first insulating film are connected via a contact hole formed in the first insulating film. A liquid crystal device, comprising: 9. The device according to claim 6, wherein the first wiring is a wiring formed simultaneously with one of the data line and the scanning line, and the second wiring is formed by the data line and the scanning line. A liquid crystal device, which is a wiring formed simultaneously with the other signal line of the scanning lines. 10. A data line driving circuit according to claim 7, wherein the driving circuit supplies an image signal to each of the plurality of data lines, and a scanning circuit supplies a scanning signal to each of the plurality of scanning lines. A line driving circuit, and each of the drawing part of the data line from the screen display area to the data line driving circuit, and the drawing part of the scanning line from the screen display area to the scanning line driving circuit is A liquid crystal device comprising wiring arranged in a sealing material forming region. 11. A liquid crystal is sealed between a first substrate and a second substrate. A plurality of scanning lines, a plurality of data lines intersecting the plurality of scanning lines, and the scanning lines are provided on the first substrate. A pixel region including a transistor connected to the data line and a pixel electrode connected to the transistor; a driving circuit portion formed around the pixel region; and a driving circuit portion between the pixel region and the driving circuit portion. A first wiring formed on the first substrate and the second substrate, wherein the first substrate and the second substrate are bonded to each other on the wiring formed on the first substrate by a sealing material containing a gap material. A manufacturing method, comprising: forming a first insulating film on the first substrate; forming a concave portion in the first insulating film; forming a first wiring in the concave portion of the first insulating film; And the scanning line and the source are made of the same material as the first wiring. Method of manufacturing a liquid crystal device characterized by a step of forming one wiring of the scan lines.