JP3617514B2 - Liquid crystal device and manufacturing method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a liquid crystal device using an active matrix substrate. More specifically, the present invention relates to a structure of a sealing material forming region which is a base in a region where a gap material-containing sealing material for bonding an active matrix substrate and a counter substrate is formed.
[0002]
[Prior art]
An active matrix substrate used in a liquid crystal device is formed in a direction in which a plurality of scanning lines and a plurality of data lines intersect on a substrate such as a quartz substrate or non-crisp glass, and a plurality of pixels are matrixed by these signal lines. Configured. A region where these pixels are arranged in a matrix is a screen display region. The active matrix substrate and the counter substrate are bonded to each other with a predetermined cell gap by a gap material-containing sealing material formed outside the screen display area. Flatness as a sealing material forming region is required for a portion that becomes a base region of the sealing material.
[0003]
Therefore, conventionally, as shown in FIG. 17, in the active matrix substrate AM, outside the screen display area 21, the drawing portion of the data line X from the screen display area 21 to the data line driving circuit 22, and the screen display area 21. Since a large number of lead-out portions of the scanning line Y to the scanning line drive circuit 23 are arranged in parallel and a substantially flat region is formed therein, this region may be used as the sealing material forming region GA. In this case, for example, the lead-out portion of the data line X and the lead-out portion of the scanning line Y may be used as they are as the under-seal wiring constituting the seal material forming area GA, but FIG. 18 and FIG. , (B), for example, the scanning line Y is a lower layer side wiring 3b made of a polysilicon film, and an upper layer side wiring 6b made of an aluminum film is connected to the lower layer side wiring 3b with a first interlayer insulating film 4 interposed therebetween. By stacking the under-seal wiring in a two-layer structure, there may be a case where the seal material forming area GA is made one step higher than the surroundings and each wiring is arranged with a slight gap from the adjacent wiring. With this configuration, as shown in FIG. 19B, when the active matrix substrate AM and the counter substrate OP are bonded to each other by the sealing material GS containing the gap material G, they are included in the sealing material GS on each wiring. Since the gap material G has been deposited, the cell gap between the active matrix substrate AM and the counter substrate OP can be controlled.
[0004]
[Problems to be solved by the invention]
As shown in FIG. 19B, in the gap control structure using the portion corresponding to the under-seal wiring projecting one step higher than the surrounding, stress from the gap material G is concentrated on the under-seal wiring. , Cracks tend to occur in the wiring under the seal. Even so, if the under-seal wiring is a dummy wiring that does not constitute a closed circuit, display is not hindered even if a disconnection occurs.
[0005]
However, when a wire that forms a closed circuit as a signal line, such as the data line X or the scanning line Y, is used as an under-seal wire, if the disconnection occurs, the display has a line defect. There is a problem that it occurs. Such a problem occurs even when the undersealed wiring is composed of one layer of wiring. However, if the undersealed wiring has a two-layer structure, the portion corresponding to the undersealed wiring protrudes higher, and thus the disconnection occurs. It tends to occur.
[0006]
In view of the above problems, an object of the present invention is to provide a liquid crystal device in which a broken line does not occur even when a signal line that constitutes a closed circuit is used as an under-sealing wiring and passes through a lower layer side of a sealing material containing a gap material. is there.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides a liquid crystal device in which a first and a second substrate are bonded together with a sealing material, and liquid crystal is injected between the first and the second substrates, The substrate is provided corresponding to a plurality of scanning lines, a plurality of data lines, a transistor provided corresponding to a region where the plurality of scanning lines and the plurality of data lines intersect, and a corresponding one of the transistors A pixel electrode; a reset signal line for applying a reset potential prior to supply of an image signal to the plurality of data lines; and a constant potential wiring; and a region of the reset signal line in the sealing material formation region. The extension portion and the extension portion of the constant potential wiring overlap through a dielectric film to form a capacitor, and the capacitor Formed on the first substrate; It is arranged in a groove-like recess extending in the extending direction of the capacitor.
[0008]
Further, the present invention provides the reset signal line. Extension part And the constant potential wiring Extension part It is preferable that the wiring is formed so that one of the two overlaps the other through a contact hole formed in the dielectric film.
[0009]
Further, the present invention provides the reset signal line. Extension part And the constant potential wiring Extension part It is preferable that a plurality of the first and second recesses extend and overlap each other, and the recesses are formed corresponding to the respective overlaps.
[0010]
In the method for manufacturing a liquid crystal device according to the present invention, the first and second substrates are bonded together with a sealing material, and liquid crystal is injected between the first and second substrates. A scanning line, a plurality of data lines, a transistor provided corresponding to a region where the plurality of scanning lines and the plurality of data lines intersect, a pixel electrode provided corresponding to the transistor, A method for manufacturing a liquid crystal device, comprising: a reset signal line for applying a reset potential prior to supply of an image signal to the plurality of data lines; and a constant potential wiring, wherein the formation region of the sealing material A capacitor in which the extension portion of the reset signal line and the extension portion of the constant voltage wiring overlap with each other via a dielectric film, Formed on the first substrate; It is characterized by comprising a step of forming in a groove-like recess extending in the extending direction of the capacitor.
[0011]
According to the present invention, since the wiring is formed in the recess in the sealing material forming region, the rise corresponding to the thickness of the wiring is relaxed and absorbed by the depth of the groove. Since these are added in a distributed manner in the sealing material forming region, it is possible to prevent concentration on the wiring formed under the sealing material.
[0012]
DETAILED DESCRIPTION OF THE INVENTION
Embodiments of the present invention will be described with reference to the drawings.
[0013]
(Overall configuration of liquid crystal device)
FIG. 1 and FIG. 2 are a plan view of a liquid crystal device to which the present invention is applied and a cross-sectional view taken along the line H-H ′, respectively.
[0014]
As shown in these drawings, the liquid crystal device LP includes a rectangular screen display area 21 in which pixels to be described later are formed in a matrix, a data line driving circuit 22 formed in an outer area of the screen display area 21, and a screen. The active matrix substrate AM includes a pair of scanning line driving circuits 23 formed on both sides of the display region 21 and a counter substrate OP disposed to face the active matrix substrate AM.
[0015]
The counter substrate OP and the active matrix substrate AM are gap materials formed along the outer peripheral edge of the screen display area 21 in an area corresponding to the area between the screen display area 21 and the data line driving circuit 22 and the scanning line driving circuit 23. The liquid crystal LC is sealed in an inner region of the sealing material GS while being pasted with a predetermined cell gap by the contained sealing material GS. Here, since the sealing material GS is partially interrupted, the liquid crystal injection port 241 is configured by the interrupted portion. For this reason, in the liquid crystal device LP, the liquid crystal LC can be injected under reduced pressure from the liquid crystal injection port 241 if the inner region of the sealing material GS is brought into a reduced pressure state after the counter substrate OP and the active matrix substrate AM are bonded together. Then, the liquid crystal injection port 241 is closed with a sealant 242. As the sealing material GS, an epoxy resin, various ultraviolet curable resins, or the like can be used. As a gap material to be mixed therewith, a cylinder having a diameter of about 2 μm to about 6 μm, a spherical glass fiber, or the like can be used.
[0016]
Here, since the counter substrate OP is smaller than the active matrix substrate AM, the peripheral portion of the active matrix substrate AM is bonded to the outer periphery of the counter substrate OP. Therefore, the sealing material GS is formed along the outer periphery of the substrate when viewed from the counter substrate OP, but is formed considerably inside from the outer periphery of the substrate when viewed from the active matrix substrate AM. Therefore, the scanning line driving circuit 23 and the data line driving circuit 22 are located outside the counter substrate OP and are not opposed to the counter substrate OP.
[0017]
In the active matrix substrate AM, a metal film such as an aluminum film, a metal silicide film, or a conductive film such as an ITO film to which a constant power source, a modulated image signal, various signals, etc. are input is provided on the side portion on the data line driving circuit 22 side. A large number of external input / output terminals 25 are configured. A plurality of signal lines 28 made of a low resistance metal film such as an aluminum film or a metal silicide film for driving the scanning line driving circuit 23 and the data line driving circuit 22 are routed from these external input / output terminals 25. Has been.
[0018]
The counter substrate OP is formed so as to surround each pixel and a counter electrode 51 made of an ITO film facing the pixel electrode of each pixel formed on the active matrix substrate AM side with the liquid crystal LC interposed therebetween. A black matrix BM1 made of a light shielding film is formed. Further, a light shielding film BM2 for parting the display screen is also formed on the counter substrate OP along the inner periphery of the sealing material GS.
[0019]
On the outer periphery of the active matrix substrate AM, vertical conduction terminals 33 are formed in areas corresponding to the corners of the screen display area 21 in the formation area of the sealing material GS. A common potential is supplied from the common potential line 32 of the active matrix substrate AM to the counter electrode 51 of the counter substrate OP by the vertical conduction member 31 made of silver dot balls sandwiched between the counter substrate OP.
[0020]
(Configuration of active matrix substrate and screen display area)
FIG. 3 is a block diagram of an active matrix substrate with a built-in drive circuit used in the liquid crystal device of this embodiment.
[0021]
In FIG. 3, an alternate long and short dash line L1 indicates a position that partitions the screen display region 21, and an alternate long and short dash line L2 indicates a region where the sealing material GS is formed.
[0022]
In the active matrix substrate AM, a plurality of pixels PX are configured in a matrix by a plurality of scanning lines Y and a plurality of data lines X on a transparent substrate 10 such as a quartz substrate or non-alkali glass. Each pixel PX is taken out, and as shown in FIG. 4, a pixel switching thin film transistor 60 (hereinafter referred to as a thin film transistor) connected to the scanning line Y and the data line X is formed. The basic configuration of the TFT 60 is the same as that of a conventional TFT, and will be described in detail in the manufacturing method. The drain electrode sandwiches the liquid crystal LC between the counter electrode 51 of the counter substrate OP. This is a pixel electrode 9a constituting the liquid crystal cell. For the liquid crystal cell, the storage capacitor CAP is configured by using the previous gate line and the capacitor wiring Z. The pixel switching TFT 60 is electrically connected to the gate electrode which is a part of the scanning line Y and the source electrode which is a part of the data line X through the first contact hole 5a of the first interlayer insulating film. A source region and a drain region to which a pixel electrode 9a made of an ITO film is electrically connected through a second contact hole 8a penetrating the first interlayer insulating film and the second interlayer insulating film are provided.
[0023]
(Configuration of drive circuit)
In FIG. 3 again, the data line driving circuit 22 formed on the active matrix substrate AM has an X-side shift register circuit and a buffer circuit, and between the data line driving circuit 22 and the screen display area 21. , A sampling circuit 224 having a TFT (analog switch) that operates based on a signal output from the X-side shift register circuit via a buffer circuit, and six image signals corresponding to each image signal developed in six phases Lines VID1 to VID6 are configured. Note that the data line drive circuit 22, the image signal lines VID1 to VID6, and the sampling circuit 224 include a sampling drive signal line 64 for supplying a signal from the X-side shift register circuit to the sampling circuit 224, and the image signal lines VID1 to VID1. The circuit is connected by an image signal sampling wiring 65 that connects the VID 6 and the sampling circuit 224. Therefore, in the sampling circuit 224, each TFT operates based on the signal output from the data line driving circuit 22, and the image signal supplied through the image signal lines VID1 to VID6 is applied to the data line X at a predetermined timing. It is possible to capture and supply to each pixel PX.
[0024]
Further, the scanning line driving circuit 23 formed on the active matrix substrate AM also includes a Y-side shift register circuit and a buffer circuit.
[0025]
In the active matrix substrate AM of the present embodiment, an area overlapping the display screen parting light shielding film BM2 on the side opposite to the side where the data line driving circuit 22 is formed with respect to the screen display area 21, A reset driving circuit 80 is also configured to appropriately perform the inversion driving method in which the polarity of the image signal is inverted for each row.
[0026]
(Reset drive circuit)
FIG. 5 is a timing chart showing a reset (precharge) operation performed in the liquid crystal device shown in FIG.
[0027]
In the liquid crystal device LP using the active matrix substrate AM, for example, when the inversion driving method in which the polarity of the image signal is inverted for each row is performed, as shown in FIG. 5A, the data line X (the pixel switching TFT 60) Since the image signal supplied to the source electrode is written into the liquid crystal cell via the TFT 60 while the polarity is inverted every horizontal scanning period, the potential of the pixel electrode of the pixel switching TFT is as shown in FIG. It changes as shown. That is, since the polarity of the image signal is inverted every horizontal scanning period, the potential of the pixel electrode changes greatly, and charging and discharging from the data line X to the image signal lines VID1 to VID6 are repeated accordingly. Such a charge / discharge has a relatively low sampling rate if the display is based on the NTSC standard, so that the display quality is unlikely to be adversely affected. Cause noise.
[0028]
Therefore, in this embodiment, as shown in FIG. 3, an image signal to the data line X is used in an area opposite to the data line driving circuit 22 with respect to the screen display area 21 using a horizontal blanking interval or the like. Prior to supply, two series of reset signal lines 81 and 82 for applying a reset potential to each of the data lines X, a reset potential supply switch circuit 83, and the reset potential supply switch circuit 83 are driven. A reset drive circuit 80 including a reset drive signal line 86 is configured, and charging / discharging from the data line X is almost completed with a reset potential. According to this configuration, as shown in FIG. 5C, a reset potential having a predetermined polarity is applied from the reset signal lines 81 and 82 immediately before the image signal is supplied to the data line X. For this reason, charging / discharging from the data line X can be almost completed before the image signal is supplied to the data line X. Therefore, as shown in FIG. The amount of charge / discharge from the data line X can be suppressed. Therefore, since the potential fluctuations of the image signal lines VID1 to VID6 can be prevented, generation of noise in the display can be suppressed.
[0029]
Further, in the active matrix substrate AM of the present embodiment, a constant potential line 84 is configured in parallel to the reset signal lines 81 and 82 in a region outside the reset signal lines 81 and 82, and the constant potential line 84 and the reset signal line 81 are arranged. , 82 is provided with a capacitor 85. The constant potential line 84 is set to the same potential as the potential of the counter electrode 51 of the counter substrate OP bonded to the active matrix substrate AM, for example, similarly to the capacitor wiring Z and the like, and this potential is shown in FIGS. This corresponds to the intermediate potential of the amplitude of the image signal and reset signal shown in FIG. As described above, in the active matrix substrate AM of this embodiment, the capacitor 85 is formed between the reset signal lines 81 and 82 and the constant potential line 84, and therefore the time constant of the reset signal lines 81 and 82 is large. Therefore, when a reset potential is applied to each data line X, it is possible to more reliably prevent a signal from wrapping around the other data line X via the reset signal lines 81 and 82. Therefore, even in a liquid crystal device of a type in which a reset potential is applied to each data line X prior to the supply of the image signal to the data line X, horizontal crosstalk due to signal wraparound does not appear, and display The quality can be improved.
[0030]
(Configuration of sealing material formation area)
In the active matrix substrate AM configured as described above, the sealing material GS is formed in a region indicated by a one-dot chain line L2 in FIG. In forming this sealing material GS, in this embodiment, as will be described in detail with reference to FIGS. 6 to 13, in the lower layer region of the sealing material GS on the active matrix substrate AM side, the display operation of the liquid crystal device LP is performed. This region is substantially flattened as a sealing material formation region by passing a signal line constituting a closed circuit that bears the above.
[0031]
FIG. 6 is an enlarged view of a corner portion (circular region L11 in FIG. 1) of the liquid crystal device LP. FIG. 7 is an explanatory diagram of a sealing material forming region around the data line driving circuit shown in FIG. 8A and 8B are a cross-sectional view taken along the line BB 'in FIG. 7 and a cross-sectional view taken along the line CC', respectively. FIG. 9 is an explanatory diagram of a sealing material forming region around the scanning line driving circuit shown in FIG. 10A and 10B are respectively
FIG. 10 is a cross-sectional view taken along line BB ′ of FIG. 9 and a cross-sectional view taken along line CC ′.
[0032]
First, as shown in FIG. 6, in the active matrix substrate AM of the present embodiment, the sampling circuit 224 and the image signal line are disposed between the data line driving circuit 22 and the screen display area 21 in the outer area of the screen display area 21. A gap material-containing sealing material GS is formed in a region corresponding to VID1 to VID6. For this reason, a plurality of columns of sampling drive signal lines 64 (data lines from the screen display area 21 to the data line drive circuit 22) for wiring-connecting the data line drive circuit 22 and the sampling circuit 224 are provided in the lower layer side region of the sealing material GS. X drawing portion) and image signal sampling wiring 65 (drawing portion of the data line X from the screen display area 21 to the data line driving circuit 22) connecting the image signal lines VID1 to VID6 and the sampling circuit 224 are sealed. Passing in parallel as the wiring under the region where is formed.
[0033]
Further, as shown in the enlarged view of the periphery of the data line driving circuit 22 in FIG. 7, the signal lines are reset at equal intervals with these signal lines on both sides of the formation region of the sampling signal driving signal line 64 and the image signal sampling wiring 65. The reset signal line 81 and the reset drive signal line 86 of the drive circuit 80 pass through, and the reset signal line 81 and the reset drive signal line 86 also pass through the lower layer side region of the sealing material GS as the under-seal wiring.
[0034]
Of the pixels PX formed in a matrix, pixels at the outer periphery are not stable in characteristics, and overlap with the light shielding film BM2 for parting as a dummy pixel PX ′ that is not used for display.
[0035]
Here, in the sampling signal drive signal line 64, the image signal sampling wiring 65, the reset signal line 81, and the reset drive signal line 86, portions corresponding to the under-seal wiring passing through the lower layer side of the sealing material GS are shown in FIGS. As shown in FIG. 8A, the upper wiring 6b is formed of an aluminum film (conductive film) formed simultaneously with the data line X. The upper wiring 6b is formed of polysilicon formed simultaneously with the scanning line Y. The lower wiring 3b made of a film (conductive film) overlaps with the first interlayer insulating film 4 interposed therebetween. Further, the lower layer side wiring 3b and the upper layer side wiring 6b are electrically connected at a plurality of positions through a plurality of contact holes 5b of the first interlayer insulating film 4 to constitute a redundant wiring structure.
[0036]
In this way, the lower layer side wiring 3b and the upper layer side wiring 6b are formed in a two-layer structure and are arranged side by side with a neighboring gap with a slight gap. Although used as the area GA, in this embodiment, as shown in the cross-section CC ′ of FIG. 7 in FIG. 8B, each under-seal wiring (lower layer side) in the sealing material formation area GA on the surface of the substrate 10. In a region overlapping with the wiring 3b and the upper layer side wiring 6b), a plurality of rows of grooves 110 (recesses) recessed in the substrate surface are formed. Therefore, even if the under-seal wiring (lower layer side wiring 3b and upper layer side wiring 6b) is formed in a region corresponding to the lower layer side of the sealing material GS, the rise corresponding to the film thickness of the lower seal wiring is the depth of the groove 110. Therefore, the outermost layer (the surface of the second interlayer insulating film 7) of the sealing material forming area GA is flat. For this reason, even if the sealing material GS containing the gap material G is applied to the surface of the sealing material forming area GA and the active matrix substrate AM and the counter substrate OP are bonded together by this sealing material GS, the stress from the gap material G Since they are dispersed and added to the sealing material forming area GA, they are not concentrated on the wiring under the seal (the lower layer side wiring 3b and the upper layer side wiring 6b). Therefore, the signal lines (sampling signal driving signal line 64, image signal sampling wiring 65, reset signal line 81, and reset driving signal line 86) constituting the closed circuit are placed under the sealing material GS containing the gap material G. Since no disconnection occurs through the side, display line defects do not occur.
[0037]
In addition, since the wiring has a two-layer structure in the portion corresponding to the under-seal wiring, the electrical resistance is small, and even if a disconnection occurs in one of the lower layer side wiring 3b and the upper layer side wiring 6b, Signals and potentials can be transmitted and supplied, and display is not hindered.
[0038]
As shown in FIG. 6, between the scanning line driving circuit 23 and the screen display area 21, a sealing material GS is formed in an area corresponding to a drawing portion of the scanning line Y from the screen display area 21 to the scanning line driving circuit 23. Has been. Accordingly, the scanning line Y passes in parallel as the under-seal wiring in the lower layer side region of the sealing material GS.
[0039]
Further, as shown in an enlarged view of the periphery of the data line driving circuit 22 in FIG. 9, a reset signal line 82 of the reset driving circuit 80 passes through a position adjacent to the scanning line Y. The lower layer side region of the sealing material GS passes as an under-seal wiring.
[0040]
Here, the scanning line Y is a lower-layer side wiring in which a portion corresponding to the lower-sealing wiring passing through the lower layer side of the sealing material GS is made of a polysilicon film (conductive film) as shown in FIGS. 9 and 10A. The upper wiring 6b made of an aluminum film (conductive film) formed simultaneously with the data line X overlaps the lower wiring 3b with the first interlayer insulating film 4 interposed therebetween. Further, in the scanning line Y, the lower layer side wiring 3b and the upper layer side wiring 6b are electrically connected at a plurality of locations via a plurality of contact holes 5b of the first interlayer insulating film 4 to constitute a redundant wiring structure. .
[0041]
On the other hand, in the reset signal line 82, the portion corresponding to the under-seal wiring passing through the lower layer side of the sealing material GS is aluminum formed simultaneously with the data line X as shown in FIGS. 9 and 10A. The upper wiring 6b is formed of a film (conductive film). The upper wiring 6b is connected to the lower wiring 3b of the polysilicon film (conductive film) formed at the same time as the scanning line Y. Overlap through. Also in the reset signal line 82, the lower layer side wiring 3b and the upper layer side wiring 6b are electrically connected at a plurality of locations via a plurality of contact holes 5b of the first interlayer insulating film 4 to form a redundant wiring structure. ing.
[0042]
As described above, the lower layer side wiring 3b and the upper layer side wiring 6b are also formed around the scanning line driving circuit 23 in a two-layer structure, and are arranged side by side with a slight gap with the adjacent wiring. Although GS is used as a sealing material forming area GA to be applied, in this embodiment, in the sealing material forming area GA of the surface of the substrate 10, as shown in FIG. A plurality of rows of grooves 110 (concave portions) that are recessed on the substrate surface are formed in regions overlapping with the respective under-seal wires (lower layer side wire 3b and upper layer side wire 6b). Therefore, even if the under-seal wiring (lower layer side wiring 3b and upper layer side wiring 6b) is formed in a region corresponding to the lower layer side of the sealing material GS, the rise corresponding to the film thickness of the lower seal wiring is the depth of the groove 110. Therefore, the outermost layer (the surface of the second interlayer insulating film 7) of the sealing material forming area GA is flat. For this reason, even if the sealing material GS containing the gap material G is applied to the surface of the sealing material forming area GA and the active matrix substrate AM and the counter substrate OP are bonded together by this sealing material GS, the stress from the gap material G Since they are dispersed and added to the sealing material forming area GA, they are not concentrated on the wiring under the seal. Therefore, even if the signal lines (scanning line Y and reset signal line 82) constituting the closed circuit pass through the lower layer side of the sealing material GS containing the gap material G, the line defect of the display is generated. do not do.
[0043]
Further, even in the portion corresponding to the under-seal wiring, the wiring has a two-layer structure, so that the electrical resistance is small and even if a disconnection occurs in one of the lower layer side wiring 3b and the upper layer side wiring 6b, Signals and potentials can be transmitted and supplied, and display is not hindered.
[0044]
FIG. 11 is an enlarged view of a corner portion (circular region L12 in FIG. 1) of the liquid crystal device LP. FIG. 12 is an explanatory diagram of a sealing material forming region around the reset circuit shown in FIG. FIGS. 13A, 13B, and 13C are a cross-sectional view taken along the line DD ′, a cross-sectional view taken along the line EE ′, and a cross-sectional view taken along the line FF ′ in FIG.
[0045]
As shown in FIG. 11, in the area opposite to the data line drive circuit 22 in the periphery of the scanning line drive circuit 23, reset signal lines 81 and 82 constituting the reset drive circuit 80, constant potential line 84, and A sealing material GS is formed between the upper layer wiring 6b and the lower layer wiring 3b as electrodes constituting the capacitor 85 in a lower layer side region of the sealing material GS, as described with reference to FIG. Is passing as under-seal wiring.
[0046]
As shown in FIGS. 12 and 13A and 13B, each of the reset signal lines 81 and 82 and the constant potential line 84 is a wiring made of a polysilicon film formed simultaneously with the scanning line Y. Of the two wirings constituting the capacitor 85, the lower layer side wiring 3b is an extended portion that protrudes from the constant potential line 84 toward the reset signal lines 81 and 82, and the reset signal lines 81 and 82 and the scanning line Y. And an electrode layer made of a polysilicon film formed simultaneously. On the other hand, the upper layer side wiring 6b is an electrode layer made of an aluminum layer formed simultaneously with the data line X, and is electrically connected to the reset signal lines 81 and 82 through the contact hole 5b. . Here, the reason why the electrode layer electrically connected to the reset signal lines 81 and 82 through the contact hole 5b is used as the upper layer side wiring 6b is that the reset signal lines 81 and 82 are in the same layer position. This is because the upper layer side wiring 6 b electrically connected to the reset signal line 82 extends toward the constant potential line 84 without being electrically connected to the reset signal line 81. In this embodiment, the capacitor 85 includes the first interlayer insulating film 4 as a dielectric film in the overlapping portion of the upper layer side wiring 6b and the lower layer side wiring 3b.
[0047]
In this region, the lower layer side wiring 3b and the upper layer side wiring 6b constituting the capacitor 85 have a two-layer structure, and are applied with a sealing material GS on the adjacent wiring with a slight gap therebetween. In this embodiment, as shown in FIG. 13C, the FF ′ cross section of FIG. 12 is used. In this embodiment, each seal is formed in the sealing material formation area GA on the surface of the substrate 10. In a region overlapping the lower wiring (lower layer wiring 3b and upper layer wiring 6b), a plurality of rows of grooves 110 recessed on the substrate surface are formed. Therefore, even if the under-seal wiring (lower layer side wiring 3b and upper layer side wiring 6b) is formed in a region corresponding to the lower layer side of the sealing material GS, the rise corresponding to the film thickness of the lower seal wiring is the depth of the groove 110. Therefore, the outermost layer (the surface of the second interlayer insulating film 7) of the sealing material forming area GA is flat. For this reason, even if the sealing material GS containing the gap material G is applied to the surface of the sealing material forming area GA and the active matrix substrate AM and the counter substrate OP are bonded together by this sealing material GS, the stress from the gap material G Since they are dispersed and added to the sealing material forming area GA, they are not concentrated on the wiring under the seal. Therefore, no disconnection occurs even if the signal lines constituting the closed circuit (the lower layer side wiring 3b and the upper layer side wiring 6b constituting the capacitor 85) pass through the lower layer side of the sealing material GS containing the gap material G. The capacity of can be obtained reliably. Further, since the sealing material forming area GA having substantially the same height is formed in any of the four sides of the screen display area 21, the cell gap can be controlled with high accuracy.
[0048]
In addition, since the capacitor 85 is formed in the formation region of the sealing material GS, which was a dead space in the past, the active matrix substrate AM is not increased in size even if the capacitor 85 having a large capacity is formed. And the screen display area 21 does not need to be reduced.
[0049]
In any region of the active matrix substrate AM, when the solid aluminum layer or the like is used as the sealing material forming region GA, the photocurable sealing material GS is irradiated with ultraviolet rays to be photocured. However, according to the present invention, it is necessary to use a quartz substrate having a considerably high light transmittance as the counter substrate OP. Since the sealing material GS is formed in the region, even if light is irradiated from the active matrix substrate AM side, the light reaches the sealing material GS through the gaps between the wirings and can be cured. Therefore, it is possible to alleviate the demand for the light transmittance of the counter substrate OP, and there is an advantage that an inexpensive glass substrate such as neo-serum can be used for the counter substrate OP. Further, in the case of the thermosetting sealing material GS, it is unavoidable that the substrate is distorted due to the heat at the time of curing. However, according to the present invention, the heating that causes such distortion is performed. There is an advantage that a photo-curing sealing material GS that does not need to be used can be used.
[0050]
In this embodiment, as shown in FIGS. 3 and 6, a region corresponding to the space between the sampling circuit 224 and the image signal lines VID1 to VID6 is sealed between the data line driving circuit 22 and the screen display region 21. The material GS is formed, and the sampling circuit 224 is in an inner region than the seal material GS. Therefore, from the viewpoint of the structure shown in FIG. 17, the area where the data line driving circuit 22 is formed can be expanded in the portion outside the seal material 80 by the amount that the sampling circuit 224 is formed in the portion inside the seal material GS. Therefore, according to the present embodiment, for the purpose of improving the display quality of the liquid crystal display panel, the data line driving circuit 22 is increased in on-current (operation speed) by expanding the channel width of the TFT constituting the data line driving circuit 22. Improvement), or introduction of a large-scale circuit. In other words, since the peripheral portion of the active matrix substrate can be reduced, a liquid crystal display panel having a display area of the same size but a narrow peripheral portion can be formed. Further, if the entire data line driving circuit 22 is formed inside the sealing material GS, there is a possibility that the liquid crystal is deteriorated due to the influence of the potential of the direct current component applied thereto, but in this embodiment, only the sampling circuit 224 is used. Is disposed inside the sealing material GS, so that the liquid crystal is not deteriorated. In addition, since the sampling circuit 224 is covered with the light shielding film BM2 for parting the display screen, even if the liquid crystal orientation is disturbed, the display quality is not deteriorated.
[0051]
(Manufacturing method of active matrix substrate)
When the sealing material forming area GA is configured in this way, the manufacturing process of the pixel switching TFT 60, the scanning line Y, and the data line X is used as it is. The manufacturing method will be described with reference to FIGS. These drawings are process cross-sectional views showing a method of manufacturing the active matrix substrate of the present embodiment, and in each figure, the left side portion is a cross-section along the line AA ′ of FIG. 4 (cross-section of the pixel TFT portion). 7 and 9 is a cross section taken along the line BB 'in FIG. 7 or FIG. 9 (sealing material forming area GA / under-seal wiring portion), and the right side is a cross section taken along the line CC' in FIG. Material forming region GA / under-seal wiring portion) is shown. In addition, since the process of forming the lower layer side wiring 3b and the upper layer side wiring 6b constituting the capacitor 85 is basically the same as the method described below, the description thereof is omitted.
[0052]
First, as shown in FIG. 14A, the lower wiring layer 3b is formed in the sealing material forming area GA in the surface of the transparent substrate 10 made of a glass substrate such as a quartz substrate or a non-crisp glass substrate. The region to be etched is subjected to wet etching or dry etching, and a groove 110 is formed there. However, the pixel TFT portion is kept flat. In forming the groove 110, the substrate 10 may be etched, but conversely, a silicon oxide film or the like is formed on both sides of the region where the lower wiring layer 3b is formed in the sealing material forming region GA. Then, this portion may be raised, and as a result, the groove 110 may be formed in the region where the lower wiring layer 3b is formed.
[0053]
Next, on either side of the pixel TFT portion and the under-seal wiring portion, the thickness is directly applied to the entire surface of the substrate 10 or the entire surface of the base protective film formed on the surface of the substrate 10 by a low pressure CVD method or the like. After forming a semiconductor film 1 made of a polysilicon film of about 500 angstroms to about 2000 angstroms, preferably about 1000 angstroms, it is patterned using a photolithography technique as shown in FIG. An island-shaped semiconductor film 1a (active layer) is formed on the part side. On the other hand, the semiconductor film 1 is completely removed on the side of the wiring under seal. The semiconductor film is formed by depositing an amorphous silicon film and then performing thermal annealing at a temperature of 600 ° C. to 700 ° C. for 1 hour to 8 hours to form a polysilicon film, or after depositing a polysilicon film. Alternatively, a method of forming a polysilicon film by implanting silicon to make it amorphous and then recrystallizing by thermal annealing may be used.
[0054]
Next, as shown in FIG. 14C, a gate oxide film 2 having a thickness of about 600 angstroms to about 1500 angstroms is formed on the surface of the semiconductor film 1a by a thermal oxidation method or the like (gate oxide film formation step). As a result, the thickness of the semiconductor film 1a is about 300 angstroms to about 1500 angstroms, preferably 350 angstroms to about 450 angstroms.
[0055]
Next, as shown in FIG. 14D, after a polysilicon film 3 for forming the scanning lines Y and the like is formed on the entire surface of the substrate 10, it is formed into a state shown in FIG. As shown, patterning is performed to form a gate electrode as a part of the scanning line Y on the pixel TFT portion side. On the other hand, in the sealing material forming area GA, the polysilicon film is left as the lower layer side wiring 3b.
[0056]
Next, as shown in FIG. 14 (F), on the side of the pixel TFT portion and the N-channel TFT portion of the driver circuit, a gate electrode is used as a mask to provide about 0.1 × 10 ¹³ / Cm ² ~ About 10 × 10 ¹³ / Cm ² A low concentration impurity ion 100 (phosphorus ion) is implanted with a dose amount of low, and a low concentration source region 1b and a low concentration drain region 1c are formed on the pixel TFT portion side in a self-aligned manner with respect to the gate electrode. Form. Here, since it is located directly under the gate electrode, a portion where the impurity ions 100 are not introduced becomes a channel region which remains the semiconductor film 1a. When ions are implanted in this way, impurities are also introduced into the polysilicon film formed as the gate electrode and the polysilicon film formed as the lower layer side wiring 3b in the sealing material forming area GA. , They will become more conductive.
[0057]
Next, as shown in FIG. 14G, in the pixel TFT portion, a resist mask 102 having a width wider than that of the gate electrode is formed so that high-concentration impurity ions 101 (phosphorus ions) are about 0.1 × 10 × 10. ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² Then, a high concentration source region 1d and drain region 1e are formed.
[0058]
In place of these impurity introduction steps, a high concentration impurity (phosphorus ion) is implanted in a state where a resist mask 102 wider than the gate electrode is formed without implanting a low concentration impurity, and a source region and a drain having an offset structure are formed. A region may be formed. Of course, a high concentration impurity (phosphorus ion) may be implanted on the gate electrode to form a source region and a drain region having a self-aligned structure.
[0059]
Although not shown, in order to form the P-channel TFT portion of the peripheral drive circuit, the screen display region and the N-channel TFT portion are covered and protected with a resist, and the gate electrode is used as a mask to provide about 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² By implanting boron ions at a dose of P, source / drain regions of the P channel are formed in a self-aligned manner. As in the formation of the N-channel TFT portion, the gate electrode is used as a mask and about 0.1 × 10 ¹³ / Cm ² ~ About 10 × 10 ¹³ / Cm ² After introducing a low concentration impurity (boron ion) at a dose of a low concentration region in the polysilicon film, a mask wider than the gate electrode is formed to form a high concentration impurity (boron ion). About 0.1 × 10 ¹⁵ / Cm ² ~ About 10 × 10 ¹⁵ / Cm ² The source region and drain region of the LDD structure (lightly doped drain structure) may be formed by implanting with a dose amount of Alternatively, a source region and a drain region having an offset structure may be formed by implanting high-concentration impurities (boron ions) in a state where a mask wider than the gate electrode is formed without implanting low-concentration impurities. . By these ion implantation processes, CMOS can be realized, and the peripheral drive circuit can be built in the same substrate.
[0060]
Next, as shown in FIG. 15A, NSG having a thickness of about 5000 angstroms to about 15000 angstroms is formed on the surface side of the gate electrode and the lower layer side wiring 3b by a CVD method or the like under a temperature condition of about 800 ° C., for example. After forming the first interlayer insulating film 4 made of a film (a silicate glass film that does not contain boron or phosphorus) or the like, as shown in FIG. A contact hole 5a is formed in a portion of the first interlayer insulating film 4 corresponding to the source region 1d. In the sealing material forming area GA, a plurality of contact holes 5b are formed in a portion corresponding to the lower layer side wiring 3b.
[0061]
Next, as shown in FIG. 15C, after a low resistance conductive film such as an aluminum film 6 for forming the data line X is formed on the surface side of the first interlayer insulating film 4 by sputtering or the like, As shown in FIG. 15D, the aluminum film 6 is patterned using a photolithography technique, a source electrode is formed as a part of the data line X in the pixel TFT portion, and an upper layer side is formed in the sealing material formation region GA. A wiring 6b is formed.
[0062]
Next, as shown in FIG. 16A, a thickness of about 5000 angstroms to about 15000 angstroms is formed on the surface side of the source electrode and the upper layer side wiring 6b by a CVD method or the like under a low temperature condition of about 500 ° C., for example. After the second interlayer insulating film 7 made of a PSG film (a silicate glass film containing boron or phosphorus) is formed, as shown in FIG. 16B, on the pixel TFT portion side, a photolithography technique and a dry etching method are used. A contact hole 8a is formed in a portion corresponding to the drain region 1e in the first interlayer insulating film 4 and the second interlayer insulating film 7.
[0063]
Next, as shown in FIG. 16C, an ITO film 9 (Indium Tin Oxide) having a thickness of about 1500 angstroms for forming the drain electrode is formed on the surface of the second interlayer insulating film 7 by sputtering or the like. 16D, the ITO film 9 is patterned using a photolithography technique as shown in FIG. 16D, the pixel electrode 9a is formed in the pixel TFT portion, and the ITO film 9 is formed in the wiring under the seal. Remove completely. Here, the pixel electrode 9a is not limited to the ITO film, but is SnO. _X Film and ZnO _X It is also possible to use a transparent electrode material made of a metal oxide having a high melting point such as a film. With these materials, step coverage within the contact hole 8a can be practically used.
[0064]
Thus, if the lower layer side wiring 3b and the upper layer side wiring 6b are formed by using the process of forming the pixel switching TFT 60, the scanning line Y, and the data line X in the pixel TFT portion, the sealing material forming region GA is formed. It can be formed with the minimum number of steps.
[0065]
(Other embodiments)
In the above embodiment, the under-sealing wiring that constitutes the sealing material forming area GA is configured by one wiring layer. However, one signal wiring is under-sealing wiring on the lower layer side of the gap material-containing sealing material GS. Even when the present invention is applied to an active matrix substrate configured to pass through, there is an advantage that the disconnection of the signal wiring can be prevented.
[0066]
【The invention's effect】
As described above, in the liquid crystal device according to the present invention, a groove is formed in the surface of the substrate serving as the base of the active matrix substrate, in the region overlapping with each under-seal wiring in the sealing material forming region. The surface of the substrate is recessed. Therefore, even if the under-seal wiring is passed through the region corresponding to the lower layer side of the seal material, the rise corresponding to the film thickness of the under-seal wire is relaxed and absorbed by the groove depth, so the outermost layer in the seal material forming region is It becomes flat. For this reason, the stress from the gap material is distributed and applied to the sealing material forming region, so that it does not concentrate on the wiring under the seal. Therefore, no disconnection occurs even if the signal line constituting the closed circuit passes through the lower layer side of the gap material-containing sealing material, so that no display line defect occurs.
[Brief description of the drawings]
FIG. 1 is a plan view of a liquid crystal device to which the present invention is applied.
FIG. 2 is a cross-sectional view taken along the line HH ′ of FIG.
3 is a block diagram of an active matrix substrate with a built-in driving circuit used in the liquid crystal device shown in FIG. 1. FIG.
4 is a plan view of a pixel switching TFT formed on the active matrix substrate shown in FIG. 1. FIG.
5 is a timing chart showing a reset (precharge) operation performed in the liquid crystal device shown in FIG. 1. FIG.
6 is an explanatory diagram showing an enlargement of a region indicated by L11 in FIG. 1; FIG.
7 is an explanatory diagram of a sealing material formation region around the data line driving circuit shown in FIG. 6;
8A and 8B are a cross-sectional view taken along line BB ′ and a cross-sectional view taken along line CC ′ in FIG. 7, respectively.
9 is an explanatory diagram of a sealing material formation region around the scanning line driving circuit shown in FIG. 6;
FIGS. 10A and 10B are a cross-sectional view taken along line BB ′ and a cross-sectional view taken along line CC ′ in FIG. 9, respectively.
FIG. 11 is an explanatory diagram showing an enlargement of a region indicated by L12 in FIG. 1;
12 is an explanatory diagram of a sealing material forming region around the reset circuit shown in FIG.
13A, 13B, and 13C are a cross-sectional view taken along the line DD ′, a cross-sectional view taken along the line EE ′, and a cross-sectional view taken along the line FF ′ in FIG. 12, respectively. .
14 is a process cross-sectional view illustrating the manufacturing method of the active matrix substrate shown in FIG. 1; FIG.
15 is a process cross-sectional view showing a process performed subsequent to FIG. 14. FIG.
16 is a process cross-sectional view showing a process performed subsequent to FIG. 15. FIG.
FIG. 17 is an explanatory view showing a corner portion of a conventional active matrix substrate.
18 is an explanatory diagram of a sealing material formation region around the scanning line driving circuit of the active matrix substrate shown in FIG. 17;
19A and 19B are a cross-sectional view taken along the line Q-Q 'and a cross-sectional view taken along the line RR' in FIG. 18, respectively.
[Explanation of symbols]
3b Lower layer side wiring of seal material formation area
4 First interlayer insulating film
6b Upper layer side wiring of sealing material formation area
7 Second interlayer insulating film
10 Substrate
21 Screen display area
22 Data line drive circuit
23 Scanning line drive circuit
60 TFT for pixel switching
64 Sampling drive signal line
65 Image signal sampling wiring
80 Reset drive circuit
85 capacitors
110 substrate groove
AM active matrix substrate
G gap material
Seal material containing GS gap material
GA sealant forming area
LP LCD device
OP Counter substrate
VID1 to VID6 Image signal lines
X data line
Y scan line

Claims (4)

A liquid crystal device in which a first substrate and a second substrate are bonded together with a sealing material, and liquid crystal is injected between the first and second substrates,
The first substrate includes a plurality of scanning lines, a plurality of data lines, a transistor provided corresponding to a region where the plurality of scanning lines and the plurality of data lines intersect, and the transistor A pixel electrode provided, a reset signal line for applying a reset potential prior to supply of an image signal to the plurality of data lines, and a constant potential wiring,
The extension portion of the reset signal line and the extension portion of the constant potential wiring overlap each other through a dielectric film in the seal material forming region, and the capacitor is formed on the first substrate. A liquid crystal device, wherein the liquid crystal device is disposed in a groove-like recess extending in the extending direction of the capacitor. The overlap of the extension portion of the reset signal line and the extension portion of the constant potential wiring is that the wiring is formed so that one of them overlaps the other through a contact hole formed in the dielectric film. The liquid crystal device according to claim 1. The extension portion of the reset signal line and the extension portion of the constant potential wiring are extended in a plurality, and each of them overlaps, and the recess is formed corresponding to each of the overlaps. The liquid crystal device according to claim 1. The first and second substrates are bonded with a sealing material, and liquid crystal is injected between the first and second substrates,
The first substrate includes a plurality of scanning lines, a plurality of data lines, a transistor provided corresponding to a region where the plurality of scanning lines and the plurality of data lines intersect, and the transistor A pixel electrode, a reset signal line for applying a reset potential prior to supply of an image signal to the plurality of data lines, and a constant potential wiring. And
A capacitor in which the extension portion of the reset signal line and the extension portion of the constant voltage wiring overlap with each other through the dielectric film in the seal material forming region is formed on the first substrate and extends in the extending direction of the capacitor. A method for manufacturing a liquid crystal device, comprising a step of forming a groove-shaped recess.

Images