JPH11168610A - Image processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an image processor that enables higher speed accessing than that of a high speed burst operation and employs a conventional memory that is less expensive than a line memory to realize cost reduction. SOLUTION: An image-processing section 102 receives image data subject to raster scanning by a scanner 101, writes the data to an optional address of a memory for each line of all pixles in a main scanning direction prior to image processing. In reading the image data, not every line of all the pixels but each block of the data is read consisting of a prescribed pixel number and a prescribed line number in the subscanning direction, and image processing is applied to each block. After the image processing, each block of the image data is written in an optional memory of the other memory, and in the case of reading the image data, the data are read by each line of all the pixels in the main scanning direction and outputted to a printer 103.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to an image processing apparatus, and more particularly, to an image processing apparatus such as a color copier, a color scanner, and a color printer for transferring a color image signal and performing image processing.

[0002]

2. Description of the Related Art When processing image data that has been raster-scanned by an image processing apparatus, when performing a filtering operation or a sub-scanning interpolation operation that refers to neighboring pixels in the sub-scanning direction, all of one line in the main scanning direction is required. Are prepared for a plurality of lines, and the arithmetic processing is performed with reference to the image data of the plurality of lines.

FIG. 10 is a block diagram of a conventional general system in which a color scanner processes RGB image data captured from a scanner device (not shown) and outputs the processed RGB image data to a color printer device (not shown). It is. The sub-scanning interpolation circuit 1001 obtains, by arithmetic processing, R image data and G image data that are aligned with the B image data among the RGB image data, and outputs the obtained data to the scanner γ unit 1002. The scanner γ circuit 1002 performs γ correction on each input image data and outputs the result to the masking processing circuit 1003. The masking processing circuit 1003 performs chromaticity coordinate conversion of the input additive RGB image data into a subtractive color digital image signal for recording colors,
004. The UCR processing circuit 1004 performs background removal processing and outputs the result to the gradation processing circuit 1005.
The gradation processing circuit 1005 performs scaling processing in the main scanning direction, printer γ correction processing, and the like, and outputs the result to the printer device.

FIG. 11 is a block diagram showing a configuration of a sub-scanning interpolation circuit 1001 in the image processing apparatus shown in FIG. The sub-scanning interpolation circuit 1001 performs sub-scanning interpolation processing of R image data and G image data in accordance with B image data. Therefore, the sub-scanning interpolation circuit 1 for the R image data
101, a sub-scanning interpolation circuit 1102 for G image data is provided. In addition, the sub-scanning interpolation circuit 1101 is provided with a line memory 1103 for a total of three lines in order to refer to image data for two lines before and after the image data for one line at the virtual position obtained by the interpolation calculation processing. Similarly, the sub-scanning interpolation circuit 1102 is provided with a line memory 1104 for a total of three lines. For B image data for which sub-scanning interpolation is not performed, a line memory 1105 for only one line is provided.

Each line memory has the same number of bits or more than the total number of pixels in the main scanning direction, and sequentially stores image data in raster scan pixel order in accordance with a write control timing signal. This is a FIFO (first-in, first-out) memory that sequentially outputs image data in the order of pixels written, that is, in the order of raster scan pixels in response to a read timing signal.

Although not shown, the smoothing filter in the masking processing circuit 1003 in FIG. 10 and the edge enhancement filter in the UCR processing circuit 1004 similarly have a plurality of lines each having a capacity of one line in the main scanning direction. Line memory is used.

[0007]

However, in the above-mentioned conventional image processing apparatus, a line memory having a higher unit cost per bit than a general-purpose memory is frequently used, so that there is a problem that the product cost is increased. Moreover, in recent years, the demand for higher image quality has become stronger, and it is necessary to process high-density pixels. For this reason, 1 in the main scanning direction
The number of pixels in the line also inevitably increases. Therefore, the price of the line memory corresponding to high image quality will rise,
As a result, there is a concern that the product cost will be further increased. On the other hand, demands for high-speed image processing apparatuses have been increasing, so that conventional line memories cannot support high-speed access.

The present invention has been made in view of the above, and it is an object of the present invention to realize a cost reduction by using a general-purpose memory which can be accessed at a high speed by a high-speed burst operation and is cheaper than a line memory. It is an object of the present invention to provide an image processing apparatus having the above configuration.

[0009]

According to a first aspect of the present invention, there is provided an image processing apparatus comprising: first storage means capable of writing raster-scanned image data at an arbitrary address; To 1 of all pixels in the main scanning direction.
Each line is written and stored in the first storage means, and the image data of a plurality of lines stored in the first storage means is stored in the predetermined number of pixels in the main scanning direction and the predetermined number of pixels in the sub-scanning direction. First storage control means for reading out each block consisting of the number of lines, and first storage control means
Image processing means for performing predetermined image processing on the image data for each block read from the storage means of the above, a second storage means capable of writing the image-processed image data to an arbitrary address, The image data processed by the means is written and stored in the second storage means for each block, and the image data stored in the second storage means is read out and output for every line of all pixels in the main scanning direction. And a second storage control means.

According to the image processing apparatus of the first aspect, before image processing, image data raster-scanned by an external device such as a scanner device has an arbitrary address for each line of all pixels in the main scanning direction. When reading out the stored image data by writing to a general-purpose first storage unit such as an SRAM which can be written to the memory, it is not a single line of all pixels but a predetermined number of pixels and a predetermined number of lines in the sub-scanning direction. Reading is performed for each block, and image processing is performed for each block. After image processing, an SRA capable of writing image data to an arbitrary address for each block
When writing to the general-purpose second storage means such as M and reading out image-processed image data, one pixel of all pixels in the main scanning direction is read.
The data is read out line by line and output to an external device such as a printer.

According to a second aspect of the present invention, an image processing apparatus comprises:
2. The image processing apparatus according to claim 1, wherein the image processing means has a line memory having at least the predetermined number of pixels and a predetermined number of lines for image processing for each block.

According to the image processing apparatus of the second aspect, image processing such as interpolation processing is performed in block units by the line memory.

According to a third aspect of the present invention, in the image processing apparatus according to the first or second aspect, the first and second storage means store the image data of all pixels in the main scanning direction and a predetermined number of lines in the sub scanning direction. It is characterized by having at least two or more bank areas for storing data, and wherein the first storage control means duplicately writes a predetermined amount of image data to the two bank areas.

According to the image processing apparatus of the third aspect,
In one bank area, a predetermined amount of the same image data such as one line of all pixels in the main scanning direction is redundantly written.

According to a fourth aspect of the present invention, there is provided an image processing apparatus according to the first aspect.
Or in 2, the first storage control means selects an arbitrary partial rectangular area out of the image data of the predetermined rectangular area formed by raster-scanning all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. Is written in the first storage means after inverting the image data in the main scanning direction.

According to the image processing apparatus of the fourth aspect, 1
Of the image data of a predetermined rectangular range such as a page, image data of an arbitrary partial rectangular range is written by inverting left and right, and partial mirror processing is performed.

According to a fifth aspect of the present invention, there is provided an image processing apparatus according to the first aspect.
Or in 2, the first storage control means is configured to execute an image of an arbitrary portion of the raster-scanned image data of a predetermined rectangular range including all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. It is characterized in that data is changed to image data other than raster-scanned image data.

According to the image processing apparatus of claim 5, 1
An editing process is performed to replace an arbitrary part of the image data of a predetermined rectangular range such as a page with another image data.

An image processing apparatus according to claim 6 is the image processing apparatus according to claim 1.
In any one of (a) to (d), the first storage control means includes
Outputting an effective image signal indicating that the image data read from the storage means is effective image data to the image processing means, and performing image processing according to the presence or absence of the effective image signal. .

According to the image processing apparatus of the present invention, when the image data before image processing is valid image data,
Image processing such as interpolation processing that refers to pixels on adjacent lines is performed. If the image data is not valid image data, image processing such as interpolation processing is not performed.

According to a seventh aspect of the present invention, there is provided the image processing apparatus according to the first aspect.
Or in 2, the first storage control means inverts, in the main scanning direction, image data of a predetermined rectangular range formed by raster-scanning all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. It is characterized by reading from the first storage means.

According to the image processing apparatus of claim 7, 1
The image data of a predetermined rectangular range such as a page is read by inverting left and right, and mirror processing is performed on the entire predetermined rectangular range such as one page.

[0023]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of an image processing apparatus according to the present invention will be described below with reference to FIGS. FIG. 1 is a block diagram of a system to which an image processing device according to the present invention is applied. The scanner device 101 outputs raster image scanned RGB image data for all pixels in the main scanning direction line by line. The image processing unit 102 receives the input RGB
Performs image processing on image data and prints CMY
The K image data is output to the printer device 103.

FIG. 2 is a block diagram showing the configuration of the image processing unit 102 in FIG. The CPU 201 includes a ROM 202 and a RAM 20 connected via a system bus.
3 and a command and data are exchanged with the image processing circuit to control the entire image processing unit 102. ROM20
Reference numeral 2 stores a program executed by the CPU 201, initial value data, and the like. The RAM 203 is a work area for storing data processed by the CPU 201.

The image processing circuit comprises first and second storage means, first and second storage control means for controlling the respective storage means, and image processing means for performing actual image processing. . Memory 204 (first storage unit)
Is a general-purpose memory which is composed of two bank areas, bank 1 and bank 2, and which can be written to an arbitrary address, for example, an SDRAM (synchronous DRAM). Memory control circuit 205 (first storage control means)
Controls the memory 204 to write and store the input RGB image data in the memory 204, read out the stored RGB image data from the memory 204, and output it to the image processing means.

The image processing means comprises a sub-scanning interpolation circuit 206, a scanner γ circuit 207, a masking processing circuit 208, a UCR processing circuit 209, and a gradation processing circuit 210, as shown in FIG. The sub-scanning interpolation circuit 206
An interpolation operation in the sub-scanning direction is performed on the RGB image data read from the memory 204 by the memory control circuit 205, and the image data thinned out at the time of scaling or image compression is interpolated and output to the scanner γ circuit 207. .

The scanner γ circuit 207 corrects the linear reflectance γ characteristic of the scanner device, converts the corrected linear γ characteristic into linear density image data, and outputs the image data to the masking circuit 208. The masking circuit 208 converts the additive RGB image data into the subtractive CMYK image data. That is, the image data is converted into Y (yellow), M (magenta), C (cyan), and K (black) YMCK image data of printable recording colors. This CMYK image data is UC
Output to the R processing circuit 209.

The UCR processing circuit 209 performs edge enhancement processing and other background removal processing on the YMCK image data, and outputs the processed data to the gradation processing circuit 210. Gradation processing circuit 2
Reference numeral 10 performs scaling processing in the main scanning direction, printer γ correction processing for adapting to the γ characteristic of the printer device, and dither processing, and outputs the image data from the image processing means to the memory control circuit 211.

The memory control circuit 211 (second storage control means) controls the memory 212 (second storage means) to write and store the input CMYK image data in the memory 212 and to store the stored CMYK image data. The image data is read from the memory 212 and output to the printer device 103. Similarly to the memory 204, the memory 212 is composed of two bank areas of a bank 1 and a bank 2, and is a general-purpose memory that can write to an arbitrary address, for example, an SDR.
AM.

Next, the configurations and functions of the memory control circuits 205 and 211 will be described. FIG. 3 is a circuit diagram showing a configuration of the memory control circuit 205 in FIG. The bank address control circuit 301 controls the bank 1 of the memory 204
And the read mode and the write mode of the bank 2 are controlled based on the input horizontal synchronization signal. The bank 1 address control circuits 302 and 303 are used to buffer the raster-scanned RGB image data.
And the address of bank 2 is transferred to bank address control circuit 3
Control is performed in accordance with the address control signal from address 01.

Multiplexer (MUX) circuits 304, 3
05 indicates the addresses of Bank 1 and Bank 2 and Bank 1
The address is switched to the address from the address control circuits 302 and 303 or the CPU address from the CPU 201. The multiplexer circuits 306 and 307 transfer the data of the banks 1 and 2 to the scanner R from the scanner device 101.
Switch to GB data or CPU data. These four
Multiplexer circuits 304, 305, 306, 30
The input selection 7 is switched by a CPU enable signal output from the CPU 201.

In the read mode, the multiplexer circuit 308 switches between bank 1 and bank 2 according to a bank switching signal from the bank address control circuit 301. 3
The state buffer 309 stores the CPU in the read mode.
Conduction is performed by a read signal (CPU-RD) from 201, and image data is output to a CPU data bus. In the write mode, the three-state buffers 310 and 311
It becomes conductive by a write signal from the bank address control circuit 301, and writes image data input from the multiplexer circuits 306 and 307 to the bank 1 and the bank 2.

FIG. 4 shows the processing order of the image data in the memory 204. FIG. 4A shows the processing in the write mode, and FIG. 4B shows the processing in the read mode. Since the write data to the banks 1 and 2 of the memory 204 in the write mode is raster-scanned image data, the image data of all pixels in the main scanning direction is sub-scanned as shown in FIG. The data is alternately input to the bank 1 and the bank 2 by N divided lines in the direction. On the other hand, in the read mode, as shown in FIG. 4B, in the sub-scanning direction, each block including a predetermined number of pixels divided into M in the main scanning direction and a predetermined number of lines in each bank in the sub-scanning direction. The reading of the image data is repeated. When the reading of one block is completed, the image data of the next one block in the same bank is read, and when the reading of the image data at the boundary of the bank is completed and all the image data of the bank are read, the next Is read out block by block.

FIG. 5 is a diagram showing the processing of one page of image data in the memories 204 and 212 in chronological order. First, image data for N divisions in the sub-scanning direction is input to the bank 1 of the memory 204 in the order shown in FIG. Next, image data for N divisions in the sub-scanning direction is input to the bank 2 of the memory 204 in the order shown in FIG.
The image data is read out in the order shown in FIG. This process is performed alternately on the banks 1 and 2 of the memory 204 until one page is completed. Memory 21
4B, image data for N divisions in the sub-scanning direction is input to the bank 1 in the order shown in FIG. Next, image data for N divisions in the sub-scanning direction is applied to the bank 2 in FIG.
Simultaneously with the input in the order shown in FIG. 4B, the image data is read from the bank 1 in the order shown in FIG. This processing is performed by the memory 212
Are performed alternately until one page is completed for banks 1 and 2.

In this case, in the vicinity of the bank switching line, as shown in FIG. 5, by inputting image data to the banks 1 and 2 at the same time, a predetermined amount of overlapping data is written to the two banks, The filter operation processing of the neighborhood is enabled.

The input speed of image data to the memory 204 depends on the output speed of the scanner device 101,
The output speed of the image data from the printer unit 103 depends on the image data processing speed of the printer device 103. However, the image processing speed in the image processing unit 102 is only required to be faster than the processing speed of the scanner device 101 and the printer device 103. When the image processing speed is sufficiently fast, the multiplexers 304, 305, and 30 shown in FIG.
6 and 307 are switched to the CPU data bus by the enable signal from the CPU 201,
01 enables image processing.

FIG. 6 is a circuit diagram showing the internal configuration of the bank 1 address control circuits 302 and 303 in FIG. The sequencer 601 includes the bank address control circuit 30
1 to process the command signal (CMD) to the memory 204 and the sub-scanning interpolation circuit 20.
6 and outputs an effective pixel signal (EN) for
A signal corresponding to the end of one burst access process is output to the block counter 302.

The block counter 602 has the sequencer 6
Counting the number of burst access processing from 01
The end of one divided line in the main scanning direction is detected, and a line end signal is output to a block address pointer 603. The end of one block is detected, and a block end signal is output to a start address pointer 604.

The start address pointer 604 holds a start pointer for setting a start address of a block to be accessed next, and the block counter 60
The stored start pointer is output to the block address pointer 603 in response to the block end signal from the block 2.

The block address pointer 603 outputs the address of the next line to be accessed according to the line end signal from the block counter 602, and accesses the next according to the signal of the start pointer from the start address pointer 604. Output block address.

The address counter 605 loads the address from the block address pointer 603 in response to the line end signal from the block counter 602, and outputs the address to the memory 204 as the address of the bank to be accessed.

Next, the operation of the bank 1 address control circuit 302 and the bank 2 address control circuit 303 shown in FIG. 6 will be described. FIG. 7 is a diagram showing an access order in an arbitrary bank of the memory 204 in the read mode for two blocks in the main scanning direction divided into M, and FIG. 7A shows an access order of the m-th block. FIG. 7B shows the access order of the next (m + 1) th block. In the write mode, the input of the image data to the memory 204 is incremented from the address “0” according to the pixel clock and in the main scanning direction. However, in the read mode, since access is performed for each of the blocks divided into M, the read address is not continuous, but is a discrete address for each line.

Now, it is assumed that the pointer indicating the start address of the m-th block set in the address counter 605 from the block address pointer 603 is a. At this time, the start address pointer 604 holds a pointer a ′ obtained by adding the difference b to the pointer a as the start address of the next m + 1 block. Moreover,
The difference b has a value smaller than the number of pixels in one line of the block (address difference d).

In FIG. 7A, when reading of the first line is completed, a line end signal is output from the block counter 602 to the block address pointer 603.
As for the address set in the address counter 605, the start address of the second line of the same m block is set by adding c to the pointer a. Each time the reading of one line of the m-th block is completed, the start address of the next line is set and the reading starts. When reading of the last line of the m-th block is completed, a block end signal is output from the block counter 602 to the start address pointer 604, and the held pointer a 'is changed to the block address pointer 60.
Set to 3.

Therefore, as shown in FIG.
The predetermined amount of image data at the beginning of one line of the +1 block is read out overlapping with the image data at the end of one line of the m block. This overlapping data is the same for all lines of the block. That is, at the boundary between adjacent blocks, a predetermined amount of image data is read redundantly. Therefore, by managing the parameters a, b, c, and d, it becomes possible to perform overlapping processing on neighboring pixels at the block boundary also in the main scanning direction. Also, depending on the presence or absence of an effective pixel signal generated by the sequencer 601, only effective pixels can be processed even when effective pixels are not continuous.

As described above, according to the above embodiment, the image data raster-scanned by the scanner device 101 can be written to an arbitrary address for each line of all pixels in the main scanning direction before image processing. SRA
When the image data written and stored in the general-purpose memory 204 such as M is read, the image data is read not for one line of all pixels but for each block including a predetermined number of pixels and a predetermined number of lines in the sub-scanning direction. The image processing is performed for each of them. After the image processing, the image data is written to a general-purpose memory 212 such as an SRAM which can write the image data at an arbitrary address for each block, and when the image-processed image data is read, the image data is read for each line of all the pixels in the main scanning direction. And outputs it to an external device such as a printer. Therefore, S which enables high-speed access by high-speed burst operation
Using a general-purpose memory such as a RAM, the raster-scanned image data can be arbitrarily image-processed, and the cost can be reduced by using a general-purpose memory that is cheaper than the line memory.

According to the above embodiment, when the image data before the image processing is the effective image data, the image processing such as the interpolation processing referring to the pixels of the adjacent line is performed.
If it is not valid image data, no image processing such as interpolation processing is performed. Therefore, when a buffer memory such as a DRAM or an SDRAM is used, even when the memory is burst-accessed, a signal indicating valid pixel data is generated in synchronization with the image data by an image processing circuit including a plurality of stages. In addition, image processing can be performed by operating the image processing circuit only when valid image data is output. Further, when a buffer memory such as a DRAM or an SDRAM is used, high-speed operation is enabled.

Further, according to the above-described embodiment, it is also possible to read out image data of a predetermined rectangular range such as one page by inverting left and right, and perform mirror processing on the entire predetermined rectangular range such as one page. Therefore, it is possible to perform the full-page mirror processing in units of one page.

Next, a modification of the embodiment will be described with reference to FIGS. FIG. 8 is a circuit diagram showing a configuration of a bank 1 address control circuit and a bank 2 address control circuit in a modification. FIG. 9 is a diagram showing a configuration of one page of image data in a modification, in which image data of an area 901 of a dashed portion within an arbitrary partial rectangular range is displayed in a reversed manner in the main scanning direction. In FIG. 8, the block counter 602 and the block address pointer 60 within the broken line
3, and the start address pointer 604,
The configuration is the same as that shown in FIG.
05 is an up-down counter. The newly added circuit is a circuit for inverting the image data in the area 901. However, since this modification corresponds to only random access, not burst operation, the sequencer 601 shown in FIG. 6 is unnecessary. Y start register 801, Y end register 802, X start register 803, and X end register 804
Store the Y start address, Y end address, X start address, and X end address of the area 901 respectively.

The sub-scanning counter 805 counts the Y address output from the address counter 605, and inputs the Y start address and the Y end address from the Y start register 801 and the Y end register 802. During the period up to the end address, the enable signal is generated and the main scanning counter 80 is generated.
6 is output. The main scanning counter 806 is activated by an enable signal from the sub-scanning counter 805, counts the X address output from the address counter 605, and sets the X start register 80.
A trigger signal is generated and output when an X start address is input from 3. The 3-state buffer 807 outputs the X end address input from the X end register 804 in response to a trigger signal from the main scanning counter 806.

The multiplexer circuit 808 inputs a trigger signal from the main scanning counter 806 to one input A, and inputs a line end signal from the block counter 602 to the other input B. The multiplexer circuit 809 includes:
The X end address from the buffer 807 is input to one input A, and the address from the block address pointer 603 is input to the other input B. In these two multiplexer circuits 808 and 809, the input A is selected in the write mode and the input B is selected in the read mode by the switching signal R / W. The count mode switching flip-flop 810 is a toggle switch that switches the count mode of the address counter 605 when receiving a trigger signal from the main scanning counter 806 at the T input. The initial value counter mode is set to the up-count mode. Therefore, in the read mode, the trigger signal is not output from the main scanning counter 806, so that the mode is always the up-count mode.

Next, the operation of this modified example will be described with reference to FIGS. Now, the Y start address 801, the Y end address 802, the X start register 803, and the X end register 804 are stored in the area 901 in FIG.
e, X start address Xs and X end address X
It is assumed that e is set.

In the write mode, the sub-scanning counter 8
05 counts the Y address and the count value is Ys
Then, an enable signal is output. Then, the main scanning counter 806 counts the X address, and when the count value reaches Xs, gives a trigger signal to the buffer 807, the input A of the multiplexer circuit 808, and the flip-flop 810. Therefore, the buffer 807 is supplied to the address counter 605 via the multiplexer circuit 809.
To the address counter 60 via the multiplexer circuit 808.
5 is input as a load signal. At the same time, the flip-flop 810 inverts the counter mode.

As a result, in FIG. 9, when the writing in the sub-scanning direction proceeds and the Y address becomes Ys, the main scanning counter 806 becomes active. Then, when the X address in the main scanning direction becomes Xs by writing pixels in order from the left end of the page to the right, the X address jumps and Xe is output from the address counter 605. Then, the address counter 605 is inverted to the down mode, and the writing in the main scanning direction is inverted from right to left. Thereafter, when the X address returns to Xs again, the X address jumps, and Xe is output from the address counter 605. In this case, the address counter 605 returns to the up mode, and writing in the main scanning direction is performed in a regular order from the left to the right end from the pixel of Xe.

When the writing of one line in the main scanning direction is completed, the Y address is incremented, and the writing of the next one line is performed in the same manner. Y address is Y
At e, the enable signal of the sub-scanning counter 805 stops. Therefore, since the main scanning counter 806 becomes non-active, inverted writing is not performed and normal writing is performed.

According to the above modification, image data of an arbitrary partial rectangular range among image data of a predetermined rectangular range such as one page is written by inverting left and right, and partial mirror processing is performed. Therefore, complicated image processing becomes possible.

Further, as an application of the above-described modified example, it is also possible to adopt a configuration in which an editing process for replacing an arbitrary portion of image data of a predetermined rectangular range such as one page with another image data is performed. Therefore, a special image pattern or the like can be added to the image data without preparing dedicated hardware.

Note that the memories 204 and 212 in the above-described embodiment and its modifications are used when image data from the scanner device 101 is image-processed and output to the printer device 103. A work area for displaying reduced RGB image data for image editing on a display unit of a color copier, or a method for developing print data from a host into a bitmap and printing when a connection means with a host is provided. It can also be used as a work area for the printer controller.

[0059]

According to the first aspect of the present invention, image data raster-scanned by an external device such as a scanner device is converted into an arbitrary address for each line of all pixels in the main scanning direction before image processing. SR that can be written to
When writing and reading the stored image data in the general-purpose first storage means such as the AM, the image data is read not for one line of all pixels but for each block including a predetermined number of pixels and a predetermined number of lines in the sub-scanning direction. , Image processing is performed for each block. After the image processing, the image data is written into a general-purpose second storage unit such as an SRAM capable of writing the image data at an arbitrary address for each block, and when the image-processed image data is read, all the pixels in the main scanning direction are read. The data is read out line by line and output to an external device such as a printer. Therefore, using a general-purpose memory such as an SRAM that can be accessed at a high speed by a high-speed burst operation, the raster-scanned image data is arbitrarily processed, and the cost is reduced by using a general-purpose memory that is cheaper than the line memory. it can.

According to the second aspect of the present invention, image processing such as interpolation processing is performed in block units by the line memory. Therefore, by reducing the capacity of the line memory used for image processing, a large-scale image processing circuit compatible with high image quality can be mounted inside semiconductor components, and the semiconductor part on which the image processing circuit is mounted is changed. Without changing the capacity of the buffer memory, it is possible to easily provide a high pixel density and provide an image processing apparatus capable of achieving high image quality.

According to the third aspect of the present invention, a predetermined amount of the same image data, for example, one line of all pixels in the main scanning direction is redundantly written in two bank areas. Therefore, it is possible to perform a filter operation process or the like that needs to refer to the neighboring pixels, and it is possible to perform image processing without any trouble even at a division boundary of a block which is a unit of image processing.

According to the fourth aspect of the present invention, image data of an arbitrary partial rectangular range among image data of a predetermined rectangular range such as one page is written by inverting left and right, and partial mirror processing is performed. Therefore, image processing by complicated image editing becomes possible.

According to the fifth aspect of the present invention, an editing process for replacing an arbitrary portion of image data of a predetermined rectangular range such as one page with another image data is performed. Therefore, a special image pattern or the like can be added to the image data without preparing dedicated hardware.

According to the invention of claim 6, when the image data before image processing is valid image data, image processing such as interpolation processing referring to pixels on adjacent lines is performed.
If it is not valid image data, no image processing such as interpolation processing is performed. Therefore, when a buffer memory such as a DRAM or an SDRAM is used, even when the memory is burst-accessed, a signal indicating valid pixel data is generated in synchronization with the image data by an image processing circuit including a plurality of stages. In addition, image processing can be performed by operating the image processing circuit only when valid image data is output. Further, when a buffer memory such as a DRAM or an SDRAM is used, high-speed operation is enabled.

According to the seventh aspect of the present invention, image data in a predetermined rectangular range such as one page is read by inverting left and right, and mirror processing is performed on the entire predetermined rectangular range such as one page. Therefore, it is possible to perform the full-page mirror processing in units of one page.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system to which an image processing device according to the present invention is applied.

FIG. 2 is a block diagram illustrating a configuration of an image processing unit in FIG. 1;

FIG. 3 is a circuit diagram showing a configuration of two memory control circuits in FIG. 2;

FIG. 4 shows a processing order of image data to a memory;
(A) is a process in the write mode, and (B) is a process in the read mode.

FIG. 5 is a diagram showing the processing of image data for one page in a time-series manner.

FIG. 6 is a circuit diagram showing an internal configuration of two bank 1 address control circuits of FIG. 3;

7A and 7B are diagrams illustrating an access order of two blocks in a read mode, wherein FIG. 7A illustrates an access order of an m-th block and FIG. 7B illustrates an access order of an (m + 1) -th block.

FIG. 8 is a circuit diagram showing a configuration of a bank 1 address control circuit and a bank 2 address control circuit in a modification.

FIG. 9 is a diagram illustrating a configuration of image data of one page in a modified example.

FIG. 10 is a block diagram of a general system for processing and outputting RGB image data in a conventional image processing apparatus.

11 is a block diagram showing a configuration of a sub-scanning interpolation circuit in the conventional image processing device of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Scanner device 102 Image processing unit 103 Printer device

Claims (7)

[Claims] A first storage unit capable of writing raster-scanned image data at an arbitrary address; and writing the image data into the first storage unit for each line of all pixels in the main scanning direction. A first method of storing and reading out image data for a plurality of lines stored in the first storage means for each block including a predetermined number of pixels and a predetermined number of lines in the sub-scanning direction among the total number of pixels in the main scanning direction. Storage control means, image processing means for performing predetermined image processing on the image data of each block read from the first storage means by the first storage control means, and an image processed image A second storage unit capable of writing data to an arbitrary address; and the image data processed by the image processing unit in the second storage unit for each of the blocks. And second storage control means for reading out and outputting the image data stored in the second storage means for each line of all pixels in the main scanning direction. Image processing device. 2. The image processing device according to claim 1, wherein the image processing unit has at least the bit number of the predetermined number of pixels and has a line memory of the predetermined number of lines for image processing for each of the blocks. 2. The image processing device according to 1. 3. The first and second storage units have at least two or more bank areas for storing image data of a total number of pixels in a main scanning direction and a predetermined number of lines in a sub-scanning direction. 3. The image processing apparatus according to claim 1, wherein the first storage control unit writes a predetermined amount of image data in two bank areas in a redundant manner. 4. The image processing apparatus according to claim 1, wherein the first storage control unit is configured to perform any part of the raster-scanned image data of a predetermined rectangular range including all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. The image processing apparatus according to claim 1, wherein image data in a rectangular range is written in the first storage unit after being inverted in a main scanning direction. 5. The image processing apparatus according to claim 1, wherein the first storage control unit is configured to perform any part of the raster-scanned image data in a predetermined rectangular range including all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. 3. The image processing apparatus according to claim 1, wherein the image data is changed to image data other than the raster-scanned image data. 6. The image processing means, wherein the first storage control means outputs to the image processing means a valid image signal indicating that the image data read from the first storage means is valid image data. The image processing apparatus according to any one of claims 1 to 5, wherein image processing is performed according to the presence or absence of the effective image signal. 7. The first storage control means inverts, in the main scanning direction, image data of a predetermined rectangular range formed by raster-scanning all pixels in the main scanning direction and a predetermined number of lines in the sub-scanning direction. 3. The image processing apparatus according to claim 1, wherein the image data is read from the first storage unit.