JPH11134817A - Digital pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a digital PLL circuit capable of expanding a lock range and a capture range and switching a method for controlling the oscillation frequency of a VCO. SOLUTION: A speed detection circuit A55 detects deviation of the input rate by using signals 3T to 11T, then expresses the input rate in seven stages, and switches the freerunning frequency of a PLL clock generation circuit 54. A speed detection circuit B56 detects the signal 11T and detects how much its width is deviated from a standard value. An output of the speed detection circuit A55 or B56 is selected by a switch 57 in accordance with the quantity of distortion of the input rate and is supplied to a control signal output section 58. Then, a control signal is supplied to a VCO 60 through a low-pass filter 59.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital PLL.
Regarding the circuit, in particular, EFM (Eight to Fourtee) such as a compact disc (CD) or a mini disc (MD)
n Modulation) digital PLL circuit as used to reproduce the signal.

[0002]

2. Description of the Related Art As described in, for example, JP-A-1-303630 and JP-A-3-212860, a reproduction PLL circuit for a CD or MD is disclosed in
Generally, a phase difference between an input signal and a PLL clock signal generated by the PLL circuit is converted into a voltage, and the frequency is changed by using a voltage-frequency conversion circuit to achieve synchronization. Further, a digital PLL circuit digitized according to the same principle is proposed in Japanese Patent Application Laid-Open No. 3-289820.

[0003] The applicant of the present invention has disclosed in Japanese Patent Application Laid-Open No. 8-7024.
No. 9 proposes a digital PLL circuit that does not require a VCO element or an analog circuit, but has limitations on a capture range and a lock range. Here, the lock range means a range in which the PLL circuit keeps locking against the above-mentioned transfer rate shift in the locked state, and the capture range indicates a state in which the PLL circuit is locked from the unlocked state to the above-mentioned transfer rate shift. Means the range that can be shifted to Here, locking means that the EFMI signal is
When latching at the rising edge of LLCK, the PLLCK is set so that the width of EFMI (3T to 11T) can be correctly determined.
Is performed.

[0004]

The MD is an audio device characterized by its small size and light weight. It is often used in a portable manner, and a system for minimizing power consumption and extending battery life appears as an inevitable demand. Come. The MD is premised on a system having a buffer memory called a shock proof memory, and it is possible to read out the data at a constant rotation speed by using this. This is more advantageous in terms of power consumption than reading at a constant linear velocity. Because the recording is performed at a constant linear velocity, if the reading method is performed at a constant linear velocity, it is necessary to increase the rotation speed toward the inner circumference of the disk. This is because a current for accelerating and decelerating flows through the spin motor when a difference in the number of revolutions occurs and the inner and outer circumferences are frequently accessed.

[0005] If the number of rotations is constant, current for acceleration and deceleration does not flow through the spin motor, and power consumption can be reduced accordingly. However, keeping the number of rotations constant means that the linear velocity of reading changes about twice, and the lock range and capture range of the PLL need to be wider accordingly. Japanese Unexamined Patent Publication No. Hei 8-7024
The digital PLL circuit proposed in Japanese Patent Publication No. 9 does not require a VCO element or an analog circuit, but is based on a CLV system with a constant reading speed from a disk. Difficult due to lack of lock range and capture range.

SUMMARY OF THE INVENTION Therefore, a main object of the present invention is to provide a digital PLL circuit capable of expanding a lock range and a capture range and switching a method for controlling an oscillation frequency of a VCO.

[0007]

The invention according to claim 1 is
The phase difference between the clock signal obtained by dividing the master clock signal generated by the VCO oscillation circuit and the input signal is measured, and the ratio of the frequency division is controlled based on the phase difference. Digital PLL for synchronization
The circuit includes input rate measuring means for measuring the rate of the input signal, and control means for controlling the input voltage of the VCO oscillation circuit based on the value of the measured rate.

[0008] In the invention according to claim 2, a plurality of input rate measuring means of claim 1 are provided, and further, a selecting means for selecting any of the plurality of input rate measuring means is provided.

According to a third aspect of the present invention, one of the plurality of input rate measuring means of the second aspect measures a length from an edge of an input signal to an edge, and generates a master signal generated by a VCO oscillation circuit. The deviation amount from the reference value based on the clock signal is accumulated for a specific period, and the rate of the input signal is calculated from the value.

According to a fourth aspect of the present invention, one of the plurality of input rate measuring means of the second aspect measures a length from an edge of an input signal to an edge thereof, and measures only the longest possible pulse width. And calculates the rate of the input signal from the amount of deviation from the reference value based on the master clock signal generated by the VCO oscillation circuit.

In the invention according to claim 5, the control means according to claim 3 or 4 includes one of the plurality of input rate measuring means.
According to the result of the rate of the input signal calculated by the
A first level when the input rate is higher than a reference value based on a master clock signal generated by the oscillation circuit, a second level when the input rates are equal, and a third level when the input rates are lower.
Output value signal.

In the invention according to claim 6, the ternary signal output from the control means is converted into an analog voltage to
Includes a low-pass filter provided to the CO oscillation circuit.

In the invention according to claim 7, the plurality of input rate measuring means of claim 4 operate even when one of the means is selected as the means for controlling the input voltage of the VCO oscillation circuit.

In the invention according to claim 8, the selection means of claim 2 selects the longest pulse width from edge to edge of the input signal as the input rate.

In the ninth aspect of the present invention, the selecting means of the second aspect has a hysteresis characteristic when switching from one of the plurality of input rate measuring means to the other and from the other to one.

[0016]

FIG. 1 is a block diagram of one embodiment of the present invention. In FIG. 1, a signal read from MD disk 51 is applied to RF signal processing circuit 52, where a waveform equalization process is performed. Thereafter, the processed signal is supplied to the slice circuit 53 and is converted into a digital binary EFM signal. This EFM signal is supplied to the PLL clock generation circuit 54, the speed detection circuit A55, and the speed detection circuit B5.
6 and given.

The PLL clock generation circuit 54 generates a PLL clock signal synchronized with the EFM signal, and the speed detection circuit A55 detects an input rate shift (speed shift) using signals from 3T to 11T. The speed detection circuit A55 indicates the input rate in seven stages, and the PLL clock generation circuit 5
4 is switched. PLL clock generation circuit 5
4 and the specific operation of the speed detection circuit A55 will be described later in detail.

The speed detection circuit B56 detects an 11T signal, and detects a deviation of the input rate by detecting how much the width deviates from the standard value. VCO
The control signal output unit 58 outputs an “H” level (increases the VCO oscillation frequency) and an “L” level (VCO) based on the speed detection output of the speed detection circuit A55 or B56.
Lower the oscillation frequency), high impedance state (VC
(O oscillation frequency hold).

The output of the speed detection circuit A 55 and the output of the speed detection circuit B 56 are selected and supplied to the input of the VCO control signal output unit 58 by the switch 57. The cause of the selection depends on the result of the speed detection circuit B56, but it is determined which is to be selected according to the deviation amount of the input rate. This will be described later in detail. The output signal of the VCO control signal output unit 58 is supplied to the VCO 60 via a low-pass filter (LPF) 59.

FIG. 2 is a flowchart for explaining a specific operation of the speed detection circuit 56 shown in FIG.
According to the flowchart shown in FIG. 2, the speed detection circuit B56 detects the signal of 11T, counts the width thereof,
By comparing with the reference 11T length obtained from the CO oscillation frequency, it is determined whether the VCO oscillation frequency is higher or lower than the input rate. More specifically, in step (abbreviated as SP in the figure) SP1, a timer for counting time is reset and initialized. In step SP2, the width of the EFM signal is counted. In other words, MCK / 4 (M
CK is counted by the VCO oscillation frequency). MCK /
The standard length of the clock signal 4 is 22 in the 11T signal.

In step SP3, in step SP2
Hold the maximum value while comparing the results counted by. The holding of the maximum value is performed during the time T1 of step SP4. During the period of T1, the value is set so that a plurality of 11T signals come. The minimum value among the maximum count values held in step SP5 is obtained. This is to remove very long input signals such as burst errors. In this case as well, a period comparison is performed in step SP6 so that a plurality of comparisons are performed.

In steps SP7 and SP8, the obtained count value of the most probable 11T MCK / 4 clock is compared with 22. If the count value is larger than 22, a decision to reduce the VCO oscillation frequency is made in step SP7. If the count value is smaller than 22, a decision is made in step SP8 to increase the VCO oscillation frequency. If the count value is equal to 22, the oscillation frequency of the VCO is held.

FIG. 3 is a block diagram showing the configuration of the PLL clock generation circuit and the speed detection circuit A55 shown in FIG. 1. FIG. 4 is a time chart showing the timing of the master clock signal MCK, the EFMI signal, and the PLL clock signal. FIG. 5 is a time chart showing the timing of the EFMI signal and the PLL clock signal.

Next, the PLL clock generation circuit 54 and the speed detection circuit A55 shown in FIG. 1 will be described in detail with reference to FIGS. The speed detection circuit A55 includes speed detection circuits 2 and 3 and a jitter detection circuit 4 as shown in FIG. Then, the PLL clock generation circuit 54
Generates a PLL clock signal as a synchronous clock from a reproduced EFM signal from a CD or MD. Where EF
The M signal is a signal having a width of 3T to 11T, where EF
The input rate of the M signal is a normal speed (transmission rate = 2.0
If 3Mbit / s), then 1T = 236.2 [nSEC] MCK = 33.8688 [MHz] The length of 1T is 8 clocks of MCK. MCK is V
It shows the oscillation frequency of the CO, and this numerical value is a value that changes in proportion to the input rate. For example, when the input rate is half the normal rate, 1T = 472.4 [nSEC] MCK = 16.9344 [MHz], and when the input rate is twice the normal rate, 1T = 1118 [nSEC]. MCK = 67.7376 [MHz]. That is, the oscillation frequency of the VCO is controlled so as to satisfy 1T · MCK ≒ 8.0 (A).

The master clock signal MCK and the EFM signal are externally applied to the PLL clock generation circuit 54. Then, the PLL clock generation circuit 54 is configured as shown in FIG.
4C is generated from the master clock signal MCK shown in FIG. 4C, and the PLL clock signal is generated by synchronizing the PLL clock signal with the EFM signal shown in FIG.
Adjust the width of the LL clock signal.

That is, the PLL clock generation circuit 54
Counts the time of the ↓ edge of the PLL clock signal generated by dividing the normal master clock signal MCK by 8 from the edge (↑ or ↓) of the EFM signal. Based on this count value (Te in FIG. 4C), the "H" level section of the PLL clock signal in section 3 is corrected. By this operation, the phase shift amount shown in FIG. 4C is reduced. Here, Tc / Te is called a phase correction gain.

The PLL clock generation circuit 54 detects a disc rotation speed deviation, and performs a phase correction other than the above-described phase correction.
The L clock signal is corrected to widen the lock range, and based on speed deviation detection data from the speed detection circuits 2 and 3 used during rough servo, as shown in FIG.
The average frequency of the PLL clock signal is changed in proportion to the rotational speed deviation by changing the width of N pulses among the PLL clock signals.

The speed detection circuits 2 and 3 detect the speed deviation by counting the pulse width of the EFM signal using the master clock signal MCK. EFM signal is 30 ns
Each signal of 3T to 11T has an offset with respect to the theoretical value if the respective signals are averaged. This seems to be manifested by the equalizing properties. In the embodiment shown in FIG. 3, in consideration of these, the determination of 3T to 11T is performed by counting the time from edge to edge, and the deviation amount of the determined signal from the width at the normal speed is detected. In addition, 3
The speed deviation is calculated from the added value of the detected deviation amount when 768 (300 Hex) T is added by adding T to 11T.

The jitter detection circuit 4 includes speed detection circuits 2 and 3
From the pulse width of the EFM signal obtained by the above, only 3T is extracted, and the magnitude of the signal variation is determined based on how many out of 1024 pulses enter the value of the width within a certain range set by the microcomputer.

FIG. 6 is a specific block diagram of the PLL clock generation circuit 54 shown in FIG. In FIG. 6, the counters 11 and 12 and the selector 13 correspond to the EFMI signal and the PL.
The counter 11 detects the phase difference from the L clock signal, and the counter 11 detects the phase difference between the time when the EFMI signal rises from the “L” level to the “H” level and the time when the PLL clock signal falls to the “L” level. The clock signal MCK is counted, and the counter 12 counts the master clock signal MCK during a period from when the EFMI signal falls from “H” level to “L” level until the PLL clock signal falls to “L” level. The phase difference between the EFMI signal and the PLL clock signal is detected, and the phase difference between the EFMI signal and the PLL clock signal is detected. The phase difference detected by each of the counters 11 and 12 is provided to the selector 13.

The selector 13 selects the output of the counter 11 while the EFMI signal is at the “H” level, and selects the output of the counter 12 while the EFMI signal is at the “L” level. The selected phase difference is given to tables 14 and 15 and converted into data for correcting the PLL clock signal by these tables 14 and 15. That is, the tables 14 and 15 indicate whether the input of the VCO control signal output unit 58 in FIG.
Alternatively, it is used properly depending on whether it is from the speed detection circuit B56.

The table 14 is used when the control of the VCO is based on rough speed detection, for example, when the deviation of the rotation speed from the transfer rate is about ± 6% or less, and the table 15 is used for controlling the VCO. Is used, for example, for a fine servo whose rotational speed deviation from a standard transfer rate is about ± 1% or less. Therefore, the table 14 stores the correction data in advance, and shifts the relationship between the phase difference and the correction data according to the speed data (A5 to A8) given from the speed detection circuit 3 with the gain fixed at 1/3. I do.

The VCO based on the speed detection circuit B56
, The EFM input rate fluctuates up to about ± 6%. The table 15 stores six kinds of gains according to the quality of the EFMI signal, and is switched by a phase servo gain switching setting signal provided from the speed detection circuit 3. First, when a signal of 1.5 T or less is input, a reproduction error due to fingerprints or the like is determined. When a phase correction prohibition input from the speed detection circuit 2 occurs, data that is not corrected is output.

The outputs of the tables 14 and 15 are supplied to the selector 16
Given to. The selector 16 responds to a table control signal such as rough servo / fine servo from the speed detection circuit 3,
The outputs of the tables 14 and 15 are selected and given to the PLL clock generator 18. The PLL clock generator 18 generates a PLL clock signal based on the output of the selector 16, and the free-running frequency control circuit 17
4, the frequency and timing of correcting the PLL clock signal to the PLL clock generator 18 are controlled.

FIG. 7 is a specific block diagram of the speed detection circuit 2 shown in FIG. 3, and FIG. 8 is a diagram for explaining the operation of the speed detection circuit 2 of FIG.

Referring to FIG. 7, pulse width counters 21 and
2 is supplied with an EFMI signal and a master clock signal MCK. The pulse width counter 21 counts the width of the EFMI signal at the falling edge of the master clock signal MCK,
The pulse width counter 22 counts the width of the EFMI signal at the rising edge of the master clock signal MCK. Outputs of these pulse width counters 21 and 22 are supplied to a table circuit 23. The table circuit 23 has a function of invalidating the pulse width of the EFMI signal from the pulse width counters 21 and 22 which cannot determine which pulse, that is, any one of 3T to 11T. For example, when the range of the speed deviation is ± 6%, 3T to
The width of each signal of 11T becomes larger as the signal becomes wider.

Here, the thick solid line shown in FIG. 8 indicates the width of fluctuation of the signal of each length, and the areas A to D are different when the speed deviation is large in the + direction and when the speed deviation is large in the-direction. The matching T signal is a region of values that can take any of them.
That is, when a signal having a width included in the area D is detected, it is a 10T signal with a speed deviation in the negative direction (slow) or a signal of 11T in which the speed deviation is large in the positive direction (fast). Can not be determined whether or not is detected. If this is treated as either 10T or 11T, a large error occurs in speed detection. Therefore, the table circuit 23 defines a hatched invalid area and outputs a special output (code FFhex). However, if the area is not the invalid area, the signal input to the table circuit 23 is output as it is.

The output of the table circuit 23 is supplied to the 768T counter 24 and to the speed detection circuit 3 as signal width information indicating the amount of deviation. The table circuit 23 outputs an EFM count pulse at each of the "H" level and the "L" level of the EFMI signal.
If the I signal is a pulse in an invalid area, it is masked and applied to the speed detection circuit 2 as an EFM count pulse (removal of the dead zone) as a clock signal for adding the deviation amount of the block width. In addition, since there is no pulse shorter than 3T, when a very thin EFMI signal is input, a phase correction prohibition signal for prohibiting phase correction is also generated and output to the phase control circuit 1.

FIG. 9 is a specific block diagram of the speed detection circuit 3 shown in FIG. In FIG. 9, the shift adder 31
Is supplied with signal width information, an EFM pulse count signal, and a 768 count end signal from the speed detection circuit 2. Then, the shift adder 31 adds the signal width information, and determines how much the speed shift amount is based on the sum of the shift amounts at the end of 768 counts. The added value of the shift adder 31 is given to the speed table 32.
The speed table 32 stores seven types of speeds in advance in order to extend the capture range for locking. The speeds are switched according to the added value of the shift adder 31, and the speed data is stored in the table with the phase control circuit 1 and the table. To the fixed variable switching circuit 33.

The table fixed variable switching circuit 33 switches the table between variable and fixed, and is mainly used for switching from rough servo to fine servo. This corresponds to the switching signal of the switch 57 in FIG.
Is switched by a switching signal given from the microcomputer via the.

The jitter detection circuit 4 shown in FIG. 3 extracts only 3T signals from the signal width information given from the speed detection circuit 2, and counts the number of signals equal to the value set by the microcomputer and the number of the entire 3T. The magnitude of the jitter is determined from the ratio. In one embodiment of the present invention, the VC is controlled so that the 3T signal has no jitter and the relationship between the EFM input rate and the master clock signal MCK satisfies the above-described equation (A).
When O is controlled, if the signal width of 3T is counted by the master clock signal MCK, about 24 counts are obtained.

The microcomputer normally sets a set value "24", and it is determined that the more 3T signals equal to 24, the smaller the jitter. When the numerical value equal to 24 is repeatedly increased and decreased with a certain period, it can be determined that the disk is eccentric. The microcomputer switches the phase servo gain of the phase control circuit based on this information. Usually, the gain is smaller as the jitter is larger, and it is better to increase the gain as the disk is eccentric.

FIG. 10 is a diagram showing changes in the average frequency of the PLL clock signal, FIG. 11 is a diagram showing points at which the table is switched, and FIG.
FIG. 3 is a diagram illustrating a width of an L clock signal.

As shown in FIG. 10, there are seven types of changes in the average frequency of the PLL clock signal, A to G. Switching between A to G determines the speed deviation by counting the pulse width of the input signal. Switching is performed at the point of the speed deviation where the tables A to G shown in FIG. 11 overlap. Each of the tables A to G is stored in the speed table 32 shown in FIG. In the tables of A to G, for example, only the tables of A and G have a large gain. For example, the gains of A and G are set to ／ and the others are set to ＝.
Increasing the gain increases the capture / lock range. Instead, playback errors may be exacerbated. The A and G tables are normally used in the VCO shown in FIG.
This is only when the input of the control signal output unit 58 is the output of the speed detection circuit B56, and it is more effective to prioritize the capture / lock range even if the error slightly worsens.

As described above, according to this embodiment, since the relationship (gain) between the phase difference and the frequency division ratio is made variable, the lock range / capture range can be expanded without increasing the number of tables. In addition, since all signals of 3T to 11T are used, accurate speed detection can be performed. Further, the digital PLL circuit according to one embodiment of the present invention can be completely constituted by a logic circuit, and can be highly integrated in an LSI.

Further, in the above-described embodiment, the pulse width of the PLL clock signal is counted, and the deviation from the standard transfer rate of the PLL clock signal, that is, the rotational speed deviation of the disk is detected. The average frequency can be changed by changing the circumference ratio.

Further, by reading the judgment of the signal quality from the jitter detecting circuit 4, the microcomputer can change the set value of the frequency division ratio, thereby enabling automatic adjustment.

According to the present invention, by measuring the pulse width of the PLL clock signal, the EFM signal becomes 3T.
１１11T, and the two results obtained by detecting the deviation of the EFM signal from the standard transfer rate are added, and the sum of the deviation amounts is added to the discrimination results of 3T〜11T. By dividing by a value, a deviation from the standard transfer rate of the PLL clock signal can be detected. This will be described in detail below.

The edges from the edge of the EFM signal are counted at both edges of the master clock signal MCK, and the deviation from the theoretical value, which would be detected at normal speed, is converted into the frequency deviation. A method of averaging times is conceivable.

The width of nT (n = 3 to 11) is obtained by changing the rotation speed. Width = nT / N (n = 3 to 11, N = [Ratio to 1-time rotation speed]) _Nn = N / 2nT (1) The amount of frequency fluctuation from normal (1 × speed) time is

[0051]

(Equation 1)

In an actual circuit, f _Nn is measured and f
Treat _1n as a constant. A sufficiently large number of times M is added to remove variations due to quantization errors and jitter, and the average value is regarded as a frequency shift. That is,

[0053]

(Equation 2)

Here, assuming that M is a sufficiently large value, from the above equation (2),

[0055]

(Equation 3)

And

[0057]

(Equation 4)

Therefore, from equation (3),

[0059]

(Equation 5)

When NT has no offset amount, N can be obtained correctly. However, the actual EFM signal has n
There are different amounts of offset depending on T. This is considered to be caused by variations in the bit length during reproduction of the disc and the characteristics of the RF amplifier. That is, the first (1)
As a result of the expression (5), the expression (6) results.

[0061]

(Equation 6)

Then,

[0063]

(Equation 7)

The equations corresponding to the equations (3) and (4) are the following equations (8).

[0065]

(Equation 8)

The term N · ΔT _n (N) / n · T of the denominator works as an error. From the above description, in the present invention,
First, when an nT signal has an offset of ΔT _n (N),

[0067]

(Equation 9)

If T _Nn is added by a shift adder 31 for a sufficiently large value M samples,

[0069]

(Equation 10)

Is as follows. Therefore, from equation (10),

[0071]

[Equation 11]

In the present invention, the denominator is truncated at M of 768T, and N is obtained from the value of the numerator at that time. In this method, no error in speed detection due to ΔT _n (N) appears.

FIG. 13 shows 1T according to an embodiment of the present invention.
6 is a time chart when a non-existent signal such as 2T is input. As shown in FIG.
If the FMI signal is a signal that is not originally present, such as 1T due to noise, even though the FMI signal is actually 7T, a phase correction inhibition signal is output as shown in FIG. Adverse effects can be reduced.

FIG. 14 shows the speed detection circuits A and B shown in FIG.
FIG. 15 is a diagram showing characteristics of 55 and 56, and FIG. 15 is a diagram showing a state transition of the switch 57 and the VCO control signal output unit 58 shown in FIG.

The operating range of the speed detection circuit A55 is shown in FIG.
The speed can be detected in the range of the input rate of ± 5%. Beyond this range, for example, 10T is determined to be 9T or 11T, and a correct result cannot be obtained.

On the other hand, the detection range of the speed detection circuit B56 is much wider than that of the speed detection circuit A55, and is -50% to + 2%.
The detection range is about 00%. FIG. 15 shows how the switch 57 is switched using this characteristic. Initially, if the frequency of the VCO does not match the input rate and the result of the speed detection circuit B56 exceeds ± 5%, VC
The O-locking state is set, and the switch 57 is switched to the b side as an input of the VCO control signal output unit 58, and the state 61 in FIG. 15 is set.

When the frequency of the VCO approaches the frequency corresponding to the input rate, the result of the speed detection circuit B56 falls within the range of ± 2%. Then, the state becomes the state 62 in FIG. 15, the switch 57 is switched to the a side, and the output of the speed detection circuit A55 is input to the VCO control signal output unit 58. as a result,
The PLL clock generation circuit 54 can be locked to the input signal. This state indicates a state in which the reproduction of the MD is sent stably. In this state, a search or the like is performed. When the result of the speed detection circuit B56 exceeds the range of ± 5% again, the state 61 is set again. The difference between the transition conditions between the states 63 and 64 is that when the state of the pull-in completion in the state 64 is narrowed and the state 62 is being reproduced, the PLL is securely locked. In this case, there is no need to make a transition to the state 61 within the range in which the speed detection circuit A55 operates.

As described above, according to this embodiment, the PL
The L circuit itself uses the variable frequency clock of the VCO oscillation circuit 60 as a reference clock and controls the VCO oscillation frequency according to the input rate of the EFM signal. To measure the input rate, the speed detection circuit B56 measures the width of the 11T signal, which is a sector sync signal, and measures the amount of deviation from the 11T width based on the current reference clock.
55, the deviation from the width of 3T to 11T based on the reference clock having the width of 3T to 11T is measured, and these outputs are switched by the switch 57 and supplied to the VCO control signal output unit 58. Although the speed detection circuit B56 is inferior to the speed detection circuit A55 in accuracy, it can measure an input rate in a wide frequency range, and the speed detection circuit A55 is inferior to the speed detection circuit B56 in a measurable frequency range. Highly accurate measurement is possible.

Therefore, the output of the speed detection circuit B56 is selected until the operation of bringing the oscillation frequency of the VCO close to the input rate of the signal, and the output of the speed detection circuit B56 is adjusted to a range that can be measured sufficiently by the latter method.
When the frequency of CO approaches, the output is switched to the output of the speed detection circuit A55. The former method operates even when the latter method is employed, detects that a difference between the input signal and the VCO oscillation frequency has occurred in the latter measurement range, and switches the control of the VCO by the former method. . As described above, even if the input rate changes continuously or discontinuously, the PLL can be followed in a wide range of the input rate.

[0080]

As described above, according to the present invention, the rate of an input signal is measured, and V is determined by the value of the measured rate.
Since the input voltage of the CO oscillation circuit is controlled, the lock range and the capture range can be expanded.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital PLL circuit according to an embodiment of the present invention.

FIG. 2 is a flowchart for explaining an operation of a speed detection circuit B56 shown in FIG.

FIG. 3 is a block diagram showing a configuration of a PLL clock generation circuit and a speed detection circuit A shown in FIG.

FIG. 4 shows master clock signal MCK, EFMI signal and P
5 is a time chart showing timing with an LL clock signal.

FIG. 5 is a time chart showing timings of an EFMI signal and a PLL clock signal.

6 is a specific block diagram of the PLL clock generation circuit shown in FIG.

7 is a specific block diagram of the speed detection circuit 2 shown in FIG.

FIG. 8 is a diagram for explaining the operation of the speed detection circuit 2 of FIG. 7;

9 is a specific block diagram of the speed detection circuit 3 shown in FIG.

FIG. 10 is a diagram showing a change in an average frequency of a PLL clock signal.

FIG. 11 is a diagram showing points for switching tables.

FIG. 12 is a diagram illustrating a width of a PLL clock signal to be input and corrected.

FIG. 13 shows 1T to 2T in an embodiment of the present invention.
5 is a time chart when a non-existent signal is input.

FIG. 14 is a diagram showing characteristics of the speed detection circuits A and B shown in FIG.

FIG. 15 is a diagram showing a state transition of a switch 57 and a VCO control signal output unit 58 shown in FIG. 1;

[Explanation of symbols]

 2,3,55,56 Speed detection circuit 4 Jitter detection circuit 11,12,21,22 Counter 13,16 Selector 14,15 Table 17 Self-running frequency control circuit 18 PLL clock generator 23 Table circuit 24 768T counter 31 Shift addition Device 32 speed table 33 table fixed variable switching circuit 34 microcomputer interface 51 MD 52 RF signal processing circuit 53 slice circuit 54 PLL clock generation circuit 57 switch 58 VCO control signal output section 59 LPF 60 VCO oscillation circuit

Claims (9)

[Claims] 1. The method according to claim 1, wherein a phase difference between a clock signal obtained by dividing a master clock signal generated by a VCO oscillation circuit and an input signal is measured, and a ratio of the division is controlled based on the phase difference. In a digital PLL circuit for synchronizing an input signal and the clock signal, an input rate measuring means for measuring a rate of the input signal; and an input voltage of the VCO oscillation circuit based on a value of the rate measured by the input rate measuring means. A digital PLL circuit comprising control means for controlling the operation of the digital PLL. 2. The digital PLL circuit according to claim 1, wherein a plurality of said input rate measuring means are provided, and further comprising a selecting means for selecting one of said plurality of input rate measuring means. 3. One of the plurality of input rate measuring means measures a length from an edge to an edge of the input signal, and is based on a master clock signal generated by the VCO oscillation circuit. 3. The digital PLL circuit according to claim 2, wherein a deviation amount from a reference value is accumulated for a specific period, and a rate of the input signal is calculated from the value. 4. One of the plurality of input rate measuring means measures the length of the input signal from edge to edge, and extracts only the longest possible pulse width,
3. The digital PLL circuit according to claim 2, wherein a rate of the input signal is calculated from an amount of deviation from a reference value based on a master clock signal generated by the VCO oscillation circuit. 5. The control means according to a result of a rate of an input signal calculated by one of the plurality of input rate measuring means, based on a master clock signal generated by the VCO oscillation circuit. 5. A signal according to claim 3, wherein a ternary signal of a first level is output when the input rate is higher than the reference value, a second level is output when the input rate is equal to the reference value, and a third level is output when the input rate is lower than the reference value. Digital PLL circuit. 6. The control circuit according to claim 3, further comprising:
6. The digital PLL circuit according to claim 5, further comprising a low-pass filter that converts a value signal into an analog voltage and supplies the analog voltage to the VCO oscillation circuit. 7. The apparatus according to claim 4, wherein said plurality of input rate measuring means operate even when one of the means is selected as a means for controlling an input voltage of said VCO oscillation circuit. A digital PLL circuit according to claim 1. 8. The digital P according to claim 2, wherein said selecting means selects the longest pulse width from edge to edge of the input signal as an input rate.
LL circuit. 9. The digital signal processing system according to claim 2, wherein said selecting means has a hysteresis characteristic when switching from one of said plurality of input rate measuring means to the other and from the other to one. PLL circuit.