JP2001135038A - Pll circuit and data reader - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit which is adaptive to the change of the frequency of an input signal without enlarging the range of the oscillation frequency of an oscillator. SOLUTION: The PLL circuit is provided with a phase comparator, a first charge pump(CP), a first low pass filter(LPF), a second voltage current converter (V/I converter), a frequency comparator, second CP, second LPF, a second V/I converter, a current adder, a current controlled oscillator (ICO), a frequency divider, a frequency counter measuring the period of the output signal of ICO based on a reference block and frequency division judgment circuit varying the frequency dividing value of the frequency divider so that the PLL circuit is locked in the oscillation frequency range of the oscillator based on the measured result of the frequency counter.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to a PLL (Phase L
More particularly, the present invention relates to a PLL circuit suitable for generating a clock signal synchronized with a signal read from a recording medium.

[0002]

2. Description of the Related Art In an apparatus for reproducing data from a recording disk on which information is recorded by a digital recording method, when reading data recorded on the recording disk using a data reading clock as a reproduction clock, A PLL circuit is used to synchronize the data with a data reading clock.

FIG. 12 is a diagram showing an example of the configuration of a conventional data reading device (reproducing device). Referring to FIG. 12, an optical head 402 that reads data from a recording disk 401, and an amplifier (preamplifier) 404 that generates a reproduction RF signal, a focus error signal, and a tracking error signal from the data read from the optical head 402.
A filter circuit (equalizer) 406 that removes noise and equalizes the waveform of the reproduced RF signal from the amplifier 404;
A binarizing circuit 407 for binarizing the F signal into "1" and "0"
And a clock (RDC) synchronized with the binarized data
K) a PLL circuit 408 for generating (also referred to as "data read clock" or "data clock"), a decoder (demodulation circuit) 409 for demodulating data, and an error correction circuit 410 for correcting an error in reproduced data. A CPU 411 for controlling the whole, a disk motor 403 for driving the recording disk 401 to rotate, and a servo controller 40 for controlling the optical head 402 and the disk motor 403
5 is provided.

FIG. 11 is a diagram showing an example of a configuration of a PLL circuit 408 used in the data reading device shown in FIG.

Referring to FIG. 11, this PLL circuit comprises:
A current controlled oscillator (current controlled oscillato) that outputs a signal of a predetermined frequency according to the input control current
r; also referred to as “ICO”) 110 and current-controlled oscillator 1
A frequency divider 111 for dividing the frequency of the signal output from 10 into 1 / N and outputting it as a data read clock (RDCK); a synchronization detection pattern (sync pattern) in the data signal read from the recording disk; , Frequency divider 1
Data read clock (RDC
K), a phase comparator 101 for comparing the phases with each other, converting the phase signal into a pulse signal having a width corresponding to the phase error between the two, and outputting
First charge pump (CP) 102 that converts a pulse signal output from phase comparator 101 into a voltage and outputs the voltage
A first low-pass filter (LPF) 103 that blocks high-frequency components from a voltage signal output from the first charge pump 102 to block noise, and converts an output voltage of the first low-pass filter 104 into a current value. Using the first voltage-to-current converter 104, the synchronization detection pattern in the data signal read from the recording disk, and the data read clock output from the frequency divider 111, the frequency error of the data read clock with respect to the data signal And a frequency comparator 105 for converting the pulse signal into a pulse signal having a width corresponding to the frequency error and outputting the pulse signal.
A second charge pump (CP) 106 that converts a pulse signal output from the second into a voltage and outputs the voltage, and a second that cuts off high frequency components from the voltage signal output from the second charge pump 106 to cut off noise. Low-pass filter (L
PF) 107 and a second voltage-current converter 108 that converts the output voltage of the second low-pass filter 107 into a current value.
And a current adder (combiner) 10 for combining and outputting the output currents of the first and second voltage-current converters 104 and 108
And the current added by the current adder 109 is
The current is input to the current control oscillator 110 as a control current.

In the PLL circuit shown in FIG. 11, a frequency comparator 105, a second charge pump 106, a second
Low-pass filter 106, second voltage-current converter 10
8, adder 109, current controlled oscillator 110, frequency divider 11
In one loop, the frequency is synchronized by detecting a frequency error based on a synchronization pattern (sync pattern) read from the recording disk. When the frequency is synchronized, the phase comparator 101 and the first In the loop of the charge pump 102, the first low-pass filter 103, the first voltage-to-current converter 104, the current adder 109, the current control oscillator 110, and the frequency divider 111, the data reading clock and the input signal (EFM signal) Is performed.

That is, from the current control oscillator 110,
A signal having a frequency and a phase that is somewhat close to the clock of the data recorded on the recording disk is output.
11, the frequency is divided by 1 / N (in this case, the frequency division value (also referred to as the "frequency division ratio" is N)), and the data read clock (RD)
CK) and the data read clock (RDCK) output from the frequency divider 111
1 and is fed back to the frequency comparator 105.

The frequency comparator 105 detects a frequency error of the data read clock for the data signal using the synchronization detection pattern read from the recording disk, and outputs a voltage value based on the detected error to the second charge pump 106. From the second low-pass filter 10
7, the voltage from which the high-frequency component has been cut is converted into a current by the second voltage-current converter 108, added by the adder 109, input to the current control oscillator 110 as a control current, and Then, a signal of a predetermined frequency is output based on the input control current.

After a signal of a predetermined frequency is generated by the current control oscillator 110, the phase comparator 101 uses the synchronization detection pattern of the data signal read from the recording disk to detect the phase error of the data read clock with respect to the data signal. Is detected, a voltage corresponding to the detected phase error is output from the first charge pump 102, and the first
Low-pass filter 103, first voltage-current converter 10
4 and converted into a current by the current adder 109.
The current added to the current from the voltage-current conversion circuit 108 is input to the current control oscillator 110 as a control current,
The current control oscillator 110 generates a data read clock that is in phase with, ie, synchronized with, the data signal read from the recording disk.

[0010] By the above-described series of operations, synchronization control of data read clock (RDCK) with respect to data recorded on the recording disk is performed.

In the recording disk, in order to control the synchronization between the data recorded on the recording disk and the data reading clock, a sync pattern is provided for each frame, for example, as schematically shown in FIG. And
On CD-ROM, EFM (Eight to Fourteen Modul
ation; 8-14 conversion modulation) signal system, DVD (Digital)
Versatile Disk) uses an EFMplus code.

In the EFM signal system, FIG.
As shown in the figure, the sync pattern has a maximum inversion interval (11
T: T is a signal having a channel bit length of two consecutive times, and the data signal is equal to or less than “11T” depending on the pit length and the pit interval of the recording disk. From the fall to the next fall is measured, and if the measured value is “22”, it is determined that the pattern is a sync pattern.

On the other hand, in the EFMplus signal system, for example, as shown in FIG.
And a signal having an inversion interval of 4T and “1” continues 9 times during 18T of one cycle of the sync pattern.
9T + 9T where "0" lasts 9 times and "1" lasts 10 times,
Since there is a possibility that a data signal such as 10T + 8T in which "0" is repeated eight times thereafter is also included, the data reading clock is used to measure from the rising edge of the signal to the next rising edge or from the falling edge to the next falling edge, and the measurement is performed. Even if the value is “18”, it cannot be immediately determined to be a sync pattern. For this reason, the data read clock measures the signal from rising to falling or from falling to rising, and when the measured value is “14”, the data reading clock measures the subsequent signal from rising to falling. Furthermore, the frequency error is detected based on the measurement result.

According to the data read clock, EFM
From the rise to the fall of the plus signal, or from the fall to the rise, the measured value is "1".
In the case other than "4", pulse signals having mutually different widths based on the measured values are output as frequency error signals. On the other hand, when the measured value becomes “14”, the data reading clock measures until the subsequent rise or fall of the signal, and based on the measurement result, pulse signals having different widths are output as frequency error signals. The output frequency error signal is converted into a voltage by the second charge pump 106, and is passed through the second low-pass filter 107, the second voltage-to-current converter 108, and the current adder 109 to control the current. Is supplied to the current control oscillator 110, and a signal of a predetermined frequency is output.

[0015] From the rise to the fall or from the fall to the rise of the EFMplus signal, the measured value is "14". When the measured value is "14", the measured value until the subsequent rise or fall of the signal is "4". In this case, the frequency error signal outputs a center value, and the frequency of the data read clock and the frequency of the EFMplus signal are synchronized.

After the frequency error signal outputs the center value and the frequency of the data read clock and the frequency of the EFMplus signal are synchronized, the output current value from the second voltage-current converter 108 is used as an offset current, and the phase comparator 10
1, the phase error is detected by the edge comparison between the data read clock and the EFMplus signal, and the first low-pass filter 103 and the first voltage-current converter 10
4. The data read clock and E are controlled by the loop of the current adder 109, the current control oscillator 110 and the frequency divider 111.
The pull-in operation is performed so that the phase of the FMplus signal is synchronized (locked). At this time, the frequency division value of the frequency divider 111 is fixed to the value at the time of frequency synchronization. FIG.
2, FIG. 13 and the like are referred to the description of Japanese Patent Application No. 10-18856 (not disclosed at the time of filing of the present application), which is a patent application filed by the present applicant.

Incidentally, the rotation of the recording disk is determined by the CLV
(Constant Linear Velocity; constant linear velocity) CLV servo control is performed. Music CD (comp
In a reproducing apparatus for reproducing actdisk), the rotational speed of the disk is relatively low, and the rotational speed difference at a position in the radial direction of the disk is small. That is, the frequency range of the data clocks on the inner and outer circumferences of the CD is not large. For this reason,
For example, after adjusting the CLV speed at a new address position after the seek, the PLL circuit 408 pulls in the data read clock for the EFM signal, and the time until the lock state is not so long, and the seek time is not so long. There is no significant effect.

[0018]

Recently, in order to increase the transfer rate of a CD-ROM, a DVD or the like used as a storage medium of an information processing device, a rotational speed such as 4 ×, 8 ×, 16 ×, or 32 × is used. At high speed.

The recording disk is a CAV (Constant Angu
lar Velocity (rotation speed is constant), for example, in the case of a 12 cm disk, the linear velocity on the outer periphery is 2.5 times the linear velocity on the inner periphery. As an example, in the case of 8 × speed CAV, as shown in FIG.
The data read clock is 83.712M on the inner circumference.
Hz and 209.28 MHz on the outer circumference, and the frequency divider 1
When the division value (division ratio) of 11 is fixed to, for example, “1”,
The current control oscillator 110 operates between the inner circumference and the outer circumference.
A five-fold oscillation frequency range is required.

In this case, since the clock rate of the data read clock (RDCK) changes while the frequency division value of the frequency divider 111 is fixed, the oscillation frequency range of the current control oscillator 110 is widened (for example, f _max / f _min = 2.5 times or more).

The reason is that when the oscillation range of the current control oscillator 110 is narrow (ie, when f _max / f _min = 2.5 or less), the clock frequency read from the recording disk exceeds the oscillation range of the oscillator. This is because the PLL does not lock.

As a PLL circuit for generating a clock synchronized with a read signal read from a recording disk in a short time, for example, Japanese Patent Application Laid-Open No. H10-69733 discloses an EMF signal read from a recording disk using a reference clock to adjust the frequency. There has been proposed a configuration in which a voltage value corresponding to a measured value is measured and added to an output of a loop filter and supplied as a control voltage to a voltage controlled oscillator to vary an oscillation frequency of the voltage controlled oscillator. As described above, the configuration described in JP-A-10-69733 is designed to widen the oscillation frequency range of the voltage-controlled oscillator.

However, if the variable range of the oscillation frequency of the current control oscillator 110 is increased in order to expand the variable frequency range of the PLL circuit, it is extremely difficult to construct an oscillator with guaranteed linearity.

Then, for example, at the lower limit of the frequency variable range, the inverter constituting the ring oscillator of the current controlled oscillator 110 is no longer inverted and the current controlled oscillator 110
Can even occur when stopping the oscillation.

On the other hand, in a PLL circuit using a current-controlled oscillator having inferior linearity, the data read clock is
It becomes difficult to correctly phase-lock the FM signal.

Further, when the frequency variable range of the current controlled oscillator of the PLL circuit is expanded, there is a problem that the pull-in time of the PLL circuit increases.

In order to expand the variable frequency range of the PLL circuit, the PLL circuit is provided with a plurality of voltage controlled oscillators having different center frequencies, and a selector selects one of the voltage controlled oscillators. For example, JP-A-6-10
No. 4748 has proposed this. However, such a configuration causes an increase in circuit scale and current consumption, and is not a practically preferable configuration.

The frequency divider 111 of the PLL circuit is of a variable type, and the CPU 41 of the data reading device (reproducing device) is used.
1 (see FIG. 12), or when the frequency division ratio of the frequency divider 111 is set by software control executed by a computer of a higher-level device to which the data reading device is connected, a PLL lock is issued from the software side. In this case, the oscillation frequency cannot be directly viewed, and the optimum frequency division value cannot be directly set for the frequency divider 411.

For this reason, at the time of reading from the recording disk 401, when an error that cannot be corrected occurs continuously over a plurality of blocks in the error correction circuit 410 (when a burst error occurs), the frequency divider 411 separates By changing the frequency value, the data is re-read (retry processing), and thus the setting of the frequency value of the frequency divider is tried until the data can be read.

However, such software control is inefficient because the access time becomes longer and the software burden increases.

Also, for example, Japanese Patent Application Laid-Open No. 7-303042 discloses a PLL frequency synthesizer which can reduce the overshoot of the frequency change timing and perform high-speed frequency switching, such as a phase comparator, a loop filter, a voltage controlled oscillator, and a variable frequency oscillator. In a PLL circuit provided with a frequency divider, a counter for inputting the output of a voltage controlled oscillator and counting the number of waves, a register for holding the output of the counter, and data for comparing the value of the register with the frequency of the storage circuit A comparator and an arithmetic unit are provided. First, a frequency division number that outputs a frequency lower than the target frequency is instructed to the variable frequency divider, and when the output of the voltage controlled oscillator reaches a predetermined frequency, the variable frequency A configuration is disclosed in which the frequency division number is changed to the frequency division number instructed to the frequency divider, and the frequency division number is set according to the target frequency. The configuration described in Japanese Patent Application Laid-Open No. 7-303042 is such that the output signal of the voltage controlled oscillator is directly counted by a counter, and it is only determined whether or not a predetermined count value has been reached.

Therefore, the present invention has been made in view of the above problems, and has as its object to provide a PLL circuit and a PLL circuit capable of responding to a change in the frequency of an input signal without expanding the range of the oscillation frequency of the oscillator. An object of the present invention is to provide a data reading device provided with a PLL circuit. Other objects, features, advantages and the like of the present invention will be immediately apparent to those skilled in the art from the following description.

[0033]

SUMMARY OF THE INVENTION In order to achieve the above object, the present invention provides an oscillator whose oscillation frequency is varied according to a control voltage or control current according to the output of a phase comparator. In a PLL circuit for feedback input to a phase comparator via a frequency divider and detecting a phase difference from an input signal, the frequency division of the frequency divider is performed in accordance with a measurement result of the cycle of the input signal or the output of the oscillator. It is provided with means for variably setting a value.

According to the present invention, there is provided a current control oscillator for inputting a control current and generating and outputting a clock signal having a frequency corresponding to the control current, a frequency dividing value being variably set, and dividing a clock signal from the current control oscillator. A frequency divider, an input signal and a clock signal output from the frequency divider, and a phase comparator for outputting a voltage corresponding to a phase difference between these signals; and the input signal and the frequency divider. And a clock signal output from the frequency divider, and detects a frequency error by measuring a synchronization pattern of the input signal with the clock signal output from the frequency divider, and outputs an error voltage corresponding to the frequency error. A frequency comparison unit, a first low-pass filter receiving an output voltage from the phase comparison unit as an input, a second low-pass filter receiving an output voltage from the frequency comparison unit as an input, A first voltage-to-current conversion circuit that converts the output voltage of the low-pass filter into a current, a second voltage-to-current conversion circuit that converts the output voltage of the second low-pass filter to a current, A current value output from the voltage-current conversion circuit and the current value output from the second voltage-current conversion circuit are combined, input as a control current of the current control oscillator, and measure a frequency of an output signal of the current control oscillator. A frequency dividing circuit that, based on the measurement result of the frequency measuring circuit, varies a frequency dividing value of the frequency divider so that a PLL circuit is locked within an oscillation frequency range of the oscillator.

[0035]

Embodiments of the present invention will be described. Referring to FIG. 1, in a preferred embodiment of the present invention, a phase comparator (1) for inputting an input signal (IN) to one input terminal and an output voltage of the phase comparator (1) are input. Low-pass filter ("loop filter")
(2), a voltage-controlled oscillator (VCO) whose oscillation frequency is variably set based on the output voltage of the loop filter (2) (3), and a voltage-controlled oscillator (3). ), And a frequency divider (4) for dividing the output signal of the phase comparator (1) and supplying the divided signal to another input terminal of the phase comparator (1). The frequency divider (4) can variably set the frequency division value. A frequency measuring circuit (5) for counting the length of one cycle of the input signal; and an input signal frequency based on the measurement result of the frequency measuring circuit (5). A frequency division determining circuit (6) for determining a frequency division value and varying the frequency division value of the frequency divider.

In a second preferred embodiment of the present invention, referring to FIG. 2, a frequency measuring circuit (5) for counting the length of one cycle of the output of the voltage controlled oscillator (3); A frequency division determining circuit (6) that determines a frequency division value of the frequency divider based on the measurement result of the frequency measurement circuit (5) and varies the frequency division value of the frequency divider.

In each of the above embodiments, the voltage controlled oscillator (3) includes a voltage / current converter (31) for inputting the output voltage of the loop filter (2) and converting it into a current, and a voltage / current converter (31). And a current control oscillator (32) for inputting the current output as a control current.

Referring to FIG. 3, a third embodiment of the present invention is an embodiment in which the present invention is applied to a PLL circuit that generates a clock synchronized with a read signal read from a recording disk or the like. Voltage-controlled oscillator (11) for generating and outputting a clock signal having a frequency corresponding to the control voltage
6), the frequency division value is variably set, and the voltage-controlled oscillator (1
Frequency divider (111) for dividing the clock signal from (16)
And a phase comparator (phase comparator 101 and charge pump 102) which receives an input signal and a clock signal output from the frequency divider (111) as inputs and outputs a voltage corresponding to the phase difference between these signals, The input signal and a frequency divider (111)
A frequency comparison unit (frequency) that detects a frequency error by measuring a synchronization pattern of the input signal with a clock signal from the frequency divider, and outputs an error voltage corresponding to the frequency error. A comparator 105 and a charge pump 106) and a phase comparison unit (101, 102)
A first low-pass filter (103) that receives an output voltage from the first comparator, and a second low-pass filter (10) that receives an output voltage from the frequency comparators (105, 106).
7), and a voltage adder (115) for adding the output voltage of the first low-pass filter (103) and the output voltage of the second low-pass filter (107). The output voltage of 115) is input as a control current of the current controlled oscillator (116), and is output to a frequency measurement circuit (117) for measuring the output cycle of the voltage controlled oscillator (116) and a measurement result of the frequency measurement circuit (117). Based on the oscillator (1
And a frequency dividing determination circuit (113) for varying the frequency of the frequency divider (111) so that the PLL circuit is locked within the oscillation frequency range of 16). In the third embodiment, the voltage-controlled oscillator (3) may be configured to include a voltage-current converter and a current-controlled oscillator that inputs a current output from the voltage-current converter as a control current. Good.

Further, in a fourth embodiment of the present invention, FIG.
A current control oscillator that applies the present invention to a PLL circuit that generates a clock synchronized with a read signal read from a recording disk or the like, and generates and outputs a clock signal having a frequency corresponding to an input control current (110) and a frequency divider (1) that divides the clock signal from the current control oscillator (110) with the frequency division value variably set.
11), a phase comparison unit (101, 102) which receives an input signal and a clock signal output from a frequency divider (111) and outputs a voltage corresponding to a phase difference between these signals.
And an input signal and a clock signal from the frequency divider (111), and a frequency error is detected by measuring a synchronization pattern of the input signal with the clock signal from the frequency divider (111). A frequency comparing section (105, 106) for outputting an error voltage corresponding to the frequency error, a first low-pass filter (103) receiving an output voltage from the phase comparing section (101, 102) as an input, Department (10
5, 106) and a first low-pass filter (1).
03) a first voltage-current conversion circuit (104) for converting the output voltage into a current, and a second low-pass filter (107)
A second voltage-to-current conversion circuit (108) for converting the output voltage of the first
4) and the second voltage-current conversion circuit (1).
08) is added as the control current to the current control oscillator (110). And
As a frequency measurement circuit, a frequency counter (11) that counts the period of the output signal of the current control oscillator (110) based on the reference clock from the reference clock generation circuit (114)
2), and based on the measurement result of the frequency counter (112), within the oscillation frequency range of the oscillator (110), the PLL
A frequency division determining circuit (113) that varies the frequency value of the frequency divider (111) so as to lock the circuit is provided.

[0040]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention;

FIG. 1 shows a PL according to a first embodiment of the present invention.
FIG. 3 is a diagram illustrating a configuration of an L circuit. Referring to FIG. 1, a PLL circuit according to a first embodiment of the present invention corresponds to a phase comparator 1 for inputting an input signal (IN) to one input terminal and a phase difference detected by the phase comparator 1. A low-pass filter (also referred to as a “loop filter”) 2 for cutting high-frequency components from an output voltage to be changed, and a voltage-controlled oscillator (VCO) whose oscillation frequency is variably set based on the output voltage of the low-pass filter 2
3 and a frequency divider 4 for dividing the output signal of the voltage controlled oscillator 3 and supplying the divided signal to another input terminal of the phase comparator 1. The frequency divider 4 has a divided value (divided value " 1 ") can be set variably, and further, a frequency measuring circuit 5 for measuring the period of the input signal, and a frequency dividing value of the frequency divider being varied based on the measurement result of the frequency measuring circuit 5 Frequency division determination circuit 6
And the frequency division value of the frequency divider 4 is variably set according to the frequency of the input signal (IN).

The frequency measuring circuit 5 is a frequency divider (not shown) built in the frequency measuring circuit 5, and a frequency (1) of the signal obtained by dividing the input signal (IN) from the rising edge to the next rising edge. Period), or a period from one falling edge to the next falling edge (one period), by counting a reference clock (not shown),
The pulse count of the reference clock corresponding to the cycle is obtained, and the frequency is measured.

Alternatively, the frequency measurement circuit 5 is turned on for one cycle from the rising edge of the input signal (IN) to the next rising edge, or for one cycle from the falling edge to the next falling edge. The capacitor is charged with the current from the constant current source via the switch, and the terminal voltage of the capacitor at the elapse of one cycle is subjected to A / D (analog / digital) conversion. You may comprise so that a numerical value may be calculated | required. The configuration of the frequency measurement circuit 5 will be described later in detail.

The frequency dividing judgment circuit 6 calculates a frequency dividing value which becomes a lockable oscillation frequency from the oscillation frequency range of the voltage controlled oscillator 3 based on the measured frequency of the input signal. Set the value automatically.

The PLL circuit according to the first embodiment of the present invention is used, for example, in a circuit for extracting a clock from an input signal, and when the frequency range of the input signal (IN) ranges from f to 8f, for example. By setting the frequency range of the voltage controlled oscillator 3 to 4f to 8f and setting the frequency division value of the frequency divider 4 to 1 (no frequency division), 2 and 4, the phase can be synchronized with the frequency range from 8f to f. Become. That is, a voltage controlled oscillator having an oscillation frequency range of f to 8f is not required,
It suffices to provide a voltage-controlled oscillator having an oscillation frequency range of 4f to 8f.

FIG. 2A is a diagram showing the configuration of the second embodiment of the present invention. The second embodiment of the present invention differs from the configuration of the first embodiment shown in FIG. 1 in that the frequency measuring circuit 5 measures the period of the output signal of the voltage controlled oscillator 3. I have.

The frequency measuring circuit 5 converts the output of the voltage controlled oscillator 3 into one period from a rising edge of a signal obtained by dividing the frequency of the signal by a frequency divider (not shown) incorporated in the frequency measuring circuit 5 to the next rising edge, or By counting a reference clock (not shown) during one cycle from the falling edge to the next falling edge, a pulse count of the reference clock corresponding to one cycle is acquired, and the frequency is measured.
Alternatively, the frequency measurement circuit 5 is controlled via a switch that is turned on for one cycle from the rising edge of the input signal to the next rising edge or for one cycle from the falling edge to the next falling edge. A capacitor corresponding to one cycle of the output of the voltage controlled oscillator 3 is obtained by charging the capacitor with a constant current from the current source and performing A / D (analog / digital) conversion of the terminal voltage of the capacitor after one cycle. You may comprise so that a numerical value may be calculated | required.

The frequency division determining circuit 6 determines the current frequency division value of the frequency divider 4 and the voltage controlled oscillator 3 measured by the frequency measuring circuit 5.
The frequency of the input signal is obtained from the frequency of the output of the voltage control oscillator 3, the frequency dividing value that becomes the lockable oscillation frequency is obtained from the oscillation frequency range of the voltage controlled oscillator 3, and the frequency dividing value of the frequency divider 4 is automatically set.

In the second embodiment of the present invention, similarly to the first embodiment, the frequency range of the voltage controlled oscillator 3 is
It is not necessary to correspond to the entire range of the input signal frequency, and in a part of the range, the phase can be synchronized over the entire range of the input signal frequency.

In the first and second embodiments,
As shown in FIG. 2B, a voltage controlled oscillator (VCO) 3
Is a voltage-current converter (V / I converter) 31 for converting the output voltage of the low-pass filter 2 into a current, and a current-controlled oscillator (ICO) 32 having a control current output from the voltage-current converter as an input. Of course, it may be constituted by.

Next, as a third embodiment of the present invention, FIG.
An example in which the PLL circuit of the present invention is applied to the data reading device for recording disks such as CD-ROMs and DVDs described with reference to FIG. Note that the above description is referred to for the data reading device shown in FIG.

FIG. 3 is a diagram showing the configuration of the third embodiment of the present invention. Referring to FIG. 3, according to a third embodiment of the present invention, a voltage controlled oscillator (VCO) 11 that generates and outputs a clock signal having a predetermined frequency according to an input control voltage.
6, a frequency divider 111 for dividing the output of the voltage controlled oscillator 116, an input signal (EFM signal), and an output (RDCK) of the frequency divider 111 as inputs, and a width corresponding to the phase error between the two. Phase comparator 10 which converts the signal into a pulse signal
1, a first charge pump 102 that converts a pulse signal output from the phase comparator 101 into a voltage and outputs the voltage,
An input signal (EFM signal) and a clock signal (RDCK) are input, and a synchronization pattern (sync pattern) of the input signal is measured by the clock signal (RDCK) to detect a frequency error of the synchronization pattern, and to detect a frequency error. A frequency comparator 105 that converts and outputs a pulse signal having a corresponding width, a second charge pump 106 that converts a pulse signal output from the frequency comparator 105 into a voltage and outputs the voltage, and a first charge pump A first low-pass filter 103 receiving the output voltage of the first input terminal 102, a second low-pass filter 107 receiving the output voltage of the first charge pump 106, and a first low-pass filter 103.
And a voltage adder 115 that adds the output voltage of the second low-pass filter 107 to the output voltage of the second low-pass filter 107. The output voltage of the voltage adder 115 is input to the voltage control oscillator 116 as a control voltage, A current control oscillator comprising a frequency measurement circuit 117 for measuring the oscillation frequency of the oscillator 3 and a frequency division determination circuit 113 for determining and setting the frequency division value of the frequency divider 111 based on the measurement result of the frequency measurement circuit 117 3
The frequency division value is set variably according to the oscillation frequency of In addition,
Regarding the frequency comparator 105, for example,
No. -18856 (not disclosed at the time of filing the application) is referred to.

FIG. 5 is a diagram showing an example of the configuration of the frequency measurement circuit 117. Referring to FIG. 5, a frequency divider 121 having an output of a voltage controlled oscillator (VCO) 116 as an input,
A predetermined frequency division value (for example, frequency division value 102
4) The signal divided in 4) is input, and a period from the rising edge of the divided signal to the next rising edge is
Alternatively, during the period from the falling edge of the frequency-divided signal to the next falling edge, a control signal generation circuit 122 that outputs an active control signal, and a control signal from the control signal generation circuit 122 is active, For example, 100M output from a reference clock generation circuit (not shown)
A counter 123 that counts a reference clock pulse having a frequency of 1 Hz. The count value of the counter 123 at the time of one cycle measurement is read out to the frequency division determination circuit 113. After the counter 123 measures one cycle of the signal obtained by dividing the frequency of the voltage-controlled oscillator 116 by the frequency divider 121, at least until the count value is read out by the frequency division determining circuit 113, the counter 123 outputs the signal from the control signal generating circuit 122. The control signal supplied to the counter 123 is made inactive,
The counter 123 stops the counting operation. After the output value of the frequency measurement circuit 117 (the count value of the counter 123) is read out by the frequency division determination circuit 113, the counter 123
Is reset (cleared to zero), and thereafter, for example, after setting the frequency division value in the frequency divider 111, the frequency measurement circuit 117 starts the frequency measurement. The counter 123 is also reset at the time of initialization (reset sequence) such as when the apparatus is turned on.

FIG. 6 is a diagram showing another example of the configuration of the frequency measuring circuit 117. Referring to FIG. 6, a frequency measuring circuit 117 receives an output of a voltage controlled oscillator (VCO) 116 or a signal obtained by dividing the output by a frequency divider (not shown), and outputs a signal from a rising edge to a next falling edge. while,
Alternatively, only during the period from the falling edge to the next falling edge, a control signal generating circuit 124 that outputs an active control signal, and a switch (SW) that is turned on when the control signal from the control signal generating circuit 124 is active
1) a constant current source 125 connected between the power supply and one end of the switch 116, a capacitor 127 connected between the other end of the switch 126 and the ground potential, and a terminal voltage of the capacitor 127 as an analog input. A / D converter 128 and a switch for discharging the capacitor 127 (S
W2) 129, and the digital output signal of the A / D converter 128 is input to the frequency division determination circuit 113.

In the cycle measuring operation, the switch 126 is turned on (the switch 129 is turned off) in response to the control signal which is set to the active state, and the constant current Ic from the constant current source 125 is turned on.
Flows into the capacitor 127, the terminal voltage of the capacitor 127 rises, and the switch 126 is turned off after one cycle, and the A / D converter 128 A / D converts the terminal voltage of the capacitor 127 after one cycle. . After the output value of the frequency measurement circuit 117 is read out to the frequency division determination circuit 113, the switch 129 is turned on and the capacitor 127 is discharged, and thereafter, for example, the frequency division value is set in the frequency divider 111. After that, the frequency measurement circuit 117 is configured to start frequency measurement.

The frequency measuring circuits shown in FIGS. 5 and 6 can of course be applied to the frequency measuring circuit 5 shown in FIGS. 1 and 2. In the present invention, the frequency measurement circuit is not limited to the configuration shown in FIGS. 5 and 6, and any circuit configuration can be used as long as the circuit measures the length of one cycle. .

The frequency dividing determination circuit 113 is a frequency measuring circuit 1
At the time when one cycle is measured at 17, the output value of the frequency measuring circuit 117 is read out, and based on the value, the frequency of the input signal is converted from the frequency of the frequency divider 111 to the frequency of the input signal. Determine the value. To explain with a simple example, PL
When the frequency division value is “1” when the L circuit is in the locked state,
When the output frequency of the voltage controlled oscillator 116 becomes twice the original value, the output value of the frequency measuring circuit 117 becomes 、, and the divided value of the frequency divider 111 is “2”, that is, the voltage controlled oscillator 116 Of the output signal of by the frequency divider 111 is output as a data read clock (RDCK).

The frequency dividing determination circuit 113 calculates the input frequency from the output value (digital output signal) of the frequency measuring circuit 117 and the current frequency dividing value of the frequency divider, and calculates the input frequency.
From the 16 oscillation frequency ranges, a frequency division value that becomes a lockable oscillation frequency is obtained, and the frequency division value of the frequency divider 111 is set.
The frequency dividing determination circuit 113 calculates an input signal frequency from the output value of the frequency measuring circuit 117 and the contents of a register storing the current frequency dividing value of the frequency divider 111, and a frequency divider according to the input signal frequency. A look-up table for outputting a frequency division value selection signal for setting to 111 is provided.

If the frequency dividing value set in the frequency divider 111 is the same as the previous value, the frequency dividing judging circuit 113 does not reset the frequency.
You may comprise so that the previous state may be hold | maintained as it is.

Next, the operation of the synchronization control according to the third embodiment of the present invention will be described.

A phase comparison result output from a phase comparator 101 to which an EFM signal (or an EFMplus signal) and a data read clock (RDCK) are input is output as a voltage by a first charge pump 102 and a first low-pass filter 103 The frequency comparator 104 receives the output voltage of the phase locked loop, which is the output of the phase locked loop, and the EFM signal and the data read clock (RDCK).
Is input to the second low-pass filter 107, and the output voltage of the frequency synchronization system, which is the output voltage of the second low-pass filter 107, is added by the voltage adder 115. The output is input to a voltage controlled oscillator 116 as a control voltage, the output is input to a frequency divider 111, and the output of the frequency divider 111 is input to a phase comparator 101 and a frequency comparator 105 as a data read clock (RDCK). are doing.

At the start of the operation, the phase comparator 101, the first charge pump 102, the first low-pass filter 103
Is in a standby state, and the frequency comparator 105,
The second charge pump 106, the second low-pass filter 107, the VCO 116, and the frequency divider 111 operate so that the frequency is synchronized by a loop (frequency synchronization). At this time, the frequency division value of the frequency divider 111 is set to a predetermined value according to the clock speed of the data rate (1 × speed, 2 × speed, etc.) by software executed by the CPU (see FIG. 12).

When the frequencies are synchronized, the output voltage of the second low-pass filter 107 is fixed at a constant value.
Phase comparator 101, first charge pump 102, first
Low-pass filter 103, VCO 116, frequency divider 11
A PLL operation is performed so that the phases are synchronized in one loop (phase synchronization). At this time, the frequency division value of the frequency divider 111 is set to the value at the time of frequency synchronization. In this state, if the speed of the clock for reading data read from the recording disk changes, the frequency measurement circuit 117 detects this, and the frequency dividing determination circuit 113 sets the frequency dividing value based on the output value of the frequency measuring circuit 117 so that the phase is synchronized within the range of the oscillation frequency of the voltage controlled oscillator 116.

Next, a fourth embodiment of the present invention will be described. In the fourth embodiment of the present invention, the CD-ROM and the DVD described with reference to FIG.
The data reading device of the recording disk such as
An example in which the LL circuit is applied will be described. FIG. 4 is a diagram showing the configuration of the fourth embodiment of the present invention. Referring to FIG. 4, a fourth embodiment of the present invention is the third embodiment shown in FIG.
The frequency measuring circuit 117 of this embodiment is constituted by a reference clock generating circuit 114 and a frequency counter 112, and the voltage controlled oscillator 116 is constituted by a current controlled oscillator 110 whose oscillation frequency is varied by a control current.

More specifically, referring to FIG. 4, a PLL circuit according to a fourth embodiment of the present invention comprises a current controlled oscillator (current controlled oscillator) for outputting a signal of a predetermined frequency in accordance with an input control current. ) 110 and the frequency of the signal output from the current control oscillator 110 is 1 / N
Frequency divider 111 for dividing the data into a data read clock (RDCK) and a synchronization detection pattern (sync pattern) in the data signal read from the recording disk
And a phase comparator 101 that compares the phases of the data read clock (RDCLK) output from the frequency divider 111 and converts the output into a pulse signal having a width that outputs a voltage corresponding to the phase error between the two. A first charge pump 102 that converts a pulse signal output from the comparator 101 into a voltage and outputs the voltage, a first low-pass filter 103 that blocks noise of a voltage value output from the first charge pump 102, A first voltage-current converter 104 for converting an output voltage of the first low-pass filter 104 into a current value, a synchronization detection pattern in a data signal read from a recording disk, and a data read clock output from the frequency divider 111 And a frequency comparator 105 that converts the pulse signal into a pulse signal having a width corresponding to the frequency error and outputs the pulse signal. A second charge pump 106 that converts the input pulse signal into a voltage and outputs the voltage, a second low-pass filter 107 that blocks noise of a voltage value output from the second charge pump 106, and a second low-pass A second voltage-to-current converter that converts the output voltage of the filter 107 into a current value, and an adder 10 that adds the output currents of the first and second voltage-to-current converters 104 and 108
A frequency counter 112 for measuring the frequency by measuring the period of the output signal of the voltage-controlled oscillator 3 by inputting the current added by the adder 109 as a control current to the current-controlled oscillator 110; A frequency division determining circuit 113 that varies the frequency division value of the frequency divider 111 based on the measurement result of the counter 112, and variably sets the frequency division value according to the oscillation frequency of the current control oscillator 110.

The frequency counter 112 outputs, for example, 1 from a reference clock generator 114 using a crystal oscillator.
The frequency of the output of the current control oscillator 110 is measured by counting the reference clock of 00 MHz.

The frequency counter 112 is configured as shown in FIG. 5. When the control signal (count enable signal) input to the counter 123 is active, the output of the current control oscillator 110 is divided by the frequency divider 121. For example, during the period from the rising edge of the signal divided by 1024 to the next rising edge, the reference clock generator 114
Count the number of reference clock pulses input from
The count value is read out to the frequency division determination circuit 113. After the counter 123 constituting the frequency counter 112 measures one cycle of the signal obtained by dividing the output of the current control oscillator 110 by 1024 by the divider 121, at least until the count value is read out to the division determining circuit 113, The control signal (count enable signal) is set to an inactive state.

The frequency dividing determination circuit 113 includes a frequency counter 1
When the measurement of one cycle of the output of the current control oscillator 110 is completed in 12, the count value of the counter 123 constituting the frequency counter 112 is read out, and the count value is obtained by dividing the count value of the frequency divider 111 by the input signal. Convert to frequency.

The frequency counter 112 has a frequency
13, a counter 12 constituting the frequency counter 112;
After the count value of 3 is read, the count value may be reset (cleared to zero) and the frequency measurement may be started again.

The frequency divider determination circuit 113 calculates the input frequency from the count value read from the frequency counter 112 and the current frequency divider value of the frequency divider, and calculates the lockable oscillation frequency from the oscillation frequency range of the current control oscillator 110. A frequency division value that becomes a frequency is obtained, and a frequency division value of the frequency divider 111 is set. The frequency division determining circuit 113 calculates an input signal frequency from the contents of a register that stores the count value and the current frequency division value of the frequency divider 111, and a frequency divider 111 according to the input signal frequency.
And a lookup table that outputs a frequency division value selection signal to set the frequency division value.

If the frequency division value set in the frequency divider 111 is the same as the previous value, the frequency division determination circuit 113 does not reset the frequency.
You may comprise so that the previous state may be hold | maintained as it is.

The operation of the fourth embodiment of the present invention will be described. In the fourth embodiment of the present invention, similarly to the third embodiment, at the start of the operation, the phase comparator 101, the first charge pump 102, the first low-pass filter 10
3. The first voltage-to-current converter 104 is in a standby state, and the frequency comparator 105, the second charge pump 106, the second low-pass filter 107, the first voltage-to-current converter 108, the ICO 110, and the frequency divider It operates so that the frequency is synchronized in the loop of the device 111 (frequency synchronization). At this time, the frequency division value of the frequency divider 111 is determined by the CPU 411 (FIG. 13).
) Is set to a predetermined value according to the clock speed of the data rate (1 × speed, 2 × speed, etc.).

At the point in time when the frequencies are synchronized, the output current of the second voltage-to-current converter 108 is fixed, supplied as an offset current of the control current via the synthesizer 109, and output from the phase comparator 101, 1 charge pump 10
2. A PLL operation is performed so that phases are synchronized in a loop of the first low-pass filter 103, the first voltage-current converter 104, the VCO 116, and the frequency divider 111 (phase synchronization). At this time, the frequency division ratio of the frequency divider 111 is set to the value at the time of frequency synchronization. In this state, if the speed of the clock for reading data read from the recording disk changes, the frequency counter 112 This is detected by the frequency division determination circuit 113 based on the count value of the frequency counter 112 within the range of the oscillation frequency of the voltage controlled oscillator 116.
Set the frequency division value so that the phases are synchronized.

FIG. 7 is a diagram showing an example of the configuration of the frequency dividers 4 and 111 applied to each of the above-described embodiments of the present invention shown in FIGS. As shown in FIG. 7, this frequency divider can variably set the frequency division value to 1 (no frequency division), 2, 4, 8, and 16, and has four stages of flip-flops 201 to 201.
204, a register 205 for inputting and holding a frequency division value selection signal output from the frequency division determination circuit 203, and a selector 206. The selector 206
The output of the current control oscillator 111 and the outputs of the flip-flops 201 to 204 of the first stage to the last stage are input, and the output of the register 205 is selected as a selection signal to select an output corresponding to the selected frequency division value. The flip-flop 201 feeds back the inverted output terminal Q # to the data input terminal D, inputs the output of the current controlled oscillator (or the output or input signal of the voltage controlled oscillator) to the clock input terminal (CK), and Each of the flip-flops 202 to 204 feedback-inputs the inverted output terminal Q # to the data input terminal D, and supplies the clock input terminal (CK) with the output terminal Q of the preceding flip-flop.
Is connected.

FIG. 8 is a diagram showing an example of the configuration of the voltage-current conversion circuits 104 and 108 applied to the fourth embodiment of the present invention and the voltage-current conversion circuit 31 shown in FIG. 2B. . Referring to FIG. 8, the current-voltage conversion circuit has a source connected to a constant current source I ₀ is supplied to the commonly connected with the reference current, the output voltage (Vi of the loop filter (LPF)
n) and reference voltages (Vref) are input to the gates of the P-channel MOS transistors PM1 and PM2, respectively. The drain of the P-channel MOS transistor PM1 is connected to the ground potential, and the drain of the P-channel MOS transistor PM2 is N-channel MOS having a source connected to ground potential and a drain and gate connected
A current is output from the drain of an N-channel MOS transistor NM2 whose gate is connected to the drain of the transistor NM1, whose gate is commonly connected to the gate of the N-channel MOS transistor NM1, and whose source is connected to the ground potential. , NM2
Constitutes a current mirror circuit. Voltage (Vin)
Current corresponding to the difference voltage between the reference voltage (Vref) and the reference voltage (Vref) is output from the P-channel MOS transistor PM2 and input to the input terminal of the current mirror circuit.
The control current Iout for the current control oscillator is output from the drain of the S transistor NM2.

The current adding circuit 109 may be configured by connecting the outputs of the first and second voltage / current circuits 104 and 108 (current mirror output in FIG. 6).

FIG. 9 is a diagram showing a configuration of a current control oscillation circuit, and is an example of a circuit configuration applied to the current control oscillation circuit 110 shown in FIG. 4 and the current control oscillation circuit 32 of FIG. 2B. It is shown. Referring to FIG. 9A,
The source is connected to a power supply (high-potential power supply VDD),
P-channel MOS transistor PM having a gate and a drain connected to each other and connected to a control current input terminal
10, a ring oscillator composed of odd-numbered (three in FIG. 3) inverters 301, 302, and 303 having an output terminal fed back to an input terminal, and a differential voltage output from a final stage inverter 303 of the ring oscillator and output. And a voltage comparator 304 that outputs a signal (ICO output).

FIG. 9B is a diagram showing an example of the circuit configuration of the inverter constituting the ring oscillator. FIG.
Referring to (b), in each inverter, a source is connected to a power supply, a gate is connected to a G terminal, and a P-channel MOS transistor PM11 which functions as a constant current source is connected to a P-channel MOS transistor PM11 whose source is commonly connected.
11 is connected to the differential input terminal I
1 and I2, the drain is connected to the GND potential via load resistors R1 and R2, and the differential output terminal O
1 and P2 MOS transistors PM12 and PM13 connected to O2.

The G terminal of the inverter is commonly connected to the gate of P channel MOS transistor PM10. That is, the input control current is supplied to the P-channel MOS transistor PM
10 and converts the voltage into a voltage.
By varying the current values of the constant current sources of the differential amplifier circuits 303 to 303, the delay time per inverter is varied, the oscillation frequency is varied, and the voltage at which the differential output from the inverter 303 is differentially input is set. The comparator 304 outputs an oscillation output.

In the current-voltage conversion circuit shown in FIG. 8, the differential transistor pair PM1, PM2 is formed of an N-channel MOS transistor, and the current mirror circuits NM1, NM2 are formed of P-channel MOS transistors.
An output current from a current mirror circuit constituted by a transistor may be input to a current control oscillator as a control current. Further, the differential amplifier circuit forming the inverter circuit of FIG. 9B may be configured by an N-channel MOS transistor.

FIG. 10 (a) is a diagram showing the relationship between the linear velocities of the inner and outer circumferences, the data clock (RDCK), the frequency division ratio, and the oscillation frequency of the current control oscillator in the case of 8 × CAV. . The linear velocity is 3.2 times faster on the inner circumference, 8 times faster on the outer circumference, 83.712 MHz on the inner circumference, and 20 times on the outer circumference.
It becomes 9.28 MHz.

That is, referring to FIG. 10A, in the above embodiment, the oscillation frequency of the current control oscillation circuit is set to 167.42 MHz in the inner circumference, the frequency division value of the frequency divider is set to "2", and the current is increased in the outer circumference. The oscillation frequency of the control oscillation circuit is set to 209.
The frequency division value is “1” at 28 MHz.

On the other hand, in the PLL circuit (see FIG. 11) described as the prior art, when the frequency divider 111 is fixed to the frequency division value “1”, the current-controlled oscillator needs to The oscillation frequency is 8
It is required that the frequency be 3.712 MHz and 209.28 MHz on the outer circumference.
It is required that the oscillation frequency range be 12 to 209.28 MHz. On the other hand, in each of the embodiments of the present invention, as described above, the frequency divider 11
The frequency division value of “1” is automatically set to “2”, and the frequency division value of “1” is automatically set at the outer periphery.
A range of 7.42 to 209.28 MHz is sufficient.

FIG. 10 (b) shows the data reading clock (RDCK) of the DVD, the double speed value (up to 16 × speed), the linear velocities of the outer circumference and the inner circumference, the dividing value, the outer circumference and the inner circumference of the current control oscillator. FIG. 6 shows an example of a relationship between oscillation frequencies in a list format.

The PL of the fourth and third embodiments described above
As a modification of the L circuit, the cutoff frequency fc of the first low-pass filter 103 is variably set based on frequency value information from the frequency division determination circuit 113 or an output value from the frequency measurement circuit 117 (frequency counter 112). Thus, the filter configuration may be configured to automatically set the filter configuration to an optimum value according to the input signal frequency. For example, in the first low-pass filter 103 shown in FIG. 3 or FIG. 4, a plurality of series circuits each including a switch and a capacitor are provided between a signal line and a ground potential as a capacitor for defining a value of the cutoff frequency fc. The time constant is varied by selecting a switch to be turned on based on the frequency division value selection information from the frequency division determination circuit 113, thereby changing the cutoff frequency fc of the first low-pass filter 103. It is set variably according to the input signal frequency.

Next, a fifth embodiment of the present invention will be described. The fifth embodiment of the present invention includes the PLL circuit of the third or fourth embodiment of the present invention as the PLL circuit 408 of the data reading device shown in FIG. Based on the frequency division value information or the output value from the frequency measurement circuit 117 (frequency counter 112), the CPU 411 (see FIG. 12) controls the characteristics (for example, cutoff frequency fc) of the filter circuit 406 (see FIG. 12).
Change the setting of. In addition to the characteristics of the filter circuit 406, the cutoff frequency fc of the first low-pass filter 103 of the PLL circuit may be automatically set to an optimum value based on the frequency of the input signal. According to the fifth embodiment of the present invention, a system configuration suitable for an input signal frequency can be automatically set.

[0087]

As described above, according to the present invention,
The following effects are obtained.

A first effect of the present invention is that the PLL circuit can autonomously set an optimum frequency dividing value automatically in accordance with an input signal frequency without using software, thereby reducing the load on software. At the same time, the time required for synchronization can be shortened. The reason is,
This is because the PLL circuit includes means for variably setting the frequency division value of the frequency divider according to the input signal frequency.

The second effect of the present invention is that the oscillation frequency range of the oscillator can be set narrow, which facilitates the design of the oscillator and contributes to shortening the pull-in time.

A third effect of the present invention is that by automatically setting the filter constant of the PLL circuit based on the measurement result of the frequency measuring circuit, it is possible to automatically set a configuration suitable for the input signal frequency. That is.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a first exemplary embodiment of the present invention.

FIG. 2A is a diagram illustrating a configuration of a second embodiment of the present invention, and FIG. 2B is a diagram illustrating a configuration of a voltage controlled oscillator (VCO).

FIG. 3 is a diagram showing a configuration of a third exemplary embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a fourth embodiment of the present invention.

FIG. 5 is a diagram illustrating an example of a configuration of a frequency measurement circuit used in each embodiment of the present invention.

FIG. 6 is a diagram showing another example of the configuration of the frequency measurement circuit used in each embodiment of the present invention.

FIG. 7 is a diagram illustrating an example of a configuration of a frequency divider used in each embodiment of the present invention.

FIG. 8 is a diagram showing an example of a configuration of a voltage-current converter used in each embodiment of the present invention.

9A is a diagram illustrating an example of a configuration of a current controlled oscillator used in each embodiment of the present invention, and FIG. 9B is a diagram illustrating an example of a configuration of an inverter of a ring oscillator.

FIG. 10 is a diagram for explaining the operation of one embodiment of the present invention.

FIG. 11 is a diagram illustrating a configuration of a conventional PLL circuit.

FIG. 12 is a diagram illustrating an example of a configuration of a conventional data reading device (reproducing device).

FIG. 13 is a diagram for explaining EMF and EMFplus codes.

[Explanation of symbols]

 1, 101, phase comparator 2, 103, 107 low-pass filter 3, 116 voltage-controlled oscillator 4, 111 frequency divider 5 frequency measuring circuit 6, 113 frequency-dividing decision circuit 102, 106 charge pump 104, 108 voltage-current converter 109 Synthesizer 112 Frequency counter 114 Reference clock 115 Voltage adder 121 Divider 122 Control signal generator 123 Counter 124 Control circuit 125 Constant current source 126, 129 Switch 127 Capacitor (capacitance) 128 A / D converter 201-204 Flip-flop 205 Register 206 Selector 401 Recording disk 402 Optical head 403 Disk motor 404 Amplifier (preamplifier) 405 Servo controller 406 Filter circuit 407 Binarization circuit 408 PLL circuit 409 Decoder 410 Error correction circuit 411 CPU

Claims (18)

[Claims] An output of an oscillator whose oscillation frequency is controlled by a control voltage or a control current according to an output of a phase comparator is fed back to the phase comparator via a frequency divider of a variable dividing value and input. A PLL circuit for detecting a phase difference from a signal, comprising: means for variably setting a frequency division value of the frequency divider according to a measurement result of a cycle of the input signal.
LL circuit. 2. An output of an oscillator whose oscillation frequency is controlled by a control voltage or a control current corresponding to an output of the phase comparator is fed back to the phase comparator via a frequency divider of a variable dividing value and input. A PLL circuit for detecting a phase difference from a signal, comprising: means for variably setting a frequency division value of the frequency divider according to a measurement result of a cycle of an output signal of the oscillator. 3. A means for variably setting the frequency division value comprises: measuring means for measuring a length of one cycle of the input signal; and, within the oscillation frequency range of the oscillator, based on a measurement result of the measuring means. 2. The PLL circuit according to claim 1, further comprising: means for determining a frequency division value so as to synchronize, and setting the determined frequency division value to the frequency divider. 4. The oscillator according to claim 1, wherein said means for variably setting said frequency dividing value comprises: measuring means for measuring a length of one cycle of an output signal of said oscillator; and an oscillating frequency range of said oscillator based on a measurement result of said measuring means. 3. The PLL circuit according to claim 2, further comprising: means for determining a frequency division value so as to synchronize within the frequency divider, and setting the determined frequency division value to the frequency divider. 5. The PLL circuit according to claim 1, wherein the frequency division value includes 1 which is a frequency division value corresponding to bypassing the frequency divider. . 6. A phase comparator for inputting an input signal to one input terminal, a loop filter receiving an output of the phase comparator as an input, and an oscillation frequency variably set based on an output voltage of the loop filter. A PLL circuit comprising: a voltage controlled oscillator; and a frequency divider that divides an output signal of the voltage controlled oscillator and supplies the divided signal to another input terminal of the phase comparator. A frequency measurement circuit for determining a frequency by measuring a cycle of the input signal; and a frequency divider for determining a frequency division value of the frequency divider based on a measurement result of the frequency measurement circuit. And a frequency dividing determination circuit for varying a frequency dividing value of the device. 7. A phase comparator for inputting an input signal to one input terminal, a loop filter receiving an output of the phase comparator as an input, and an oscillation frequency variably set based on an output voltage of the loop filter. A PLL circuit comprising: a voltage-controlled oscillator; and a frequency divider that divides an output signal of the oscillator and supplies the divided signal to another input terminal of the phase comparator, wherein the divider has a variable dividing value. A frequency measurement circuit that determines the frequency of the input signal by measuring a cycle of an output signal of the oscillator; and determines a frequency division value of the frequency divider based on a measurement result of the frequency measurement circuit. And a frequency-dividing determination circuit that varies a frequency-divided value of the frequency divider. 8. The frequency dividing determination circuit sets the frequency dividing value according to a measurement result output from the frequency measuring circuit so that a PLL circuit is locked within an oscillation frequency range of the oscillator. 8. The PLL circuit according to claim 6, wherein: 9. A voltage controlled oscillator for generating and outputting a clock signal having a frequency corresponding to an input control voltage, and a frequency divider having a frequency dividing value variably set and dividing a clock signal from the voltage controlled oscillator. A phase comparison unit that receives an input signal and a clock signal output from the frequency divider and outputs a voltage corresponding to a phase difference between these signals; and the input signal and the output from the frequency divider A frequency comparison circuit that receives a clock signal as an input, detects a frequency error by measuring a synchronization pattern of the input signal using a clock signal output from the frequency divider, and outputs an error voltage corresponding to the frequency error. A first low-pass filter that receives an output voltage from the phase comparison unit as an input; a second low-pass filter that receives an output voltage from the frequency comparison unit as an input; A voltage adder for adding the output voltage of the band-pass filter and the output voltage of the second low-pass filter, wherein the output voltage of the voltage adder is input to the current control oscillator as the control voltage. Further, a frequency measurement circuit that measures the cycle of the output signal of the voltage-controlled oscillator, based on the measurement result of the frequency measurement circuit, so that the PLL circuit is locked within the oscillation frequency range of the oscillator,
A frequency divider determining circuit for setting a frequency division value of the frequency divider. 10. The voltage controlled oscillator comprises: a voltage / current converter for converting an input voltage into a current; and a current controlled oscillator for inputting a current output from the voltage / current converter as a control current. The PLL circuit according to any one of claims 6 to 9, wherein: 11. A current control oscillator for generating and outputting a clock signal having a frequency corresponding to an input control current, and a frequency divider having a frequency-divided value variably set and frequency-dividing a clock signal from the current control oscillator. A phase comparison unit that receives an input signal and a clock signal output from the frequency divider and outputs a voltage corresponding to a phase difference between these signals; and the input signal and the output from the frequency divider A frequency comparison circuit that receives a clock signal as an input, detects a frequency error by measuring a synchronization pattern of the input signal using a clock signal output from the frequency divider, and outputs an error voltage corresponding to the frequency error. A first low-pass filter that receives an output voltage from the phase comparison unit as an input; a second low-pass filter that receives an output voltage from the frequency comparison unit as an input; A first voltage-to-current conversion circuit that converts the output voltage of the low-pass filter to a current; and a second voltage-to-current conversion circuit that converts the output voltage of the second low-pass filter to a current. A sum current obtained by adding a current output from the first voltage-current conversion circuit and a current output from the second voltage-current conversion circuit is input to the current control oscillator as the control current; A frequency measurement circuit for measuring the cycle of the output signal of the current control oscillator, based on the measurement result of the frequency measurement circuit, so that the PLL circuit is locked within the oscillation frequency range of the oscillator,
A frequency divider determining circuit for setting a frequency division value of the frequency divider. 12. A frequency divider for inputting a signal to be measured input to the frequency measurement circuit and outputting a signal obtained by dividing the frequency of the signal to be measured, the frequency measurement circuit being divided by the frequency divider. And a counter that counts a reference clock input from the reference clock generation circuit during a period from a rise of the signal to the next rise or from a fall to the next fall. 12. The PLL circuit according to any one of 6 to 11. 13. The frequency measurement circuit according to claim 1, wherein the signal to be measured input to the frequency measurement circuit, or a signal obtained by dividing the signal by a frequency divider, rises from the rising edge to the next rising edge or rises. From a fall to the next fall, a switch that is turned on, a capacitance charged by a current from a constant current source via the switch that is turned on, and a terminal voltage of the capacitance, The PLL circuit according to any one of claims 6 to 11, further comprising: an analog-digital converter that outputs a measurement result as a digital value. 14. A signal output from a phase comparison unit to which a signal read from a recording disk and a data read clock are input is smoothed by a first low-pass filter, converted to a current by a first voltage-current converter, and output. Phase-locked current and EF
The output voltage of the frequency comparison unit having the M data and the data read clock as inputs is smoothed by a second low-pass filter, and converted into a current by a second voltage-current converter, and is combined with an output current of a frequency synchronization system. And input to the current controlled oscillator,
In a PLL circuit that inputs an output of the current control oscillator to the phase comparison unit and the frequency comparison unit via a frequency divider, the frequency divider includes a frequency divider selected from among a plurality of frequency division values. A frequency counter that divides the output of the current control oscillator and counts the length of one cycle of the output signal of the current control oscillator using a reference clock generated by a reference clock generation circuit; and a count value of the frequency counter. A frequency division determination circuit that sets a frequency division value of the frequency divider so as to obtain an oscillation frequency range of the current control oscillator based on the above, and lock the frequency within the oscillation frequency range of the current control oscillator. A PLL circuit characterized by the above-mentioned. 15. The frequency divider, wherein one or a plurality of signals obtained by dividing an input signal to the frequency divider by one frequency division value or different frequency division values, and an input to the frequency divider. And a selection circuit that receives a signal as an input, selects a signal output from the frequency division determination circuit as a selection signal, and selects and outputs any one of the plurality of input signals. The PLL circuit according to claim 6. 16. The apparatus according to claim 9, wherein a cutoff frequency of said first low-pass filter is variably set based on a measurement result of said frequency measurement circuit. 15. The PLL circuit according to any one of 14. 17. An amplifier for generating a reproduction RF signal, a focus error signal, and a tracking error signal from data read through a head for reading data from a recording disk, and removing noise from the reproduction RF signal from the amplifier. A filter for performing waveform equalization, a binarization circuit for binarizing a reproduction RF signal from the filter, and a data read clock synchronized with the data input by the binarized data by the binarization circuit A PLL circuit for generating and outputting a clock, a demodulation circuit for demodulating data based on a clock for reading data from the PLL circuit, an error correction circuit for correcting an error in reproduced data, an electric motor for rotatingly driving the recording disk, In a reproducing apparatus including a servo control device for controlling a head and an electric motor, and a CPU for controlling the whole, The PLL circuit according to any one of claims 7 to 16,
A data reading device comprising an L circuit. 18. The data reading device according to claim 17, wherein the filter characteristic is set variably based on an output of the frequency division determining circuit.