JPH11121738A - MOS transistor - Google Patents
MOS transistorInfo
- Publication number
- JPH11121738A JPH11121738A JP10069749A JP6974998A JPH11121738A JP H11121738 A JPH11121738 A JP H11121738A JP 10069749 A JP10069749 A JP 10069749A JP 6974998 A JP6974998 A JP 6974998A JP H11121738 A JPH11121738 A JP H11121738A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- gate
- region
- mos transistor
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
- H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs having non-planar bodies, e.g. having recessed gate electrodes
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
- H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
- H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
- H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
- H10D84/0167—Manufacturing their channels
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/514—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers
- H10D64/516—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the insulating layers the thicknesses being non-uniform
Landscapes
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
(57)【要約】
【課題】 ホットキャリヤ効果を防止しながら、ドレイ
ン飽和電流特性も良好となるＭＯＳトランジスタを提供
すること。
【解決手段】 ホットキャリヤ効果を防止する厚い絶縁
膜１４は、ポリシリコンゲート１３のエッジからチャン
ネル方向にＬＤＤ領域であるｎ- 領域１５を越えない範
囲で形成される。
[PROBLEMS] To provide a MOS transistor having a good drain saturation current characteristic while preventing a hot carrier effect. SOLUTION: A thick insulating film 14 for preventing a hot carrier effect is formed in a range not exceeding an n − region 15 which is an LDD region in a channel direction from an edge of a polysilicon gate 13.
Description
【０００１】[0001]
【発明の属する技術分野】本発明はＭＯＳトランジスタ
に係り、特にゲート領域構造に関するものである。[0001] 1. Field of the Invention [0002] The present invention relates to a MOS transistor, and more particularly to a gate region structure.
【０００２】[0002]
【従来の技術】既存のＭＯＳトランジスタにおいては、
ドレインエッジでの高電界によるホットキャリヤ効果に
起因する信頼性低下を改善するために、一般にＬＤＤ領
域を形成した。しかし、素子の高速特性を追求してＬＤ
Ｄ領域のドーピング濃度が増加することに伴い、ゲート
エッジで再度電界が増加した。そこで、ゲートエッジ付
近を部分的に酸化（ＧＰＯＸ：gate poly oxidation ）
させて、ゲートエッジ部のゲート絶縁膜両端部のゲート
絶縁膜を厚くすることにより、この部分の電界を最小化
させてホットキャリヤ効果を抑制させることが行われて
おり、これをＧＰＯＸ構造と呼ぶ。2. Description of the Related Art In existing MOS transistors,
An LDD region is generally formed in order to improve the reliability reduction caused by the hot carrier effect due to the high electric field at the drain edge. However, in pursuit of high-speed characteristics of the device, LD
As the doping concentration of the D region increased, the electric field increased again at the gate edge. Therefore, partial oxidation near the gate edge (GPOX: gate poly oxidation)
By increasing the thickness of the gate insulating film at both ends of the gate insulating film at the gate edge, the electric field in this portion is minimized to suppress the hot carrier effect. This is called a GPOX structure. .
【０００３】図３は、ＧＰＯＸ構造を採用した従来のＭ
ＯＳトランジスタを示す。この図において、１はｐ型シ
リコン基板であり、このシリコン基板１のチャンネル領
域上にゲート絶縁膜２を介してポリシリコンゲート３が
形成される。このポリシリコンゲート３エッジのゲート
絶縁膜２両端部およびその外側の基板１表面部には厚い
絶縁膜４が形成される。この絶縁膜４の下において、シ
リコン基板１内には、ソースおよびドレインを構成する
ｎ- 領域５とｎ+ 領域６が形成される。ポリシリコンゲ
ート３の側面には側壁７が形成される。FIG. 3 is a diagram showing a conventional M-type structure employing a GPOX structure.
3 illustrates an OS transistor. In FIG. 1, reference numeral 1 denotes a p-type silicon substrate, and a polysilicon gate 3 is formed on a channel region of the silicon substrate 1 via a gate insulating film 2. A thick insulating film 4 is formed on both ends of the gate insulating film 2 at the edge of the polysilicon gate 3 and on the surface of the substrate 1 outside the both ends. Under the insulating film 4, an n − region 5 and an n + region 6 forming a source and a drain are formed in the silicon substrate 1. Side walls 7 are formed on the side surfaces of the polysilicon gate 3.
【０００４】このようなＭＯＳトランジスタは、次のよ
うな工程により製造される。まず、ｐ型シリコン基板１
上にゲート絶縁膜２を形成した後、ポリシリコンをその
上に堆積し、所定のゲートパターンマスク（図示せず）
を用いて前記ポリシリコン層をパターニングしてポリシ
リコンゲート３を形成する。次いで、ゲートポリ酸化工
程を施して７〜１７ｎｍほどの厚い酸化膜４を形成す
る。次いで、ＬＤＤイオン注入工程を実施してｎ- 領域
５を形成した後、ポリシリコンゲート３の側面に側壁７
を形成し、しかる後、再びイオン注入工程を施してｎ+
領域６を形成することによりＬＤＤ構造のソースおよび
ドレインを完成させる。[0004] Such a MOS transistor is manufactured by the following steps. First, the p-type silicon substrate 1
After forming the gate insulating film 2 thereon, polysilicon is deposited thereon, and a predetermined gate pattern mask (not shown)
Then, the polysilicon layer is patterned to form a polysilicon gate 3. Next, a gate poly-oxidation process is performed to form a thick oxide film 4 having a thickness of about 7 to 17 nm. Next, after performing an LDD ion implantation step to form an n − region 5, a side wall 7 is formed on the side surface of the polysilicon gate 3.
Is formed, and then an ion implantation process is performed again to obtain n +
By forming the region 6, the source and the drain of the LDD structure are completed.
【０００５】[0005]
【発明が解決しようとする課題】上記のような従来の構
造および方法において、厚い絶縁膜４は、ゲート絶縁膜
２よりも相当に厚く形成されるため、この絶縁膜４を形
成するためのＧＰＯＸ工程は、長時間の熱酸化工程とな
る。しかるに、熱酸化工程時間が長くなると、酸化時の
酸化源のＨ2 ／Ｏ2 がポリシリコンゲートとゲート絶縁
膜の界面、およびゲート絶縁膜とシリコン基板の界面に
沿ってポリシリコンゲート３のエッジからポリシリコン
ゲート３の中央部側に拡散するため、図３に示すよう
に、厚い絶縁膜４にバーズビークＢＢが発生し、厚い絶
縁膜４がポリシリコンゲート３のエッジから内側に深く
入り込むようになる。この従来例のように厚い絶縁膜４
を７〜１７ｎｍ厚に形成した場合、厚い絶縁膜４は、ポ
リシリコンゲート３のエッジから５０ｎｍも深く入り込
み、ｎ- 領域５（ＬＤＤ領域）を越えてその内側のチャ
ンネル領域まで入り込む。したがって、従来のＭＯＳト
ランジスタでは、ＧＰＯＸ構造によりホットキャリヤ効
果は改善されるが、厚い絶縁膜４がポリシリコンゲート
３の内側に深く形成される結果、動作速度を代弁するド
レイン飽和電流(Idsat) 特性が劣化し、高速回路を実現
する上で障害が発生する問題点があった。In the conventional structure and method as described above, the thick insulating film 4 is formed to be considerably thicker than the gate insulating film 2, so that GPOX for forming the insulating film 4 is used. The process is a long-time thermal oxidation process. However, when the thermal oxidation process time is prolonged, the oxidation source H 2 / O 2 at the time of the oxidation is increased along the interface between the polysilicon gate and the gate insulating film and the interface between the gate insulating film and the silicon substrate along the edge of the polysilicon gate 3. 3, the bird's beak BB occurs in the thick insulating film 4 as shown in FIG. 3, and the thick insulating film 4 penetrates deeply from the edge of the polysilicon gate 3 to the inside. Become. Thick insulating film 4 as in this conventional example
Is formed to a thickness of 7 to 17 nm, the thick insulating film 4 penetrates as deep as 50 nm from the edge of the polysilicon gate 3, crosses the n − region 5 (LDD region), and enters the channel region inside. Therefore, in the conventional MOS transistor, although the hot carrier effect is improved by the GPOX structure, the thick insulating film 4 is formed deep inside the polysilicon gate 3, and as a result, the drain saturation current (Idsat) characteristic which substitutes the operation speed is obtained. However, there has been a problem that a failure occurs in realizing a high-speed circuit.
【０００６】本発明は上記の点に鑑みなされたもので、
ホットキャリヤ効果を防止しながら、ドレイン飽和電流
特性も良好となるＭＯＳトランジスタを提供することを
目的とする。[0006] The present invention has been made in view of the above points,
It is an object of the present invention to provide a MOS transistor having a good drain saturation current characteristic while preventing a hot carrier effect.
【０００７】[0007]
【課題を解決するための手段】本発明は上述の課題を解
決するために、ＬＤＤ構造を有するＭＯＳトランジスタ
において、半導体基板のチャンネル領域上にゲート絶縁
膜を介してゲートを形成し、該ゲートエッジ部のゲート
絶縁膜両端部にゲート絶縁膜よりも厚い絶縁膜を形成
し、該厚い絶縁膜は前記チャンネル領域側にＬＤＤ領域
を越えない範囲で形成されることを特徴とするＭＯＳト
ランジスタとする。According to the present invention, in order to solve the above-mentioned problems, in a MOS transistor having an LDD structure, a gate is formed on a channel region of a semiconductor substrate via a gate insulating film, and the gate edge is formed. A MOS transistor characterized in that an insulating film thicker than the gate insulating film is formed at both ends of the gate insulating film, and the thick insulating film is formed on the channel region side so as not to exceed the LDD region.
【０００８】また、本発明は、ＬＤＤ構造を有するＭＯ
Ｓトランジスタにおいて、半導体基板のチャンネル領域
上にゲート絶縁膜を介してゲートを形成し、該ゲートエ
ッジ部のゲート絶縁膜両端部にゲート絶縁膜よりも厚い
絶縁膜を形成し、該厚い絶縁膜は、ＬＤＤ領域が終わる
地点からチャンネル領域側に１０ｎｍ以内に位置するこ
とを特徴とするＭＯＳトランジスタとする。Further, the present invention relates to an MO having an LDD structure.
In the S transistor, a gate is formed on a channel region of a semiconductor substrate via a gate insulating film, and an insulating film thicker than the gate insulating film is formed at both ends of the gate insulating film at the gate edge. , The MOS transistor is located within 10 nm from the point where the LDD region ends to the channel region side.
【０００９】[0009]
【発明の実施の形態】次に添付図面を参照して本発明の
ＭＯＳトランジスタの実施の形態を詳細に説明する。図
１は本発明の第１の実施の形態を示す断面図である。こ
の図において、１１はｐ型シリコン基板であり、このシ
リコン基板１１のチャンネル領域上にゲート絶縁膜１２
を介してポリシリコンゲート１３が形成される。このポ
リシリコンゲート１３エッジのゲート絶縁膜１２両端部
およびその外側の基板１１表面部には厚い絶縁膜１４が
形成される。この絶縁膜１４は、ゲート絶縁膜１２と類
似の性質の絶縁膜であり、例えばシリコン酸化膜であ
る。前記ポリシリコンゲート１３のエッジ部分の下にお
いてシリコン基板１１の表面部内には、ＬＤＤ領域であ
るｎ- 領域１５が形成される。さらに、このｎ- 領域１
５に接続して、その外側の基板１１表面部内にはｎ+ 領
域１６が形成される。このｎ- 領域１５とｎ+ 領域１６
とによりソースおよびドレイン領域が形成される。ポリ
シリコンゲート１３の側面には側壁１７が形成される。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a MOS transistor according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. In this figure, reference numeral 11 denotes a p-type silicon substrate, and a gate insulating film 12 is formed on a channel region of the silicon substrate 11.
, A polysilicon gate 13 is formed. A thick insulating film 14 is formed on both ends of the gate insulating film 12 at the edge of the polysilicon gate 13 and on the surface of the substrate 11 outside thereof. The insulating film 14 is an insulating film having properties similar to those of the gate insulating film 12, and is, for example, a silicon oxide film. An n − region 15, which is an LDD region, is formed in the surface portion of the silicon substrate 11 below the edge portion of the polysilicon gate 13. Furthermore, this n - region 1
5 and an n + region 16 is formed in the surface portion of the substrate 11 outside thereof. The n − region 15 and the n + region 16
Thus, source and drain regions are formed. Side walls 17 are formed on the side surfaces of the polysilicon gate 13.
【００１０】以上のような構造において、厚い絶縁膜１
４は、ポリシリコンゲート１３のエッジからポリシリコ
ンゲート１３の中央部（内側）に入り込んで形成される
が、図１の第１の実施の形態では、厚い絶縁膜１４は、
ＬＤＤ領域であるｎ- 領域１５を越えない範囲で形成さ
れる。例えばポリシリコンゲート１３のエッジからｎ-
領域１５の縁までを２５ｎｍとすると、厚い絶縁膜１４
は、ポリシリコンゲート１３のエッジからチャンネル方
向に２０ｎｍ未満の位置まで形成される。すなわち、厚
い絶縁膜１４は、ｎ- 領域１５の内側のチャンネル領域
には形成されないようにする。その結果、図１の第１の
実施の形態では、ホットキャリヤ効果を防止できる上
に、チャンネル領域でのゲート絶縁膜１２の厚さを元来
の厚さのままとすることによりドレイン飽和電流特性を
向上させることができ、高速回路を実現できる。なお、
厚い絶縁膜１４を２〜３ｎｍの厚さに形成することによ
り、上記のような入り込み状態で厚い絶縁膜１４を形成
できる。In the above structure, the thick insulating film 1
4 is formed by penetrating into the central portion (inside) of the polysilicon gate 13 from the edge of the polysilicon gate 13, but in the first embodiment of FIG.
It is formed in a range not exceeding n − region 15 which is an LDD region. For example, n − from the edge of the polysilicon gate 13
Assuming that the region up to the edge of the region 15 is 25 nm, the thick insulating film 14 is formed.
Is formed from the edge of the polysilicon gate 13 to a position less than 20 nm in the channel direction. That is, the thick insulating film 14 is prevented from being formed in the channel region inside the n − region 15. As a result, in the first embodiment shown in FIG. 1, the hot carrier effect can be prevented and the drain saturation current characteristic can be reduced by keeping the gate insulating film 12 in the channel region at the original thickness. And a high-speed circuit can be realized. In addition,
By forming the thick insulating film 14 to have a thickness of 2 to 3 nm, the thick insulating film 14 can be formed in the above-described indented state.
【００１１】図２は本発明の第２の実施の形態を示す。
この第２の実施の形態において、図１と同一部分は図１
と同一符号を付してその説明を省略する。この第２の実
施の形態では、ポリシリコンゲート１３のエッジからポ
リシリコンゲート１３の中央部方向へのｎ- 領域１５の
入り込みが少ないため、厚い絶縁膜１４がｎ- 領域１５
を越えてチャンネル領域側まで入り込んでいるが、この
ように入り込んでも、ｎ- 領域１５が終わった地点から
チャンネル領域側に１０ｎｍ以内に入り込み部が留まる
ように厚い絶縁膜１４が形成される。したがって、この
第２の実施の形態においても、ホットキャリヤ効果を防
止でき、かつ、ドレイン飽和電流特性を向上させること
ができる。FIG. 2 shows a second embodiment of the present invention.
In the second embodiment, the same parts as those in FIG.
The same reference numerals are given and the description is omitted. In the second embodiment, since the n − region 15 is less penetrated from the edge of the polysilicon gate 13 toward the center of the polysilicon gate 13, the thick insulating film 14 is formed in the n − region 15.
However, even if such a penetration occurs, a thick insulating film 14 is formed such that the penetration portion remains within 10 nm from the point where the n − region 15 ends to the channel region side. Therefore, also in the second embodiment, the hot carrier effect can be prevented and the drain saturation current characteristics can be improved.
【００１２】シミュレーションで、厚い絶縁膜１４の厚
さを２〜３ｎｍにして、図１および図２の厚い絶縁膜１
４の形成状態でＭＯＳトランジスタを製造したところ、
厚い絶縁膜の厚さを７〜１７ｎｍにして図３の状態で厚
い絶縁膜を形成した従来のＭＯＳトランジスタに比較し
て、ドレイン飽和電流が約１５％以上向上することを確
認した。従来の構造ではＮ−ＭＯＳＦＥＴで Idsat＝５
８０μA/μm であり、本発明の構造ではIdsat=６５０μ
A/μm の結果が得られた。また、実際製造した場合は、
従来の構造がＮ−ＭＯＳＦＥＴで Idsat＝６００μA/μ
m 、本発明の構造がIdsat=７１０μA/μm であり、実際
製造時は前記のシミュレーションの結果よりも一層良好
な結果を本発明は得た。このような本発明での性能向上
はポリシリコンゲートの大きさが８０％スケールダウン
される効果と同様な効果を生み出すものであって、本発
明の構造によればスケールダウンに伴う特性劣化を防止
し得る。In the simulation, the thickness of the thick insulating film 14 was set to 2-3 nm, and the thickness of the thick insulating film 1 shown in FIGS.
When a MOS transistor was manufactured in the formation state of No. 4,
It has been confirmed that the drain saturation current is improved by about 15% or more as compared with the conventional MOS transistor in which the thickness of the thick insulating film is 7 to 17 nm and the thick insulating film is formed in the state of FIG. In the conventional structure, Idsat = 5 with N-MOSFET
80 μA / μm, and Idsat = 650 μm in the structure of the present invention.
A / μm results were obtained. Also, when actually manufactured,
Conventional structure is N-MOSFET and Idsat = 600μA / μ
m, the structure of the present invention is Idsat = 710 μA / μm, and the present invention actually obtained a better result than that of the above-mentioned simulation at the time of manufacture. Such performance improvement in the present invention produces an effect similar to the effect that the size of the polysilicon gate is reduced by 80%. According to the structure of the present invention, deterioration of characteristics due to scale down is prevented. I can do it.
【００１３】また、本発明によるＭＯＳトランジスタ特
性の改善効果はショ−トチャンネル構造になればなるほ
ど一層大きくなる。これはゲート長さが１／２サブミク
ロンになるに従い、ゲート長さに対する絶縁膜のバーズ
ビーク長さが占める比重が大きくなり、バーズビークが
ＭＯＳトランジスタ特性に与える影響が大きくなるため
である。ゲート長さが短くなればなるほどバーズビーク
長さに伴うドレイン飽和電流の変化は一層大きくなる。
したがって、本発明の構造は、ゲート長さが１／２サブ
ミクロンの素子になるに従い一層重要な要素として作用
する。Further, the effect of improving the MOS transistor characteristics according to the present invention becomes larger as the short channel structure becomes. This is because, as the gate length becomes ミ ク ロ ン submicron, the specific gravity occupied by the bird's beak length of the insulating film with respect to the gate length increases, and the influence of the bird's beak on the MOS transistor characteristics increases. The shorter the gate length, the greater the change in drain saturation current with bird's beak length.
Therefore, the structure of the present invention acts as a more important factor as the gate length becomes a half submicron device.
【００１４】なお、本発明は、上述の実施の形態に限定
されるものではなく、本発明の技術的思想を外れない限
り多様な置換、変形および変更が可能であることは本発
明の属する技術分野で通常の知識を有する者においては
明白である。It should be noted that the present invention is not limited to the above-described embodiment, and that various substitutions, modifications and changes can be made without departing from the technical idea of the present invention. It is obvious to those having ordinary knowledge in the field.
【００１５】[0015]
【発明の効果】以上詳述したように本発明のＭＯＳトラ
ンジスタによれば、ホットキャリヤ効果を防止しなが
ら、ドレイン飽和電流特性も良好となり、高速回路を実
現できる。As described in detail above, according to the MOS transistor of the present invention, the hot carrier effect is prevented, the drain saturation current characteristics are improved, and a high-speed circuit can be realized.
【図１】本発明のＭＯＳトランジスタの第１の実施の形
態を示す断面図。FIG. 1 is a sectional view showing a MOS transistor according to a first embodiment of the present invention;
【図２】本発明のＭＯＳトランジスタの第２の実施の形
態を示す断面図。FIG. 2 is a sectional view showing a MOS transistor according to a second embodiment of the present invention;
【図３】従来のＭＯＳトランジスタを示す断面図。FIG. 3 is a sectional view showing a conventional MOS transistor.
１１ ｐ型シリコン基板 １２ ゲート絶縁膜 １３ ポリシリコンゲート １４ 絶縁膜 １５ ｎ- 領域 １６ ｎ+ 領域Reference Signs List 11 p-type silicon substrate 12 gate insulating film 13 polysilicon gate 14 insulating film 15 n - region 16 n + region
Claims (4)
において、 半導体基板のチャンネル領域上にゲート絶縁膜を介して
ゲートを形成し、該ゲートエッジ部のゲート絶縁膜両端
部にゲート絶縁膜よりも厚い絶縁膜を形成し、該厚い絶
縁膜は前記チャンネル領域側にＬＤＤ領域を越えない範
囲で形成されることを特徴とするＭＯＳトランジスタ。In a MOS transistor having an LDD structure, a gate is formed on a channel region of a semiconductor substrate via a gate insulating film, and an insulating film thicker than the gate insulating film is formed on both ends of the gate insulating film at the gate edge. Wherein the thick insulating film is formed on the channel region side so as not to exceed the LDD region.
類似な性質を有することを特徴とする請求項１記載のＭ
ＯＳトランジスタ。2. The semiconductor device according to claim 1, wherein the thick insulating film has properties similar to those of the gate insulating film.
OS transistor.
において、 半導体基板のチャンネル領域上にゲート絶縁膜を介して
ゲートを形成し、該ゲートエッジ部のゲート絶縁膜両端
部にゲート絶縁膜よりも厚い絶縁膜を形成し、該厚い絶
縁膜は、ＬＤＤ領域が終わる地点からチャンネル領域側
に１０ｎｍ以内に位置することを特徴とするＭＯＳトラ
ンジスタ。3. A MOS transistor having an LDD structure, wherein a gate is formed on a channel region of a semiconductor substrate via a gate insulating film, and an insulating film thicker than the gate insulating film at both ends of the gate insulating film at the gate edge. Wherein the thick insulating film is located within 10 nm from the point where the LDD region ends to the channel region side.
類似な性質を有することを特徴とする請求項３記載のＭ
ＯＳトランジスタ。4. The M according to claim 3, wherein the thick insulating film has properties similar to those of the gate insulating film.
OS transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1997P-51507 | 1997-10-08 | ||
| KR1019970051507A KR19990030993A (en) | 1997-10-08 | 1997-10-08 | Most transistor structure for high speed operation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11121738A true JPH11121738A (en) | 1999-04-30 |
| JP3602963B2 JP3602963B2 (en) | 2004-12-15 |
Family
ID=19522349
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06974998A Expired - Fee Related JP3602963B2 (en) | 1997-10-08 | 1998-03-19 | MOS transistor |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US6218715B1 (en) |
| JP (1) | JP3602963B2 (en) |
| KR (1) | KR19990030993A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030044343A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Transistor in a semiconductor device and a method of manufacturing the same |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6355580B1 (en) * | 1998-09-03 | 2002-03-12 | Micron Technology, Inc. | Ion-assisted oxidation methods and the resulting structures |
| KR100393205B1 (en) * | 2000-05-30 | 2003-07-31 | 삼성전자주식회사 | Memory merged logic semiconductor device of salicided dual gate structure including embedded memory of self-aligned contact structure and Method of manufacturing the same |
| KR100438772B1 (en) * | 2001-08-07 | 2004-07-05 | 삼성전자주식회사 | Method for manufacturing semiconductor device capable to prevent bubble defects |
| KR100557531B1 (en) * | 2004-03-11 | 2006-03-03 | 주식회사 하이닉스반도체 | Semiconductor device and manufacturing method thereof |
| KR100628642B1 (en) * | 2004-12-31 | 2006-09-26 | 동부일렉트로닉스 주식회사 | Formation method of high voltage MOS transistor and high voltage MOS transistor |
| US20070241372A1 (en) * | 2006-04-18 | 2007-10-18 | Ching-Hung Kao | Image sensor device and method of manufacturing the same |
| KR100840661B1 (en) * | 2006-09-13 | 2008-06-24 | 동부일렉트로닉스 주식회사 | Semiconductor device and manufacturing method thereof |
| JP5435720B2 (en) * | 2009-12-21 | 2014-03-05 | パナソニック株式会社 | Semiconductor device |
| US11195754B2 (en) | 2018-10-09 | 2021-12-07 | International Business Machines Corporation | Transistor with reduced gate resistance and improved process margin of forming self-aligned contact |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5146291A (en) * | 1988-08-31 | 1992-09-08 | Mitsubishi Denki Kabushiki Kaisha | MIS device having lightly doped drain structure |
| US5543646A (en) * | 1988-09-08 | 1996-08-06 | Mitsubishi Denki Kabushiki Kaisha | Field effect transistor with a shaped gate electrode |
| KR970011744B1 (en) * | 1992-11-04 | 1997-07-15 | 마쯔시다덴기산교 가부시기가이샤 | Mosfet of ldd type and a method for fabricating the same |
| US5554544A (en) * | 1995-08-09 | 1996-09-10 | United Microelectronics Corporation | Field edge manufacture of a T-gate LDD pocket device |
-
1997
- 1997-10-08 KR KR1019970051507A patent/KR19990030993A/en not_active Application Discontinuation
-
1998
- 1998-03-19 JP JP06974998A patent/JP3602963B2/en not_active Expired - Fee Related
- 1998-09-08 US US09/149,642 patent/US6218715B1/en not_active Expired - Lifetime
-
2001
- 2001-01-10 US US09/757,747 patent/US20010001296A1/en not_active Abandoned
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20030044343A (en) * | 2001-11-29 | 2003-06-09 | 주식회사 하이닉스반도체 | Transistor in a semiconductor device and a method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990030993A (en) | 1999-05-06 |
| US6218715B1 (en) | 2001-04-17 |
| JP3602963B2 (en) | 2004-12-15 |
| US20010001296A1 (en) | 2001-05-17 |
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