JPH11110334A - Data processing circuit and image forming device provided with the circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten processing start time low in request order after finishing processing high in request order by separating/connecting a data bus by a buffer and standing by the output of a control signal low in request priority order. SOLUTION: A video data request is inserted in the process of burst read processing of a device according to the occurrence of the video data request of a RAM 7 from a printer engine 5. When the device outputs an access control signal, a two-way buffer 21 separates the RAM 7 from a data bus of the device. The video data request fetches video data that is designated by a RAM access control signal from the RAM 7 according to a DMA and it is sent to the engine 5. In such cases, a device access control signal and the device which perform burst read become a standby state. A buffer control signal connects the data bus and resumes a burst read operation after video data output of the RAM 7 is finished.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a laser printer,
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image forming apparatus such as a digital copying machine, which relates to a data processing circuit for controlling memory access and an image forming apparatus including the same.

[0002]

2. Description of the Related Art In recent years, multimedia equipment has attracted attention, and data handled therein is processed by converting all of video, audio, characters, and the like into digital signals. In the information to be converted into the digital signal, the amount of the video data is enormous in comparison with the voice and character data.

As a conventional data processing circuit and image forming apparatus for handling data of these digital signals, a memory access control method, a semiconductor integrated circuit to which the method is applied, and an image forming apparatus are disclosed in Japanese Patent Application Laid-Open No. 8-314793. There is a decoding device. The semiconductor integrated circuit and the image decoding device change a plurality of accesses to the memory according to a state of the access at that time, and perform arbitration and scheduling of the memory access according to the changed priority. By doing so, it is configured to prevent concentration on a specific memory access, occurrence of an invalid period, and the like.

Further, in the conventional models, when a request for an access having a higher priority is received during a burst read for processing image data having a particularly large data amount as a digital signal, a burst is generated. Stop the reading halfway (stop the output of all control signals such as address and chip select), start the access with the higher priority, and when the processing is completed, re-output the interrupted control signal and burst read Resume.

Further, contrary to the above operation, during a process of controlling data output of the RAM with a higher priority, refresh control of the RAM, or control of data storage in the RAM, an access request such as a local read to each device is performed. Occurs, after a high-priority process of data output control to the RAM being processed, refresh control, or data storage control is completed, an access control signal for a device that controls each device is output. Processing such as a local read generated as an access request has been performed.

[0006]

However, in a data processing circuit and an image forming apparatus having such a configuration, the invention described in Japanese Patent Application Laid-Open No. 8-314793 described in the above-mentioned conventional example is adapted to the state according to the state. Although the priority is changed, even if an access request with a high priority occurs during an access with a long processing period such as a burst read or the like, it is necessary to wait until the burst read processing is completed.

Further, when the burst read processing is temporarily interrupted and resumed after the processing of the access with a higher priority, the control signals such as the address and the chip select must be output again, and furthermore, the ROM or the ROM must be output. It also takes time due to output delay by individual devices such as IC cards.

In addition, when a process such as a local read which is a data access request of each device having a lower priority occurs during the processing of an access request having a higher priority, an access control signal of the device is transmitted after the process having the higher priority is completed. There is a problem that it takes time until the processing is started because the processing that has occurred in each device is performed by re-outputting.

The present invention is directed to solving the above-mentioned problem of the prior art, and is intended to solve the problem when an access process for a high-priority request occurs during the processing of a burst read (low-priority request). Without completely stopping the processing of the low priority request, the processing of the high priority access is performed in the middle of the processing of the low priority request, and the time until the resumption of the interrupted processing after the end is performed. In addition, the access control signal to the device for the local read (low-priority request) generated during the high-priority access processing is output, and is output after the high-priority access processing is completed. It is an object of the present invention to provide a data processing circuit for shortening the processing start time of a request with a low priority by using an access control signal set, and an image forming apparatus having the same. You.

[0010]

In order to achieve this object, a data processing circuit according to the present invention and an image forming apparatus provided with the data processing circuit are designed to control access to each device such as a ROM and an IC card by controlling a RAM. Data output control or refresh control, and RA
A means for performing arbitration for controlling data storage in the M to have a higher priority, and a bi-directional device shared between the RAM and a device and a data bus RAM connected between the devices and the device. A buffer is provided.

[0011] Also, the RAM and each device are shared,
It has a one-way buffer inserted between the RAM of the data bus connecting between them or each device and the read-only device.

According to the above-mentioned structure, the buffer inserted into the data bus while outputting the access control signal from the device in response to the request having the higher priority to the RAM during the access processing of the request having the lower priority of each device. Each device is separated by the data bus by the buffer control signal to the RAM, and the operation of the request with high priority to the RAM can be performed.

In response to a low priority request of each device during access processing of a high priority request to the RAM, an access control signal from a device separated by a buffer inserted into the data bus is output, and The buffer control signal connects the device and the data bus after the operation of the higher-order request is completed, and the device access processing can be started immediately using the access control signal of the device that has been output earlier. it can.

[0014]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a controller of a printer as an example of an image forming apparatus according to a first embodiment of the present invention. In FIG. 1, 1 is a controller, 2 is a host computer, 3 is a disk drive including a flexible disk device or a hard disk device for storing various data such as font data, programs, print data, etc.
Reference numeral 4 denotes an operation panel for notifying the user of the current state of the apparatus and inputting for giving a mode instruction. Reference numeral 5 denotes a printer engine for performing an operation for actually printing and outputting.

Reference numeral 6 denotes a CPU for controlling the entire controller 1 by a program stored in a program ROM described later, a mode instruction input from the operation panel 4, and a command from the host computer 2, and 7 denotes a work of the CPU 6. Memory, input buffer memory for input data, page buffer memory for print data,
RAM used for download font memory, etc.
Reference numeral 8 denotes a non-volatile memory (NVRAM) that stores the contents of a mode instruction input from the operation panel 4, 9 denotes a program ROM in which a program for controlling the controller 1 is stored, 10 denotes font pattern data, and the like. Is an IC card which stores font data and programs and supplies them from outside the apparatus.

Further, reference numeral 12 denotes a host I / F which communicates with the host computer 2 and which normally has a standard such as Centronics I / F (interface) and RS-232C;
Is a disk I / O for communicating with the disk drive 3.
F and 14 are panel I / Fs for communicating commands and status with the operation panel 4, and 15 is an engine I for communicating commands, status and print data with the printer engine 5.
/ F, 16 are Centronics, RS-232C and Appl
e talk, TCP / IP protocol network etc.
Host computer 2 having an I / F and corresponding to each I / F
It is an option board that can receive data from such as.

FIG. 2 shows a data processing circuit according to the first embodiment, and is a block diagram showing an example of a data bus connection configuration. Here, components corresponding to the components described in FIG. 1 are indicated by the same reference numerals. FIG.
, 5 is a printer engine, 6 is a CPU, 7 is R
AM and 8 are NVRAM, 9 is a program ROM, 10 is a font ROM, 11 is an IC card, 16 is an option board, 20 is an ASIC having functions such as CPU I / F, engine I / F, access signal control, data bus control and the like. (Appli
cation specific integrated circuit), 21 is ASI
RAM 7 connected via a common data bus with C20
And a bidirectional buffer composed of a tri-state gate and a bidirectional buffer for separating / connecting other devices such as NVRAM 8, program ROM 9, font ROM 10, IC card 11, etc., and 22 is another ASIC. FIG. 3 is a timing chart showing the relationship between control signals of the data processing circuit shown in FIG. 2 of the first embodiment.

A data bus connection of a data processing circuit as shown in the block diagram of FIG. 2 is configured in the controller 1 of the printer according to the first embodiment thus configured, and the memory access by the data processing circuit is performed. The control operation will be described with reference to the timing chart of FIG.

First, as shown in FIG. 2, when a request for outputting (higher priority) video data stored in the RAM 7 occurs from the printer engine 5 connected to the ASIC 20, for example, the RAM 7 is shared. Assume that the IC card 11, which is one of the devices, is performing a burst read (low priority request) operation via the data bus.

At the break (R7 to R0) of the burst read process for each clock shown in FIG. 3, the ASIC 20 inserts a video data output request process. At this time, R
At the timing of arrow 1 (arrow A shown in FIG. 3), the device access control signals (ADDress, / C
S, / Read) is output and the buffer control signal (D
By IR (/ OE) (signal change is not shown), the bidirectional buffer 21 separates the RAM 7 from other devices (in this example, the IC card 11) on the data bus. Thus, the processing of the video data request is performed by the DMA,
The video data designated by the RAM access control signal is taken into the ASIC 20 from the M7, and the printer engine 5
To be printed out. At this time, the device access control signal previously performing the burst read is R5 (FIG. 3).
In the state shown by the arrow B), the device is in a standby state. After the output of the video data from the RAM 7 is completed, the connection of the data bus disconnected by the buffer control signal is performed, and the process shifts to R6 next to R5 to restart the burst read operation.

As described above, the data bus is connected to the bidirectional buffer.
By separating the RAM 7 from the other devices by means of 21, it is possible to reduce the load on the data bus corresponding to requests having different priorities, and further reduce the output delay due to each device outputting data again during the middle of a burst read. It is possible to shorten the restart processing time of the interrupted burst read.

Next, FIG. 4 shows Embodiment 2 of the present invention.
3 is a block diagram illustrating a data processing circuit provided in the image forming apparatus of FIG. Here, FIG. 4 has substantially the same configuration as FIG. 2 showing the first embodiment, and substantially the same components corresponding to the components are denoted by the same reference numerals and are indicated by the same reference numerals. The different parts will be omitted, and only different parts will be described. In FIG. 4, reference numeral 2 denotes a host computer connected to an ASIC described later via a Centronics I / F, and 23 denotes a CPU I / F and an engine I / F.
An ASIC having functions such as F, host I / F, access signal control, and data bus control. FIG. 5 is a timing chart showing the relationship between control signals of the data processing circuit shown in FIG. 4 of the second embodiment.

FIG. 4 is a block diagram showing an example of a data bus connection configuration of the data processing circuit configured as described above, and the operation of memory access control by the data processing circuit will be described with reference to the timing chart of FIG. I do.

During data output control (high-priority request) of video data to be printed between the printer engine 5 and the RAM 7, an access (low-priority) request such as a local read request from each device is performed. Occurs (arrow C shown in FIG. 5), at the timing of R1, the device access control signal (ADDress //
(CS, / Read) is output. At this time, since the data output control of the RAM 7 is in the process of being accessed, the buffer control signal is in the state of (/ CE; H), and each device is separated from the data bus by the bidirectional buffer 21. Then, R5 (arrow D shown in FIG. 5)
When it is confirmed that the control processing is completed, the buffer control signal is changed to (/ CE; L) in the next R6.
In this state, the device that has generated the access request is connected to the data bus, and an access request such as a local read by the device access control signal that has been waiting in the output state is immediately executed.

In the first and second embodiments, a case has been described in which video data is read from the RAM 7 as data output control during a burst read. However, the refresh operation of the RAM 7 and the transfer from the host computer 2 to the RAM 7 are performed. Even in the case of control for performing a data storage operation, the same operation as described above can be performed.

FIG. 6 shows Embodiment 3 of the present invention.
3 is a block diagram illustrating a data processing circuit provided in the image forming apparatus of FIG. Here, FIG. 6 is substantially the same as that of FIG. 4 showing the second embodiment, except that the bidirectional buffer 21 of FIG. 4 is replaced with a one-way buffer described later. RAM 7 or between each device and a read-only device. In FIG.
24 is an ASIC2 connected via a common data bus
3, a device such as RAM7 and NVRAM8, and a program RO which is another read-only device.
It is a one-way buffer comprising a one-way buffer for separating / connecting M9, font ROM 10, and IC card 11, and a tri-state gate.

In the third embodiment having the above-described configuration, as described in the first or second embodiment, a request having a low priority (burst read from a read-only device) is performed. Etc.) during the access processing of the RAM 7 when a high-priority request is issued as a data output operation, or during the access processing of a high-priority request, a low-priority request (from a read-only device). The operation when a local read or the like occurs is similar except that the operation is performed by a read-only device using a one-way buffer 24 instead of the two-way buffer 21, and a detailed description thereof will be omitted. In the third embodiment, the IC card 11 is described as a read-only device. However, the printer controller described in the third embodiment is used for storing font data and programs and supplying the data from outside the apparatus. It is also possible to write according to the purpose of another use,
It is not limited to this purpose of use.

As described above, in each device disconnected from the data bus by the bidirectional buffer 21 or the unidirectional buffer 24, when an access request occurs, the device waits for a device access control signal to be output, and a process with a higher priority is performed. When each device is connected by the bidirectional buffer 21 (one-way buffer 24) according to the buffer control signal, the device access control signal that has been waiting can be obtained immediately, and the access request that has occurred can be obtained. Can be performed.

[0029]

As described above, according to the present invention,
By providing a bidirectional (one-way) buffer on the data bus shared and connected to the RAM and each device, the load of the switching operation corresponding to each priority of the data bus is reduced, and the data propagation delay is suppressed. Further, during a process that occupies the data bus for a long period of time, such as a burst read between the RAM and each device, the time for resuming the process even if the process is interrupted can be reduced.
As a result, the processing speed can be increased.

Further, a device access control signal, which is a low-priority access request such as a local read of each device generated during the high-priority access processing, is made to wait for output, and after completion of the high-priority access processing, The buffer control signal has the effect of shortening the acquisition time of the device access control signal when connecting the device in which the bidirectional (one-way) buffer is on standby to the data bus, and improving the processing speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a printer controller as an example of an image forming apparatus according to a first embodiment of the present invention;

FIG. 2 is a data processing circuit according to the first embodiment, and is a block diagram illustrating a connection configuration example of a data bus.

FIG. 3 is a timing chart showing a relationship between control signals of the data processing circuit shown in FIG. 2 of the first embodiment;

FIG. 4 is a block diagram showing a data processing circuit provided in the image forming apparatus according to the second embodiment of the present invention, showing a connection configuration example of a data bus;

FIG. 5 is a timing chart showing a relationship between control signals of the data processing circuit shown in FIG. 4 according to the second embodiment;

FIG. 6 is a block diagram showing a data processing circuit provided in the image forming apparatus according to the third embodiment of the present invention, showing a connection configuration example of a data bus;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Controller 2 Host computer 3 Disk drive 4 Operation panel 5 Printer engine 6 CPU 7 RAM 8 NVRAM 9 Program ROM 10 Font ROM 11 IC card 12 Host I / F 13 Disk I / F 14 Panel I / F 15 Engine I / F 16 Option board 20, 23 ASIC 21 Bidirectional buffer 22 Another ASIC 24 Unidirectional buffer.

Claims (11)

[Claims] 1. An access control to each device such as a ROM and an IC card, a data output control of a RAM, a refresh control to a RAM, or an R
A data processing circuit that performs arbitration in which data storage control to the AM has a higher priority. The data processing circuit is shared by the RAM and the devices, and is connected between the RAM of a data bus connecting the devices and the devices. A data processing circuit comprising a bidirectional buffer inserted into the data processing circuit. 2. A data output control of a RAM, a refresh control to a RAM, or a control from a host computer by controlling access to each device such as a ROM and an IC card.
A data processing circuit that performs arbitration in which data storage control to the AM has a higher priority. The data processing circuit is shared by the RAM and the devices and is read-only to the RAM of the data bus connecting the devices or the devices. A data processing circuit comprising a one-way buffer inserted between the device and the device. 3. The data processing circuit is inserted into a data bus while outputting an access control signal from a device in response to a request with a high priority to a RAM during access processing of a request with a low priority of each device. 3. The data processing circuit according to claim 1, wherein the device is separated by the data bus according to a buffer control signal of the buffer, and an operation of a request with a high priority to the RAM is performed. 4. The data processing circuit according to claim 2, wherein the low-priority request of each device during access processing of the high-priority request to the RAM causes an access control signal from a device separated by a buffer inserted into the data bus. 3. The device according to claim 1, wherein after the operation of the higher priority request is completed, the device and the data bus are connected by a buffer control signal to perform the operation of the lower priority request. Data processing circuit. 5. A data output control of a RAM, a refresh control to a RAM, or a control from a host computer by controlling access to each device such as a ROM and an IC card.
A means for performing arbitration for controlling data storage in the AM to have a higher priority, and shared between the RAM and the devices and inserted between the RAM and a data bus RAM connecting the devices and the devices. An image forming apparatus having a data processing circuit having a bidirectional buffer, wherein an access control signal from a device is changed by a high priority request to the RAM during access processing of a low priority request of each device. Image forming, wherein the device is separated by the data bus by a buffer control signal of the bidirectional buffer inserted into the data bus while outputting the data, and an operation of a request with a high priority to the RAM is performed. apparatus. 6. A data output control of a RAM, a refresh control to a RAM, or an R control from a host computer by controlling access to each device such as a ROM and an IC card.
A means for performing arbitration for controlling data storage in the AM to have a higher priority, and shared between the RAM and the devices and inserted between the RAM and a data bus RAM connecting the devices and the devices. An image forming apparatus having a data processing circuit having a bidirectional buffer, wherein the device is inserted into the data bus by a low-priority request of each device during access processing of a high-priority request to the RAM. An access control signal is output from a device separated by the bidirectional buffer, and after the operation of the high priority request is completed, the device and the data bus are connected by a buffer control signal to perform the operation of the low priority request. An image forming apparatus, comprising: 7. A data output control of a RAM, a refresh control to a RAM, or a control from a host computer by controlling access to each device such as a ROM and an IC card.
A means for performing arbitration for controlling data storage in the AM to have a higher priority, and a RAM shared by the RAM and the devices and a RAM of a data bus connecting between the devices or a read-only device. An image forming apparatus having a data processing circuit having a one-way buffer inserted between the read-only device, wherein during the access process of the low-priority request of the read-only device, a high-priority request to the RAM, While the access control signal from the device is output, the device is separated by the data bus by the buffer control signal of the one-way buffer inserted into the data bus, and the operation of a request with a high priority to the RAM is performed. An image forming apparatus comprising: 8. A data output control of the RAM, a refresh control to the RAM, or a control from the host computer by controlling access to each device such as a ROM and an IC card.
A means for performing arbitration for controlling data storage in the AM to have a higher priority, and a RAM shared by the RAM and the devices and a RAM of a data bus connecting between the devices or a read-only device. An image forming apparatus having a data processing circuit having a one-way buffer inserted between the RAMs, wherein a low-priority request of the read-only device during access processing of a high-priority request to the RAM includes: Outputting an access control signal from a device separated by a one-way buffer inserted into the data bus, connecting the device and the data bus by a buffer control signal after completion of the operation of the request having the higher priority, and An image forming apparatus that performs an operation of a request with a low rank. 9. The access control of a request with a high priority to the RAM in the image forming apparatus includes a data output operation of fetching video data from the RAM and outputting the video data to a printer engine for performing print output, a refresh operation of the RAM, or 9. The image forming apparatus according to claim 5, wherein the operation is one of a data storage operation from a host computer to the RAM. 10. The image forming apparatus according to claim 5, wherein the access control of a low priority request of each device in the image forming apparatus is a burst read operation or a local read operation of each device. apparatus. 11. An access control for a request having a low priority of a read-only device in the image forming apparatus,
8. The operation of a burst read or a local read of the read-only device.
Or the image forming apparatus according to 8.