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JPH1093242A - Printed wiring board - Google Patents

Printed wiring board

Info

Publication number
JPH1093242A
JPH1093242A JP24636496A JP24636496A JPH1093242A JP H1093242 A JPH1093242 A JP H1093242A JP 24636496 A JP24636496 A JP 24636496A JP 24636496 A JP24636496 A JP 24636496A JP H1093242 A JPH1093242 A JP H1093242A
Authority
JP
Japan
Prior art keywords
conductor
wiring board
printed wiring
face
bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP24636496A
Other languages
Japanese (ja)
Other versions
JP3633136B2 (en
Inventor
Kenji Hirohata
賢治 廣畑
Minoru Mukai
稔 向井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP24636496A priority Critical patent/JP3633136B2/en
Publication of JPH1093242A publication Critical patent/JPH1093242A/en
Application granted granted Critical
Publication of JP3633136B2 publication Critical patent/JP3633136B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Manufacturing Of Printed Wiring (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a printed wiring board which has a structure such that through-wiring path may be constituted of conductor bumps, and which is free of an interfacial peel-off which can be caused easily, in an interface between an end face of each conductor bump and a part of a conductor pattern to be electrically connected to the end face of the conductor bump by a difference between coefficients of linear expansion of the constituent materials of the bump and the pattern, and which can have high reliability in both the mechanical and electrical connections. SOLUTION: In a printed wiring board provided with insulating material layers 2, conductor bumps 3 which pass through the insulating material layers 2 and form wiring path, conductor patterns 6a which, being located airtightly on the surface of the insulator material layer 2, have sections 22 to be electrically connected to end faces 4 of the conductor bumps 3. The sections 22 are as large as or less than the size of the end faces 4 and are located within the projected images, which are obtained by projecting the end faces 4 in the direction of the conductor bumps 3 passing through the insulator layers 2.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、機械的および電気
的な接続の信頼性確保を図れるようにした印刷配線基板
に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board capable of ensuring the reliability of mechanical and electrical connections.

【0002】[0002]

【従来の技術】周知のように、最近では、電子機器の小
型・軽量化、高速化、多機能化、高信頼性化の要求が益
々高まっている。このようなことから、電子機器に組込
まれる半導体集積回路素子の高集積化および高速化が推
進されている。
2. Description of the Related Art As is well known, recently, there has been an increasing demand for smaller, lighter, faster, multifunctional, and more reliable electronic devices. For these reasons, high integration and high speed of semiconductor integrated circuit elements incorporated in electronic devices are being promoted.

【0003】ところで、電子機器に半導体集積回路素子
を組込む場合には、通常、半導体集積回路素子をパッケ
ージングし、これらのパッケージを印刷配線基板上に実
装し、この印刷配線基板を電子機器に組込む方式が採ら
れている。この場合、半導体集積回路素子の内部での電
気信号伝播遅延に比較して印刷配線基板を経由するパッ
ケージ間配線による電気信号伝播遅延の影響を無視でき
ない場合には、これによって電子機器の性能が律束され
かねないことになる。すなわち、半導体集積回路素子の
高集積化および高速化を図っても、印刷配線基板を経由
する配線路の電気信号伝播遅延が大きい場合には、この
伝播遅延によって電子機器の性能が決定されてしまう。
したがって、高密度実装化と高速信号伝送化とを達成す
る配線基板技術が必要不可欠となる。
When a semiconductor integrated circuit device is incorporated in an electronic device, the semiconductor integrated circuit device is usually packaged, these packages are mounted on a printed wiring board, and the printed wiring substrate is incorporated in the electronic device. The method is adopted. In this case, if the influence of the electric signal propagation delay due to the wiring between the packages via the printed wiring board cannot be neglected as compared with the electric signal propagation delay inside the semiconductor integrated circuit element, the performance of the electronic device is thereby limited. It could be bundled. That is, even if the integration degree and speed of the semiconductor integrated circuit element are increased, if the electric signal propagation delay of the wiring path passing through the printed wiring board is large, the performance of the electronic device is determined by the propagation delay. .
Therefore, a wiring board technology that achieves high-density mounting and high-speed signal transmission is indispensable.

【0004】こうしたことから、最近、従来の印刷配線
基板とは違って多層化が容易な構造の印刷配線基板が提
案されている。この新たに提案された印刷配線基板は、
ドリルによる孔開け工程や複雑なメッキ工程を必要とせ
ずに多層化を実現できるもので、たとえば4層構成のも
のは図3に示すように構成されている。
[0004] For these reasons, recently, there has been proposed a printed wiring board having a structure that can be easily multilayered unlike conventional printed wiring boards. This newly proposed printed wiring board,
A multi-layer structure can be realized without a drilling step or a complicated plating step. For example, a four-layer structure is configured as shown in FIG.

【0005】すなわち、この印刷配線基板1は、絶縁材
層2と、この絶縁材層2を貫通して配線路を形成する導
電体バンプ3と、絶縁材層2の表面に密着配置されて導
電体バンプ3の端面4に電気的に接続される部分5を備
えた導電体パターン6とを基本要素7とし、この基本要
素7を複数積層した構成となっている。
That is, the printed wiring board 1 includes an insulating material layer 2, a conductive bump 3 that penetrates the insulating material layer 2 to form a wiring path, and a conductive material that is disposed in close contact with the surface of the insulating material layer 2. A conductor pattern 6 having a portion 5 electrically connected to the end face 4 of the body bump 3 is used as a basic element 7, and a plurality of the basic elements 7 are stacked.

【0006】ここで、この印刷配線基板1の製造方法に
ついて図5を参照しながら簡単に説明する。まず、図5
(a) に示すように、たとえば厚さが20μmの電解銅箔1
1を用意する。次に、この電解銅箔11の図中上面に、
たとえば厚さが200 μmで、所定箇所にたとえば0.3mm
径の孔を複数有したステンレス製のメタルマスクを当て
がって位置決めする。次に、このメタルマスクに設けら
れた孔を使ってたとえば銀系の導電ペーストを電解銅箔
11の図中上面に印刷する。この導電ペーストを乾燥さ
せた後に、再び同じメタルマスクを使って同一位置に導
電ペーストを印刷して乾燥させ、この作業を必要回数繰
り返して、電解銅箔11の図中上面に高さが200 μm程
度の導電体バンプ12を形成する。勿論、1回の印刷工
程で導電体バンプ12を形成することもできる。
Here, a method of manufacturing the printed wiring board 1 will be briefly described with reference to FIG. First, FIG.
As shown in (a), for example, an electrolytic copper foil 1 having a thickness of 20 μm
Prepare 1 Next, on the upper surface of the electrolytic copper foil 11 in the drawing,
For example, with a thickness of 200 μm and 0.3 mm
Positioning is performed by applying a stainless metal mask having a plurality of holes having a diameter. Next, using a hole provided in the metal mask, for example, a silver-based conductive paste is printed on the upper surface of the electrolytic copper foil 11 in the drawing. After this conductive paste was dried, the conductive paste was printed again at the same position using the same metal mask and dried, and this operation was repeated as many times as necessary, so that the height of the upper surface of the electrolytic copper foil 11 in the figure was 200 μm. Conductor bumps 12 are formed to a degree. Of course, the conductor bumps 12 can be formed in a single printing process.

【0007】次に、導電体バンプ12が突出している側
に、たとえばガラスクロスにエポキシ樹脂を含浸させ
た、たとえば厚さが150 μmの合成樹脂系シート13を
載せ、この合成樹脂系シート13の上に厚さ3mm 程度の
シリコーンゴム板で形成された当て板を載置する。次
に、この積層体を加熱・加圧・冷却機構付きのプレス装
置にセットし、まず全体をたとえば120 ℃まで温度上昇
させた状態で当て板を介して合成樹脂系シート13を電
解銅箔11へ押し付け、その後に冷却する。
Next, a synthetic resin sheet 13 having a thickness of, for example, 150 μm, for example, in which glass cloth is impregnated with an epoxy resin, is placed on the side from which the conductive bumps 12 protrude. A patch plate made of a silicone rubber plate with a thickness of about 3 mm is placed on top. Next, the laminate is set on a press device equipped with a heating, pressurizing and cooling mechanism. And then cooled.

【0008】上述した加熱、押圧、冷却工程によって、
図5(b) に示すように、各導電体バンプ12が合成樹脂
系シート13を貫通した積層体14を得る。次に、積層
体14の上面、つまり導電体バンプ12の先端部が突出
している側に、たとえば厚さが20μmの電解銅箔15を
載置し、この上に堅い当て板を載置する。次に、この積
層体を加熱・加圧・冷却機構付きのプレス装置にセット
し、全体をたとえば170 ℃まで温度上昇させた状態で当
て板を介して電解銅箔15を積層体14へ押圧し、一定
時間経過後に徐冷する。
By the above-mentioned heating, pressing and cooling steps,
As shown in FIG. 5B, a laminate 14 in which each conductive bump 12 penetrates the synthetic resin sheet 13 is obtained. Next, an electrolytic copper foil 15 having a thickness of, for example, 20 μm is placed on the upper surface of the laminated body 14, that is, on the side from which the tip of the conductive bump 12 protrudes, and a rigid backing plate is placed thereon. Next, this laminate is set on a press device having a heating, pressurizing and cooling mechanism, and while the whole is heated to, for example, 170 ° C., the electrolytic copper foil 15 is pressed against the laminate 14 via a backing plate. After a certain time, cool slowly.

【0009】この工程によって、図5(c) に示すよう
に、両面が銅箔張りで、両面の銅箔間が導電体バンプ1
2によって電気的に接続された印刷配線基板要素16を
得る。次に、図5(d) に示すように、両面の銅箔をエッ
チングによって必要な形状に加工して導電体パターン1
7を形成する。したがって、図3と対応させると、合成
樹脂系シート13が絶縁材層2に、導電体バンプ12が
導電体バンプ3に、導電体パターン17が導電体パター
ン6に対応していることになる。
By this step, as shown in FIG. 5C, both sides are covered with copper foil, and the conductive bumps 1 are formed between the copper foils on both sides.
2 to obtain the printed wiring board elements 16 electrically connected to each other. Next, as shown in FIG. 5 (d), the copper foil on both sides is processed into a required shape by etching, and the conductor pattern 1 is formed.
7 is formed. Therefore, when corresponding to FIG. 3, the synthetic resin sheet 13 corresponds to the insulating material layer 2, the conductor bumps 12 correspond to the conductor bumps 3, and the conductor patterns 17 correspond to the conductor patterns 6.

【0010】なお、図3には4層構成の印刷配線基板1
が示されているが、この印刷配線基板1を形成するとき
には、図5(d) に示す要素の両面に、図5(b) に示す積
層体14を導電体バンプ12の頂部が導電体パターン1
7に接触するようにそれぞれ当てがって所定温度まで昇
温させ、この状態で各積層体14を押圧し、一定時間経
過後に徐冷する。このようにして得られた積層体の両面
に存在している銅箔をエッチングによって必要な形状に
加工して導電体パターン6を形成する。このように導電
体バンプ3で貫通配線路を形成する構造であると、上述
した手法で多層の印刷配線基板を簡単に製作できる。
FIG. 3 shows a printed wiring board 1 having a four-layer structure.
However, when the printed wiring board 1 is formed, the laminate 14 shown in FIG. 5B is provided on both sides of the element shown in FIG. 1
Each of the laminates 14 is pressed so as to come in contact with 7 and is heated to a predetermined temperature. In this state, each of the laminates 14 is pressed and gradually cooled after a certain period of time. The copper foil present on both sides of the laminate thus obtained is processed into a required shape by etching to form the conductor pattern 6. With such a structure in which the through wiring path is formed by the conductive bumps 3, a multilayer printed wiring board can be easily manufactured by the above-described method.

【0011】しかしながら、上記のように構成された印
刷配線基板にあっても次のような問題が残されていた。
すなわち、このような高密度実装の可能な印刷配線基板
に半導体パッケージを実装するときには、面実装形態、
具体的にははんだバンプを用いるBGA(Ball Grid Ar
ray)構成が採用される。このBGA構成では、半導体パ
ッケージ側に設けられた各電極にはんだバンプを設けて
おき、これらはんだバンプと印刷配線基板に設けられた
各電極パターンとを接触させ、この状態でリフロー処理
し、各はんだバンプを溶融させて機械的および電気的に
接続する方式が採用される。
However, the following problems still remain in the printed wiring board configured as described above.
That is, when mounting a semiconductor package on a printed wiring board capable of such high-density mounting, the surface mounting form,
Specifically, BGA (Ball Grid Ar) using solder bumps
ray) configuration. In this BGA configuration, solder bumps are provided on the respective electrodes provided on the semiconductor package side, and these solder bumps are brought into contact with the respective electrode patterns provided on the printed wiring board. A method of melting and mechanically and electrically connecting the bumps is adopted.

【0012】このようなリフロー処理時には印刷配線基
板が高温に加熱される。このとき、絶縁材層2、導電体
バンプ3、導電体パターン6の各構成材料の線膨張率が
一致していれば格別問題とはならないが、通常、これら
の構成材料は線膨張率が異なるので、この線膨張率の違
いに起因して構成材料間の界面に熱応力が生じる。
During such a reflow process, the printed wiring board is heated to a high temperature. At this time, there is no particular problem if the linear expansion coefficients of the constituent materials of the insulating material layer 2, the conductive bumps 3, and the conductive patterns 6 match, but these constituent materials usually have different linear expansion coefficients. Therefore, thermal stress is generated at the interface between the constituent materials due to the difference in the coefficient of linear expansion.

【0013】従来の印刷配線基板1では、導電体バンプ
3の端面4に電気的に接続される導電体パターン6の部
分5が端面4より大きく形成されているので、特に部分
5と端面4との界面21に大きな熱応力が発生する虞が
あった。すなわち、絶縁材層2をたとえばガラスエポキ
シ樹脂で形成した場合、この材料の200 ℃における厚み
方向(印刷配線基板の厚み方向)の線膨張率は15×10-5
(1/℃) である。一方、導電体バンプ3を銀ペーストで
形成した場合、この材料の200 ℃における厚み方向の線
膨張率は3 ×10-5(1/℃) である。したがって、ガラス
エポキシ樹脂と銀ペーストとの組合せでは、リフロー処
理時に、線膨張率の違いによって部分5を端面4から引
き剥がすような大きな熱応力が界面21に発生し、これ
が原因して界面剥離が起こり、機械的および電気的な接
続の信頼性が低下する虞がある。これは、ガラスエポキ
シ樹脂と銀ペーストとの組合せに限らず、絶縁物と導電
体との組合せでは共通に同様の問題が発生する虞があっ
た。
In the conventional printed wiring board 1, the portion 5 of the conductor pattern 6 electrically connected to the end face 4 of the conductor bump 3 is formed to be larger than the end face 4. There is a possibility that a large thermal stress may be generated at the interface 21 of the substrate. That is, when the insulating material layer 2 is formed of, for example, a glass epoxy resin, the linear expansion coefficient of this material in the thickness direction at 200 ° C. (the thickness direction of the printed wiring board) is 15 × 10 −5.
(1 / ° C). On the other hand, when the conductor bump 3 is formed of a silver paste, the linear expansion coefficient of this material in the thickness direction at 200 ° C. is 3 × 10 −5 (1 / ° C.). Therefore, in the combination of the glass epoxy resin and the silver paste, a large thermal stress is generated at the interface 21 at the time of the reflow treatment, such that the portion 5 is peeled off from the end face 4 due to a difference in the coefficient of linear expansion. As a result, the reliability of mechanical and electrical connections may be reduced. This is not limited to the combination of the glass epoxy resin and the silver paste, but the same problem may occur in common with the combination of the insulator and the conductor.

【0014】[0014]

【発明が解決しようとする課題】上述の如く、導電体バ
ンプで貫通配線路を形成する構造を採用した従来の印刷
配線基板にあっては、構成材料の線膨張率の違いに起因
して、特にはんだリフロー処理時に、導電体バンプの端
面と導電体パターンの上記端面に接続されている部分と
の界面において界面剥離が生じ、機械的および電気的な
接続の信頼性が低下する虞があった。
As described above, in a conventional printed wiring board adopting a structure in which a through wiring path is formed by a conductive bump, a difference in the coefficient of linear expansion of a constituent material causes a problem. In particular, at the time of the solder reflow treatment, interface separation occurs at the interface between the end face of the conductor bump and the portion connected to the end face of the conductor pattern, and there is a concern that the reliability of mechanical and electrical connection may be reduced. .

【0015】そこで本発明は、上述した不具合を効果的
に解消でき、もって導電体バンプで貫通配線路を形成す
る構造の特徴を最大限に発揮させ得る印刷配線基板を提
供することを目的としている。
It is an object of the present invention to provide a printed wiring board which can effectively solve the above-mentioned disadvantages and thereby maximize the features of the structure in which the through wiring path is formed by the conductive bumps. .

【0016】[0016]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、絶縁材層と、この絶縁材層を貫通して配
線路を形成する導電体バンプと、前記絶縁材層の表面に
密着配置されて前記導電体バンプの端面に電気的に接続
される部分を持つ導電体パターンとを備えてなる印刷配
線基板において、前記導電体パターンの前記導電体バン
プに電気的に接続される部分は、前記端面の大きさ以下
の大きさで、かつ上記端面を上記導電体バンプの貫通方
向に投影して得られる投影像内に位置していることを特
徴としている。
SUMMARY OF THE INVENTION To achieve the above object, the present invention provides an insulating material layer, a conductor bump penetrating the insulating material layer to form a wiring path, and a surface of the insulating material layer. And a conductive pattern having a portion electrically connected to an end face of the conductive bump, the conductive pattern being electrically connected to the conductive bump of the conductive pattern. The portion is not larger than the size of the end face, and is located in a projected image obtained by projecting the end face in a direction in which the conductive bump penetrates.

【0017】なお、前記導電体パターンの前記導電体バ
ンプに電気的に接続される部分のうちの幾つかの部分
は、一部または全部が上記導電体バンプの前記端面部分
に埋め込まれていてもよい。
It is to be noted that some or all of the portions of the conductor pattern that are electrically connected to the conductor bumps may be partially or entirely embedded in the end surface portions of the conductor bumps. Good.

【0018】本発明に係る印刷配線基板では、導電体バ
ンプの端面に電気的に接続される導電体パターンの部分
が、導電体バンプの端面の大きさ以下の大きさで、かつ
上記端面を上記導電体バンプの貫通方向に投影して得ら
れる投影像内に位置している。このため、絶縁材層の構
成材料と導電体バンプの構成材料との厚み方向の線膨張
率が異なっていても、導電体バンプの端面と導電体パタ
ーンの上記端面に電気的に接続される部分との界面に大
きな熱応力が生じるのを抑制できる。この結果、はんだ
リフロー処理後の信頼性を確保することができる。
In the printed wiring board according to the present invention, the portion of the conductor pattern electrically connected to the end face of the conductor bump has a size equal to or smaller than the size of the end face of the conductor bump, and It is located in the projected image obtained by projecting in the penetrating direction of the conductor bump. Therefore, even if the linear expansion coefficient in the thickness direction of the constituent material of the insulating material layer and the constituent material of the conductor bump are different, the portion electrically connected to the end face of the conductor bump and the end face of the conductor pattern A large thermal stress can be prevented from being generated at the interface with the substrate. As a result, reliability after the solder reflow process can be ensured.

【0019】[0019]

【発明の実施の形態】以下、図面を参照しながら発明の
実施形態を説明する。図1には本発明の一実施形態に係
る4層構成の印刷配線基板1aの概略構成が示されてい
る。なお、この図では図3と同一機能部分が同一符号で
示されている。この印刷配線基板1aは図5で説明した
方法で形成されている。
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a schematic configuration of a four-layer printed wiring board 1a according to an embodiment of the present invention. In this figure, the same functional parts as those in FIG. 3 are indicated by the same reference numerals. This printed wiring board 1a is formed by the method described with reference to FIG.

【0020】この例に係る印刷配線基板1aが従来の印
刷配線基板と異なる点は、絶縁材層2の表面に密着配置
されて導電体バンプ3の端面4に電気的に接続される部
分22を持つ導電体パターン6aの構造にある。具体的
には、部分22の大きさおよび位置にある。すなわち、
部分22は、端面4の大きさ以下の大きさで、かつ端面
4を導電体バンプ3の貫通方向に投影して得られる投影
像内に位置している。この例において、部分22は、端
面4の大きさと同じ大きさで、かつ端面4の投影像から
はみ出さないように設けられている。
The printed wiring board 1a according to this embodiment is different from the conventional printed wiring board in that a portion 22 which is closely attached to the surface of the insulating material layer 2 and is electrically connected to the end face 4 of the conductor bump 3 is provided. In the structure of the conductive pattern 6a. Specifically, it is at the size and position of the portion 22. That is,
The portion 22 has a size equal to or smaller than the size of the end face 4 and is located in a projected image obtained by projecting the end face 4 in a direction in which the conductive bump 3 penetrates. In this example, the portion 22 is provided so as to have the same size as the size of the end face 4 and not protrude from the projected image of the end face 4.

【0021】なお、導電体バンプ3の端面4に電気的に
接続される部分22の形状に制約はないが通常、円形が
採用される。導電体パターン6aの形成は、図5を用い
て一部説明したように、導電性金属箔上にエッチングレ
ジストインクをスクリーン印刷し、導電体パターンとな
る部分をマスクしてから、塩化第2銅をエッチング液と
してエッチング処理し、続いてレジストマスクを剥離す
ることによって得られる。このとき、導電体バンプ3の
端面4に接触して電気的に接続される部分22が、端面
4の大きさ以下の大きさで、かつ端面4を導電体バンプ
3の貫通方向に投影して得られる投影像内で接触するよ
うにマスクの大きさおよび位置を設定することによって
上述した条件を満たす導電体パターン6aを形成するこ
とができる。
The shape of the portion 22 electrically connected to the end face 4 of the conductor bump 3 is not limited, but a circle is usually employed. The formation of the conductor pattern 6a is performed by partially printing the etching resist ink on the conductive metal foil and masking the portion to be the conductor pattern, as described partially with reference to FIG. Is used as an etching solution, followed by removing the resist mask. At this time, the portion 22 which is in contact with and electrically connected to the end face 4 of the conductor bump 3 is smaller than the size of the end face 4 and the end face 4 is projected in the penetrating direction of the conductor bump 3. By setting the size and position of the mask so as to make contact with each other in the obtained projected image, the conductive pattern 6a satisfying the above-described conditions can be formed.

【0022】このような構造であれば、導電体パターン
6aにおける導電体バンプ3の端面4に電気的に接続さ
れる部分22は、導電体バンプ3の端面4を臨む範囲内
だけに位置していることになる。このため、絶縁材層2
の構成材料と導電体バンプ3の構成材料との厚み方向の
線膨張率が異なっていても、この違いに起因して導電体
バンプ3の端面4と部分22との界面21に大きな熱応
力が生じるようなことはない。すなわち、高温雰囲気に
おかれても部分22には、この部分22を端面4から引
き剥がすような大きな熱応力は作用しない。したがっ
て、はんだリフロー処理後の機械的、電気的な信頼性を
確保することができる。
With such a structure, the portion 22 of the conductor pattern 6a that is electrically connected to the end face 4 of the conductor bump 3 is located only within a range facing the end face 4 of the conductor bump 3. Will be. Therefore, the insulating material layer 2
Even if the constituent material of the conductive bump 3 and the constituent material of the conductor bump 3 have different linear expansion coefficients in the thickness direction, a large thermal stress is generated at the interface 21 between the end face 4 and the portion 22 of the conductor bump 3 due to this difference. Nothing happens. That is, even in a high-temperature atmosphere, a large thermal stress does not act on the portion 22 to peel the portion 22 from the end face 4. Therefore, mechanical and electrical reliability after the solder reflow process can be ensured.

【0023】図2(a) には本発明の別の実施形態に係る
4層構成の印刷配線基板1bの概略構成が示されてい
る。なお、この図では図1と同一機能部分が同一符号で
示されている。この印刷配線基板1bも図5で説明した
方法で形成されている。
FIG. 2A shows a schematic structure of a printed wiring board 1b having a four-layer structure according to another embodiment of the present invention. In this figure, the same functional parts as those in FIG. 1 are indicated by the same reference numerals. This printed wiring board 1b is also formed by the method described with reference to FIG.

【0024】この例に係る印刷配線基板1bが図1に示
される印刷配線基板1aと異なる点は、絶縁材層2の表
面に密着配置されて導電体バンプ3の端面4に電気的に
接続される部分23を持つ導電体パターン6bの構造に
ある。具体的には、部分23の大きさおよび位置にあ
る。
The printed wiring board 1b according to this embodiment is different from the printed wiring board 1a shown in FIG. 1 in that the printed wiring board 1b is closely attached to the surface of the insulating material layer 2 and is electrically connected to the end face 4 of the conductor bump 3. In the structure of the conductor pattern 6b having the portion 23 which is formed. Specifically, it is at the size and position of the portion 23.

【0025】すなわち、部分23は、端面4の大きさ以
下の大きさで、端面4を臨む範囲内に位置している。そ
して、部分23のうちで印刷配線基板1b内に位置して
いるものは、図2(b) にも示すように、導電体バンプ3
の端面部分に一部または全部が埋め込まれる関係に設け
られている。
That is, the portion 23 is smaller than the size of the end face 4 and is located within a range facing the end face 4. Then, of the portions 23, those located in the printed wiring board 1b are, as shown in FIG.
Are provided so as to be partially or wholly embedded in the end face portion.

【0026】このような構造であれば、導電体パターン
6bにおける導電体バンプ3の端面4に電気的に接続さ
れる部分23は、導電体バンプ3の端面4より小さく、
かつ端面4を導電体バンプ3の貫通方向に投影して得ら
れる投影像内に位置していることになる。このため、絶
縁材層2の構成材料と導電体バンプ3の構成材料との厚
み方向の線膨張率が異なっていても、この違いに起因し
て導電体バンプ3の端面4と部分23との界面21に大
きな熱応力が生じるのを抑制できる。したがって、はん
だリフロー処理後の機械的、電気的な信頼性を確保する
ことができる。
With such a structure, a portion 23 of the conductor pattern 6b electrically connected to the end face 4 of the conductor bump 3 is smaller than the end face 4 of the conductor bump 3,
In addition, the end face 4 is located in a projected image obtained by projecting the end face 4 in the penetrating direction of the conductive bump 3. For this reason, even if the linear expansion coefficients in the thickness direction of the constituent material of the insulating material layer 2 and the constituent material of the conductor bump 3 are different, the difference between the end face 4 of the conductor bump 3 and the portion 23 is caused by this difference. The generation of a large thermal stress at the interface 21 can be suppressed. Therefore, mechanical and electrical reliability after the solder reflow process can be ensured.

【0027】なお、導電体バンプ3は、たとえば銀、
金、銅、はんだ粉などの導電性粉末、これらの合金粉末
もしくは複合(混合)金属粉末と、たとえばポリカーボ
ネート樹脂、ポリスルホン樹脂、ポリエステル樹脂、フ
ェノキシ樹脂、フェノ一ル樹脂、ポリイミド樹脂などの
バインダー成分とを混合して調製された導電性組成物、
あるいは導電性金属などで構成することができる。ま
た、導電体バンプ3の形成は、導電性組成物で形成する
場合は、たとえば比較的厚いメタルマスクを用いた印刷
法により、アスペクト比の高いバンプを形成でき、その
バンプの高さは一般的に100 μm〜400 μm程度が望ま
しい。また、絶縁材層2を形成する材料としては、エポ
キシ樹脂、ビスマレイミドトリアジン樹脂、ポリイミド
樹脂、フェノール樹脂、ポリエステル樹脂、メラミン樹
脂、あるいはブタジェンゴム、ブチルゴム、天然ゴム、
ネオプレンゴム、ンリコーンゴムなどの生ゴムのシート
類を挙げることができる。これらの合成樹脂は、単独て
もよいが絶縁性無機物や有機物系の充填物を含有しても
よく、さらにガラスクロスやマット、有機合成繊維布や
マット、あるいは紙などの補強材と組合せてなるシート
であってもよい。また、導電体パターン6a,6bを形
成する材料としては、電解銅箔を用いる場合が多い。ま
た、図1、2には4層の印刷配線基板が例示されている
が、本発明は両面板や4層以外の多層板においても有効
である。
The conductor bump 3 is made of, for example, silver,
Conductive powders such as gold, copper, solder powders, alloy powders or composite (mixed) metal powders thereof, and binder components such as polycarbonate resin, polysulfone resin, polyester resin, phenoxy resin, phenol resin, and polyimide resin. A conductive composition prepared by mixing
Alternatively, it can be made of a conductive metal or the like. When the conductive bump 3 is formed of a conductive composition, a bump having a high aspect ratio can be formed by, for example, a printing method using a relatively thick metal mask, and the bump has a general height. About 100 μm to 400 μm is desirable. The material for forming the insulating material layer 2 includes epoxy resin, bismaleimide triazine resin, polyimide resin, phenol resin, polyester resin, melamine resin, butadiene rubber, butyl rubber, natural rubber,
Examples include sheets of raw rubber such as neoprene rubber and silicone rubber. These synthetic resins may be used alone or may contain an insulating inorganic or organic filler, and are further combined with a reinforcing material such as glass cloth or mat, organic synthetic fiber cloth or mat, or paper. It may be a sheet. In addition, as a material for forming the conductor patterns 6a and 6b, an electrolytic copper foil is often used. Although FIGS. 1 and 2 illustrate a four-layer printed wiring board, the present invention is also effective for a double-sided board or a multilayer board other than the four-layer board.

【0028】[0028]

【発明の効果】以上説明したように、本発明によれば、
絶縁材層、導電体バンプおよび導電体パターンを構成し
ている材料の線膨張率がそれぞれ異なる場合であって
も、この異なりに起因して導電体バンプの端面と導電体
パターンの上記端面に電気的に接続される部分との界面
に発生し易い熱応力を低減させることができ、もって機
械的、電気的な接続の信頼性を確保することができる。
As described above, according to the present invention,
Even if the materials constituting the insulating material layer, the conductive bumps, and the conductive pattern have different linear expansion coefficients, due to this difference, the end face of the conductive bump and the end face of the conductive pattern are electrically connected. Thermal stress easily generated at the interface with the part to be electrically connected can be reduced, so that the reliability of mechanical and electrical connection can be ensured.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施形態に係る印刷配線基板の概略
断面図
FIG. 1 is a schematic sectional view of a printed wiring board according to an embodiment of the present invention.

【図2】(a) 本発明の別の実施形態に係る印刷配線基板
の概略断面図で、(b) は(a) におけるB部を取出して拡
大して示す斜視図
2A is a schematic cross-sectional view of a printed wiring board according to another embodiment of the present invention, and FIG. 2B is an enlarged perspective view showing a portion B in FIG.

【図3】従来の印刷配線基板の概略断面図FIG. 3 is a schematic sectional view of a conventional printed wiring board.

【図4】図3におけるA−A線沿って切断し矢印方向に
見た図
FIG. 4 is a view taken along the line AA in FIG. 3 and viewed in the direction of the arrow.

【図5】図3に示す印刷配線基板の製造方法の一例を説
明するための図
FIG. 5 is a view for explaining an example of a method of manufacturing the printed wiring board shown in FIG.

【符号の説明】[Explanation of symbols]

1a,1b…印刷配線基板 2…絶縁材層 3…導電体バンプ 4…端面 5a,6b…導電体パターン 21…界面 22,23…端面に電気的に接続される部分 1a, 1b ... printed wiring board 2 ... insulating material layer 3 ... conductor bump 4 ... end face 5a, 6b ... conductor pattern 21 ... interface 22, 23 ... part electrically connected to the end face

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】絶縁材層と、この絶縁材層を貫通して配線
路を形成する導電体バンプと、前記絶縁材層の表面に密
着配置されて前記導電体バンプの端面に電気的に接続さ
れる部分を持つ導電体パターンとを備えてなる印刷配線
基板において、 前記導電体パターンの前記導電体バンプに電気的に接続
される部分は、前記端面の大きさ以下の大きさで、かつ
上記端面を上記導電体バンプの貫通方向に投影して得ら
れる投影像内に位置していることを特徴とする印刷配線
基板。
1. An insulating material layer, a conductive bump penetrating the insulating material layer to form a wiring path, and electrically connected to an end face of the conductive bump disposed closely on a surface of the insulating material layer. A conductive pattern having a portion to be electrically connected to the conductive bumps of the conductive pattern, the portion having a size equal to or less than the size of the end face, and A printed wiring board, wherein the printed wiring board is located in a projected image obtained by projecting an end face in a direction in which the conductor bump penetrates.
【請求項2】前記導電体パターンの前記導電体バンプに
電気的に接続される部分のうちの幾つかの部分は、一部
または全部が上記導電体バンプの前記端面部分に埋め込
まれていることを特徴とする請求項1に記載の印刷配線
基板。
2. Some or all of the portions of the conductor pattern that are electrically connected to the conductor bumps are partially or entirely embedded in the end surface portions of the conductor bumps. The printed wiring board according to claim 1, wherein:
JP24636496A 1996-09-18 1996-09-18 Printed wiring board Expired - Fee Related JP3633136B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24636496A JP3633136B2 (en) 1996-09-18 1996-09-18 Printed wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24636496A JP3633136B2 (en) 1996-09-18 1996-09-18 Printed wiring board

Publications (2)

Publication Number Publication Date
JPH1093242A true JPH1093242A (en) 1998-04-10
JP3633136B2 JP3633136B2 (en) 2005-03-30

Family

ID=17147462

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24636496A Expired - Fee Related JP3633136B2 (en) 1996-09-18 1996-09-18 Printed wiring board

Country Status (1)

Country Link
JP (1) JP3633136B2 (en)

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2712167A1 (en) * 1993-11-10 1995-05-19 Seb Sa Flow control sensor for vacuum cleaner.
JP2002176237A (en) * 2000-12-06 2002-06-21 Ibiden Co Ltd Printed wiring board
JP2002305376A (en) * 2001-04-05 2002-10-18 Dt Circuit Technology Co Ltd Printed wiring board, manufacturing method thereof, and semiconductor device
WO2006059428A1 (en) * 2004-12-03 2006-06-08 Sony Chemical & Information Device Corporation Process for producing multilayer wiring board
JP2008131036A (en) * 2006-11-21 2008-06-05 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
JP2008311612A (en) * 2007-06-13 2008-12-25 Samsung Electro Mech Co Ltd Multilayer printed circuit board, and method of manufacturing the same
JP2009088461A (en) * 2007-09-28 2009-04-23 Samsung Electro-Mechanics Co Ltd Method for manufacturing printed circuit board
JP2009141305A (en) * 2007-12-03 2009-06-25 Samsung Electro Mech Co Ltd Printed circuit board and method of manufacturing the same
JP2009239185A (en) * 2008-03-28 2009-10-15 Toppan Printing Co Ltd Build-up multilayer wiring board and manufacturing method therefor
JP2009290020A (en) * 2008-05-29 2009-12-10 Toshiba Corp Flexible printed wiring board, shielding method of wiring board and electronics
WO2010125858A1 (en) * 2009-04-29 2010-11-04 株式会社 村田製作所 Multilayered resin circuit board, and manufacturing method of multilayered resin circuit board
JPWO2012108381A1 (en) * 2011-02-08 2014-07-03 株式会社村田製作所 Resin multilayer substrate and manufacturing method thereof
JP2014132603A (en) * 2012-11-14 2014-07-17 Fujikura Ltd Multilayer wiring board
CN112165767A (en) * 2020-10-27 2021-01-01 惠州市特创电子科技有限公司 Multilayer circuit board and mobile communication device

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2712167A1 (en) * 1993-11-10 1995-05-19 Seb Sa Flow control sensor for vacuum cleaner.
JP2002176237A (en) * 2000-12-06 2002-06-21 Ibiden Co Ltd Printed wiring board
JP4684454B2 (en) * 2001-04-05 2011-05-18 大日本印刷株式会社 Printed wiring board manufacturing method and printed wiring board
JP2002305376A (en) * 2001-04-05 2002-10-18 Dt Circuit Technology Co Ltd Printed wiring board, manufacturing method thereof, and semiconductor device
WO2006059428A1 (en) * 2004-12-03 2006-06-08 Sony Chemical & Information Device Corporation Process for producing multilayer wiring board
US8112881B2 (en) 2004-12-03 2012-02-14 Tessera Interconnect Materials, Inc. Method for manufacturing multilayer wiring board
JP2008131036A (en) * 2006-11-21 2008-06-05 Samsung Electro-Mechanics Co Ltd Printed circuit board and method of manufacturing the same
US8058558B2 (en) 2006-11-21 2011-11-15 Samsung Electro-Mechanics Co., Ltd. Printed circuit board and manufacturing method thereof
JP2008311612A (en) * 2007-06-13 2008-12-25 Samsung Electro Mech Co Ltd Multilayer printed circuit board, and method of manufacturing the same
JP4614367B2 (en) * 2007-09-28 2011-01-19 サムソン エレクトロ−メカニックス カンパニーリミテッド. Printed circuit board manufacturing method
JP2009088461A (en) * 2007-09-28 2009-04-23 Samsung Electro-Mechanics Co Ltd Method for manufacturing printed circuit board
JP2009141305A (en) * 2007-12-03 2009-06-25 Samsung Electro Mech Co Ltd Printed circuit board and method of manufacturing the same
JP2009239185A (en) * 2008-03-28 2009-10-15 Toppan Printing Co Ltd Build-up multilayer wiring board and manufacturing method therefor
JP2009290020A (en) * 2008-05-29 2009-12-10 Toshiba Corp Flexible printed wiring board, shielding method of wiring board and electronics
WO2010125858A1 (en) * 2009-04-29 2010-11-04 株式会社 村田製作所 Multilayered resin circuit board, and manufacturing method of multilayered resin circuit board
JPWO2012108381A1 (en) * 2011-02-08 2014-07-03 株式会社村田製作所 Resin multilayer substrate and manufacturing method thereof
JP5652481B2 (en) * 2011-02-08 2015-01-14 株式会社村田製作所 Resin multilayer substrate and manufacturing method thereof
JP2014132603A (en) * 2012-11-14 2014-07-17 Fujikura Ltd Multilayer wiring board
CN112165767A (en) * 2020-10-27 2021-01-01 惠州市特创电子科技有限公司 Multilayer circuit board and mobile communication device

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