JPH1092180A - Semiconductor memory device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a semiconductor memory device which enables the reduction of a power consumption. SOLUTION: A memory cell array 21a is divided into a plurality of blocks BLK0a-BLK3a. Word lines are classified into a global word line through which driving signals are propagated in accordance with address designation and local word lines LWL00, LWL10, LWL20 and LWL30 which are provided in the respective memory blocks and to which memory cells in same columns are connected in common. Block selection circuits 22a-1 and 22a-2 which connect selectively only the local word lines LWL00, LWL10, LWL20 and LWL30 to which the memory cells whose addresses are designated are connected to the global word line through which the driving signals are propagated are provided. With this constitution, the number of the memory cells whose addresses are designated and the number of the memory cells whose access transistors are driven are not the number of all the cells in one column of the array but can be reduced to the number of the memory cells provided in the divided block only, so that a power consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention
(Static Random Access Memory) and the like.

[0002]

2. Description of the Related Art FIG. 7 is a block diagram showing a configuration of a general SRAM device. This SRAM device 10 has the structure shown in FIG.
As shown in FIG. 2, the memory cell arrays 11a and 11b, the precharge circuits 12a and 12b, the column gate groups 13a,
13b, read / write circuit (R / W) groups 14a, 14b,
And a row decoder 15.

The memory cell arrays 11a and 11b are arranged in parallel with a row decoder 15 interposed therebetween, and each memory cell MC is arranged in a matrix of m rows and 64 columns. Then, each of the memory cell arrays 11a, 11b
Are 16 memory cell blocks BLK0a to BLK15a, BLK0 with four cells as one block in the column direction.
b to BLK15b.

Each memory cell MC has, as shown in FIG.
A latch circuit LTC is formed by cross-connecting the inputs and outputs of the inverters INV1 and IN2, and two storage nodes ND1 and ND2 of the latch circuit LTC are connected to the bit line BL and the anti-bit line BLB. It comprises access transistors AT1 and AT2 commonly connected to WL.

The memory cells M arranged in the same row
The gates of the C access transistors AT1 and AT2 are connected to the same word line to which a drive signal is selectively applied and driven by the row decoder 15, and the two storage nodes ND1 and ND2 of the memory cells MC arranged in the same column. Are operatively connected to a pair of bit lines BL and BLB by access transistors AT1 and AT2.

The precharge circuits 12a, 12b
Precharges a pair of bit lines BL and BLB to a predetermined potential, for example, power supply voltage V _DD before starting access.

The column gate groups 13a and 13b and the read / write circuit groups 15a and 15b correspond to each memory cell block BL.
It is formed in accordance with the arrangement width of K0a to BLK15a and BLK0b to BLK15b, and is provided corresponding to each block.

In such a configuration, for example, memory cell MC in the first row and first column of memory cell array 11a (see FIG. 7)
When data is read by addressing (indicated by *), first, all bit line pairs BL and BLB on the memory cell array 11a side are precharged to the power supply voltage _VDD level by the precharge circuit 12a.

In this precharge state, the addressed word line WL0 is selected, and a high-level drive signal is applied to the word line WL from the row decoder 15. At this time, the other word lines are kept at the low level.

When a high-level drive signal is applied to word line WL0, two access transistors AT1 and AT2 of 64 memory cells MC arranged in the first row of memory cell array 11a are turned on. Is held. As a result, data of two storage nodes ND1 and ND2 having complementary levels of each memory cell are output to bit line pair BL and BLB. Thereby, the bit line BL
A potential difference occurs between B and BLB. Then, based on the address designation, only the column gate to which the bit line pair to which the memory cell MC * is connected is held in the conductive state, and the read data to these bit line pairs BL and BLB is read / written by the read / write circuit. The data is input to and read from a sense amplifier (not shown) of the corresponding circuit of the group 14a.

[0011]

However, in the above-described circuit, even when one memory cell is selected and data is read, the remaining 63 cells arranged in the same row as the selected memory cell MC * are used. Memory cells are commonly connected to the same word line WL0.
Two access transistors AT of four memory cells
1, AT2, that is, all of the 128 access transistors are kept conductive, and each storage node ND1,
ND2 data is output to 64 bit line pairs BL and BLB, charging and discharging are performed based on the stored data, and there is a disadvantage that wasteful power consumption is performed. In particular, power consumption is large due to the discharge of the bit line pair precharged to the power supply voltage V _DD level. This disadvantage is even more serious in the case of the so-called dual access mode.

The present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption.

[0013]

In order to achieve the above object, the present invention provides a memory system comprising a plurality of memory cells arranged in a matrix,
A semiconductor memory device in which memory cells arranged in the same row are driven by the same drive signal and transmit and receive data between the driven memory cells and bit lines, wherein the plurality of memory cells are arranged in a column direction. And a global word line through which the drive signal is propagated based on the address specification, and a memory cell block provided for each memory cell block, and the memory cells in the same row of the memory cell block are commonly shared. A connected local word line, and a selection circuit for selectively connecting only the local word line of the predetermined memory cell block to which the addressed memory cell is connected to the global word line to which the drive signal has been transmitted. .

Further, the present invention has a precharge means for precharging only the bit line connected to the addressed memory cell to a predetermined potential before transmitting the drive signal to the global word line. Alternatively, before propagating the drive signal to the global word line, a precharge means for precharging a plurality of bit lines connected to the memory cells of the memory cell block in which the addressed memory cell exists to a predetermined potential is provided. Have.

Further, the semiconductor memory device of the present invention corresponds to a column decoder for selecting a bit line to which a addressed memory cell is connected, and to the number of memory cells arranged on the same row in a memory cell block. A plurality of read / write circuits provided corresponding to the memory cells, a bit line output of each memory cell corresponding to each memory cell of each memory cell block, wired between the column decoder and the read / write circuit. To a common read / write circuit.

Further, in the semiconductor memory device of the present invention, a shield line is provided between the adjacent local bus lines.

According to the semiconductor memory device of the present invention, when selecting and accessing a memory cell, a drive signal is propagated to a selected global word line based on an address designation. Then, in the selection circuit, only the local word line of the predetermined memory cell block to which the addressed memory cell is connected is selectively connected to the global word line to which the drive signal has been transmitted. Thereby, the drive signal propagated to the global word line is transmitted only to the local word line of the predetermined memory cell block, and only the storage nodes of a plurality of memory cells arranged on the same row of the memory cell block are connected to the bit line. And data is exchanged.

[0018]

FIG. 1 is a block diagram showing an embodiment of an SRAM device according to the present invention. FIG. 2 is a circuit diagram showing a main portion of the SRAM device shown in FIG. Decoder (block decoder), local bus line, read /
FIG. 3 is a main part circuit diagram of a writing circuit.

This SRAM device 20 includes memory cell arrays 21a and 21b, block selection circuits 22a-1 and 22a.
a-2, 22b-1, 22b-2, precharge circuit 2
3a, 23b, column gate groups 24a, 24b, local bus line groups 25a, 25b, read / write circuit (R / W)
It is composed of groups 26a and 26b, a row decoder 27 and a block decoder 28.

The memory cell arrays 21a and 21b are arranged in parallel with the row decoder 27 interposed therebetween, and each memory cell MC is arranged in a matrix of m rows and 64 columns. Then, each of the memory cell arrays 21a, 21b
Represents four memory cell blocks BLK0a to BLK3a and BLK0b each having 16 cells as one block in the column direction.
~ BLK3b. Here, each memory cell array is divided into four memory cell blocks each having 16 cells. However, the present invention is not limited to such a divided form, and each memory cell array is divided into two memory cell blocks each having 32 cells. , Or each memory cell array may be divided into eight memory cell blocks of eight cells.

Each memory cell MC is, similarly to the memory cell shown in FIG. 8, a latch circuit LTC having cross-coupled inputs and outputs of inverters INV1 and IN2, and two storage nodes ND1 and ND2 of the latch circuit LTC. And bit line B
L and an anti-bit line BLB, and the gate is constituted by access transistors AT1 and AT2 commonly connected to the local word line LWL.

The local word line LWL is wired for each row of the memory cell block, and is connected to one local word line LWL.
Sixteen memory cells MC are connected to WL. Therefore, one local word line LWL00, LWL1
The gates of 32 access transistors AT are connected to 0 and. Then, the memory cell array 21a,
In the entire 21b, global word lines GWL0,... To which a drive signal is applied by addressing by the row decoder 27 are wired corresponding to each row.

The global word line GWL is connected to the block selection circuits 22a-1, 22a-2, 22b-1, 22b-
2, the local word line LW of a predetermined memory cell block to which the addressed memory cell is connected.
L is selectively connected.

The block selection circuit 22a-1 is connected to the memory cell blocks BLK0a and BLK0 of the memory cell array 21a.
And K1a. And FIG.
As shown in FIG. 7, a plurality of local word lines LWL00, LWL01,
LWL02,... Are changed to global word lines GWL in the corresponding rows in response to the input of block selection signal SB0.
0, GWL1, GWL2,... And select circuits SL00, SL01, SL02,... And a plurality of local word lines LWL10, LWL11, LWL12,. Global word lines GWL0, GWL1, GWL of the corresponding rows in response to the input of signal SB1.
Selection circuits SL10, S selectively connected to
L11, SL12,... Are arranged in parallel.

The block selection circuit 22a-2 is connected to the memory cell blocks BLK2a and BLK2 of the memory cell array 21a.
And K3a. And FIG.
As shown in FIG. 7, a plurality of local word lines LWL20, LWL21,
LWL22,... Are set to global word lines GWL of the corresponding row in response to the input of block selection signal SB2.
0, GWL1, GWL2,... And select circuits SL20, SL21, SL22,... And a plurality of local word lines LWL30, LWL31, LWL32,. The global word lines GWL0, GWL1, and GWL in the corresponding rows respectively correspond to the input of the signal SB3.
Selection circuits SL30, S selectively connected to
L31, SL32, ... are arranged in parallel.

Similarly, block selection circuits 22b-1, 22b-1,
2b-2 is also arranged and has the same configuration as the above-described 22a-1 and 22a-2, and a detailed description thereof is omitted here.

Then, each of the block selection circuits 22a-1, 22a-1
Each selection circuit SL provided in 22a-2, 22b-1, and 22b-2 has a configuration as shown in FIG.

That is, the selection circuit SL has a p-channel M
OS (PMOS) transistor PT21, n-channel M
It comprises an OS (NMOS) transistor NT21 and an inverter INV21. A PMOS transistor PT21 and an NMOS transistor NT21 are connected in series between the supply line of the power supply voltage V _DD and the supply line SBL of the block selection signal, and both transistors P21
The gate of T21 and NT21 is the global word line GWL
It is connected to the. Then, the PMOS transistor PT
21 and the NMOS transistor NT21 are connected to the input terminal of the inverter INV21.
The output terminal of the NV 21 is connected to the local word line LWL. Further, between the supply line of the power supply voltage V _DD and the input terminal of the inverter INV21, a gate may be connected to the output terminal of the inverter INV21 and a PMOS transistor PT22 may be added.

In the selection circuit SL having such a configuration, when no drive signal is applied to the global word line GWL and the global word line GWL is held at a low level, the PMOS transistor PT21 is turned on. The NMOS transistor NT21 is maintained in a non-conductive state. As a result, the inverter INV2
1 is supplied with the power supply voltage V _DD , and the local word line LWL is kept at a low level, that is, in a non-drive state. On the other hand, when a drive signal is applied to global word line GWL and global word line GWL is held at a high level, PMOS transistor PT21 is held in a non-conductive state and NMOS transistor NT21 is held in a conductive state. At this time, an active block selection signal SB at the ground level (low level) is supplied to the block selection signal line SBL. As a result, the input side of the inverter INV21 is held at the ground level, and the local word line LWL is held at the high level, that is, in the driving state. When the logic of the global word line GWL and the block selection signal line is activated at a high level, the input terminal of the selection circuit SL is connected to the global word line GWL and the block selection signal line, respectively.
The output terminal may be constituted by a two-input AND gate connected to the local word line LWL.

The precharge circuits 23a correspond to the four memory cell blocks BLK0a to BLK3a, and correspond to four block precharge circuits 23a-0, 23a-1,.
23a-2 and 23a-3, each of which is individually driven.

The block precharge circuits 23a-0, 23a-0,
23a-1,23a-2,23a-3, as shown in FIG. 2, connected PMOS transistor between the supply lines of each bit line BL, BLB and the power supply voltage V _DD PT23
-0 to PT23-31, and two-input NAND gates NA0 to NA3 whose output terminals are commonly connected to the gates of the PMOS transistors PT23-0 to PT23-31.

One input terminal of each of the two-input NAND gates NA0 to NA3 is connected to an input line for a high-level active precharge signal SPr. The other input terminal of the NAND gate NA0 of the block precharge circuit 23a-0 is connected to the block selection signal line SBL0 via the inverter INV30. The other input terminal of the NAND gate NA1 of the block precharge circuit 23a-1 is connected to the block selection signal line SBL1 via the inverter INV31. The other input terminal of the NAND gate NA2 of the block precharge circuit 23a-2 is connected to the block selection signal line SBL2 via the inverter INV32. The other input terminal of the NAND gate NA3 of the block precharge circuit 23a-3 is connected to the block selection signal line S via the inverter INV33.
Connected to BL3.

In the precharge circuit 23a having such a configuration, of the block select signals SBO to SB3, only the block precharge circuit connected to the block select signal line input at the active low level is the bit line. The precharge operation is performed, and the bit line precharge operation is not performed on the remaining three blocks.
In the example described above, the transistors for precharging the bit line pairs BL and BLB are constituted by PMOS transistors, but may be constituted by NMOS transistors. In this case, it is necessary to change the gate for driving the precharge NMOS transistor from the NAND gate to the AND gate.

Similarly, the precharge circuit 23b has the same configuration as the above-described precharge circuit 23a, and a detailed description thereof will be omitted.

As shown in FIG. 3, the column gate group 24a is connected to the block decoder 28, and has four control line pairs B0, B0B, B1, B1B, B2 which take a level according to the decoding result of the block decoder 28. , B2B, B
3, B3B are wired. Control line pair B0, B0B
Is for controlling the bit line output in the memory cell block BLK0a, and operates the 16 bit line pairs of the memory cell block BLK0a and the local bus line group 25a according to the level of the control line pair B0, B0B. Are switched between the conduction states of the 16 transfer gate groups TMG0 that are connected to. The control line pairs B1 and B1B are for controlling the bit line output in the memory cell block BLK1a. According to the levels of the control line pairs B1 and B1B, the 16 bit line pairs of the memory cell block BLK1a and the local bus lines are provided. The conduction state of the 16 transfer gate groups TMG1 operatively connected to the group 25a is switched. Control line pair B
2 and B2B are for controlling the bit line output in the memory cell block BLK2a, and include a control line pair B2 and B2B.
According to the level of 2B, the conduction state of 16 transfer gate groups TMG2 which operatively connects the 16 bit line pairs of the memory cell block BLK2a to the local bus line group 25a is switched. The control line pairs B3 and B3B are for controlling the bit line output in the memory cell block BLK3a, and according to the levels of the control line pairs B3 and B3B, the 16 bit line pairs of the memory cell block BLK3a and the local bus lines are provided. The conduction state of the 16 transfer gate groups TMG3 operatively connected to the group 25a is switched.

The control lines B0B, B1B, B2B,
B3B respectively branch to form a block selection signal line SBL.
0, SBL1, SBL2, and SBL3 are wired to the block selection circuits 22a-1 and 22a-2.

Transfer gate groups TMG0 to TMG3 are formed, for example, as shown in FIG.
Transfer gates TM0, TM0B,..., TM15, which connect the source and the drain of the MOS transistor NT.
A bit line pair BL, BLB is connected to TM15B. Then, each transfer gate TM0, TM0B,
, TM15, and TM15B have their gates connected to the control line B0 (.about.3) B, and their NMOS transistors NT have their gates connected to the control line B0 (.about.3).

Similarly, the column gate group 24b has the same configuration as the above-described column gate group 24a, and a detailed description thereof will be omitted.

The block decoder 28 comprises two-input NAND gates NA280 to NA283 for an address decoder,
And inverters INV280 to INV283. Output terminal of NAND gate NA280 is control line B
0B and the inverter INV280
And the output terminal of the inverter INV280 is connected to the control line B0. NAND Gate NA28
1 is connected to the control line B1B, is connected to the input terminal of the inverter INV281, and the output terminal of the inverter INV281 is connected to the control line B1. The output terminal of the NAND gate NA282 is the control line B2B.
And the input terminal of the inverter INV282, and the output terminal of the inverter INV282 is connected to the control line B2. The output terminal of the NAND gate NA283 is connected to the control line B3B, connected to the input terminal of the inverter INV283, and the output terminal of the inverter INV283 is connected to the control line B3.

The local bus group 25a includes 16 local bus line pairs LB0, LB0B,..., LB15, LB15.
B, and shield lines G1 to G15 which are arranged between adjacent pairs of local bus lines and are grounded. The shield lines G1 to G15 are wired to prevent interference between the local bus line pairs LB0, LB0B,..., LB15, LB15B.

The local bus lines LB0 and LB0B are connected to the transfer gates TG0 and TG of each of the transfer gate groups TGM0 to TGM3.
0B, each memory cell block BLK0 is connected in parallel.
a to BLK3a are operatively connected to the bit line pair BL, BLB in the first column, and read / write circuit 26-BLK3a.
0 are connected to a pair of data input / output terminals. Local bus lines LB1 and LB1B are connected to each transfer gate group TGM0.
Through the transfer gates TG1 and TG1B of the memory cell blocks BLK0a to BLK3a, and are operatively connected to the pair of bit lines BL and BLB in the second column of the memory cell blocks BLK0a to BLK3a. It is connected to a pair of data input / output terminals. Hereinafter, similarly, local bus lines LB15 and LB15B are connected to each transfer gate group TGM.
0 through TGM3 transfer gates TG15, TG15B in parallel to each of the memory cell blocks BLK0a-BLK.
It is operatively connected to the bit line pair BL, BLB in the 16th column of 3a, and is also connected to a data input / output terminal forming a pair of the read / write circuits 26-15.

Each of the read / write circuits 26-0 to 26-15
Are read sense amplifiers 261 as shown in FIG.
And write buffers 262 and 263, for example, which are selectively operated. Each of the read / write circuits 26-0 to 26-15 is connected to a 16-bit global bus line GB, and outputs read data and inputs write data.

The row decoder 27 has two-input NAND gates NA270, NA271 and NA271 for an address decoder.
272, ... and inverters INV270, INV271,
INV272, .... NAND gate N
The output terminal of A270 is connected to the input terminal of inverter INV270, and the output terminal of inverter INV270 is connected to global word line GWL0. Similarly, the output terminal of the NAND gate NA271 is connected to the input terminal of the inverter INV271, the output terminal of the inverter INV271 is connected to the global word line GWL1, the output terminal of the NAND gate NA272 is connected to the input terminal of the inverter INV272, The output terminal is connected to the global word line GWL2.

Next, the operation of the above configuration will be described. Here, an example will be described in which data is read out by addressing a memory cell MC (indicated by * in FIG. 1) in the first row and first column of the memory cell array 21a.

First, a NAND gate NA280 is obtained based on the decoding result of the block decoder 28 based on the address designation.
Only the output of becomes low level. As a result, the control line B0 of the column gate group 24a is at a high level and B0B is at a low level, and a low-level active block selection signal is transmitted to the block selection signal line SBL0. This block selection signal is supplied to the block selection circuit 22a.
-1 and input to the NAND gate NA0 of the block precharge circuit 23a-0 at a high level via the inverter INV30.

Then, the precharge signal SPr is supplied to each of the circuits 23a-0 to 23a-3 at a high level for a predetermined period. At this time, another block selection signal line SBL
Since the inactive high-level block selection signal is propagated to 1, SLB2 and SBL3, only the output of the NAND gate NA0 of the precharge circuit 23a-0 goes high, and the other precharge circuits 23a-1
Outputs of the NAND gates NA1 to NA3 of 〜23a-3 are kept at a low level.

As a result, only the transistor PT of the precharge circuit 23a-0 is kept conductive, so that
Only the 16 bit line pairs BL and BLB wired to the memory cell block BLK0a are precharged to the power supply voltage _VDD level. At this time, the precharge operation is not performed on the 48 bit line pairs wired to the remaining memory cell blocks BLK1a to BLK3a.

Next, the precharge signal SPr is switched to a low level, and the transistor PT of the precharge circuit 23a-0 is switched to a non-conductive state. In this precharge state, only the output of the NAND gate NA270 goes low according to the decoding result of the row decoder 27 based on the address designation. As a result, only the output of the driving inverter INV270 becomes high level, that is,
A drive signal is propagated to a high level only to global word line GWL0.

With the transmission of the drive signal to global word line GWL0, block selection circuits 22a-1, 22a-1
Selection circuits SL00, SL10, S in the first row of 22a-2
Although the NMOS transistors NT21 of L20 and SL30 are switched to the conductive state, since only the block selection signal SB0 is at the active low level, the local word line LWL0 in the first row of the memory cell block BLK0a is switched.
A high level signal is propagated as a drive signal only to 0. Other block selection signals SB1, SB2, SB3
Is inactive high level, the local word lines LWL10, LWL20, LWL30 of the memory cell blocks BLK1a, BLK2a, BLK3a are kept at low level.

As a result, memory cell block BLK0a
Of the 16 memory cells MC arranged in the first row of FIG.
The access transistors AT1 and AT2 are kept conductive. As a result, data of two storage nodes ND1 and ND2 having complementary levels of each memory cell are output to bit line pair BL and BLB. As a result, a potential difference occurs between the bit lines BLB, BLB. At this time, since the control line B0 is at the high level and the control line B0B is at the low level in the transfer gates of the transfer gate group TMG0, each transfer gate is held in a conductive state, and the bit line pair BL, BLB is connected. When the data is on the local buses LB0, LB
Read / write circuit 26, which is controlled to an operating state via OB
The signal is input to −0, amplified by the sense amplifier 260, and output to the global bus line GB.

As described above, according to the present embodiment, the memory cell arrays 21a and 21b are divided into a plurality of blocks BLK0a to BLK3a and BLK0b to blk3b, and the drive signal is propagated based on the address designation of the word lines. Global word line GWL and a local word line LWL provided for each memory cell block and connected in common to the memory cells in the same row of the memory cell block, and the addressed memory cells are connected. Block selecting circuit 22a for selectively connecting only the local word line LWL of a given memory cell block to the global word line GWL to which the drive signal has been transmitted.
Since -1, 22a-2, 22b-1, and 22b-2 are provided, the number of memory cells whose access transistors are driven at the same time as the memory cell for addressing is arranged in a divided block instead of the entire row of the array. Memory cells can be reduced, and power consumption can be reduced.

Further, before propagating the drive signal to the global word line, a precharge for precharging a plurality of bit lines connected to the memory cells of the memory cell block in which the addressed memory cell exists to a predetermined potential. Since the circuits 23a and 23b are provided, the number of bit lines that fully swing from the power supply voltage V _DD level to the ground level at the time of reading can be reduced, so that power consumption can be further reduced. Further, since the shield lines G1 to G15 are arranged between the adjacent local bus lines, interference between data can be prevented.

It is needless to say that the number of divided blocks and the like are not limited to the present embodiment, and various modes such as providing a block selection circuit according to the number of blocks are possible.

[0054]

As described above, according to the semiconductor memory device of the present invention, the number of memory cells whose access transistors are driven at the same time as the memory cell for addressing is divided into divided blocks instead of the entire row of the array. It can be reduced to only the arranged memory cells, and the power consumption can be greatly reduced. In addition, since the precharge operation can be selectively performed, the number of bit lines whose level changes can be reduced, and the power consumption can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of an SRAM according to the present invention.

FIG. 2 is a main part circuit diagram mainly showing a memory array part of FIG. 1;

FIG. 3 shows a column decoder (block decoder) shown in FIG. 1;
FIG. 3 is a main part circuit diagram of a local bus line and a read / write circuit.

FIG. 4 is a circuit diagram showing a specific configuration example of a selection circuit in a block selection circuit according to the present invention.

FIG. 5 is a circuit diagram showing a configuration example of a column gate group.

FIG. 6 is a circuit diagram showing a configuration example of a read / write circuit.

FIG. 7 is a block diagram illustrating a configuration example of a conventional SRAM device.

FIG. 8 is a circuit diagram showing a configuration example of an SRAM cell.

[Explanation of symbols]

Reference Signs List 20 SRAM device 21a, 21b Memory cell array 22a-1, 22a-2, 22b-1, 22b-2 Block selection circuit 23a, 23b Precharge circuit 24a, 24b Column gate group 25a, 25b Local bus line Groups 26a, 26b read / write circuit (R / W) group 27 row decoder 28 block decoder BLK0a to BLK3a, BLK0b to BLK3b memory cell block

Claims (5)

[Claims] A plurality of memory cells arranged in a matrix;
A semiconductor memory device in which memory cells arranged in the same row are driven by the same drive signal to transfer data between the driven memory cells and bit lines, wherein the plurality of memory cells are arranged in a column direction. And a global word line through which the drive signal is propagated based on the address designation, and a memory cell block provided for each memory cell block, and the memory cells in the same row of the memory cell block are commonly used. A connected local word line, and a selection circuit for selectively connecting only the local word line of the predetermined memory cell block to which the addressed memory cell is connected to the global word line to which the drive signal has been propagated. Semiconductor storage device. 2. A semiconductor device according to claim 1, further comprising a precharge means for precharging only a bit line connected to the addressed memory cell to a predetermined potential before transmitting a drive signal to said global word line. Storage device. 3. A precharge circuit for precharging a plurality of bit lines connected to memory cells of a memory cell block in which addressed memory cells exist to a predetermined potential before transmitting a drive signal to the global word line. 2. The semiconductor memory device according to claim 1, further comprising a charging unit. 4. A column decoder for selecting a bit line to which a addressed memory cell is connected, and a column decoder corresponding to the number of memory cells arranged on the same row in a memory cell block and provided corresponding to each memory cell. A plurality of read / write circuits, and a bit line output of each memory cell of each memory cell block which is wired between the column decoder and the read / write circuit. 4. The semiconductor memory device according to claim 1, further comprising: a plurality of local bus lines for inputting data to said plurality of local bus lines. 5. The semiconductor memory device according to claim 4, wherein a shield line is provided between adjacent local bus lines.