JPH1064267A - Dram - Google Patents

Abstract

PROBLEM TO BE SOLVED: To decrease the consumption of a current at a sense amplifier, by equalizing a first sense amplifier array not immediately after the first sense amplifier array operates, but after a sense amplifier bias is transmitted to a second sense amplifier array. SOLUTION: The DRAM has two, a first and a second sense amplifier arrays. The sense amplifier arrays have memory cell arrays 1, 21 consisting of many memory cells 5, 25, respectively. Sense amplifiers 6, 26 are driven by a pull-up/ pull-down bias potential signal from sense amplifier drivers 9, 29. First, after the first sense amplifier array operates, the first sense amplifier array is not immediately equalized by an equalization circuit part MN1, but held. When the second sense amplifier array operates, transmission circuit parts MP1, MN7 operate thereby to drive the second sense amplifier 26. Thereafter, the first array is equalized by an equalization circuit part MN4. Accordingly, the consumption of a current at the sense amplifiers is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a DRAM (Dynamic Random Access Memory) which is a semiconductor memory device.
In particular, the present invention relates to a dram for reducing power consumption in a continuous sensing operation. The present invention can be applied to all semiconductor memory devices, and can be particularly applied to a DRAM having one transistor and one capacitor cell. Further, the present invention can reduce power consumption even in the self refresh operation of the DRAM.

[0002]

2. Description of the Related Art Generally, a cell array block for storing data of a DRAM device.
Has a structure in which a plurality of cells each including one NMOS transistor and a capacitor are connected to a word line and a bit line connected in a net shape. The operation of the row decoder for selecting one of the word lines of the cell array block is to select a word line corresponding to a row address input from a plurality of word lines. Let us briefly consider the operation of (DRAM) elements.

[0003] First, a RAS (/ RAS) signal which is a main signal for operating the DRAM element is activated (low (lo) signal).
w)) while accepting the address signal input to the row address buffer.
A row decoding operation for decoding an address signal and selecting one of the word lines of the cell array block is performed. At this time, if data such as cells connected to the selected word line is placed on the bit lines (BL, / BL), the signal indicating the operation time of the bit line sense amplifier is enabled and selected by the row address. Drive the sense amplifier drive circuit of the selected cell array block. In addition, the sense amplifier drive circuit changes the sense amplifier bias potential to the power supply potential (Vcc) and the ground potential (Vss), respectively, to drive the sense amplifier. When the sense amplifier starts operating, the bit lines (BL, / BL), which have maintained a minute potential difference, transition to a large potential difference. Thereafter, a column decoder selected by a column address transfers data on the bit line to a data bus. By turning on the column transfer transistor transmitting to the line, the data transmitted to the bit line (BL, / BL) is transmitted to the data bus line (DB, / DB) and output to the outside of the device.

With such an operation, the bit lines (BL, //
In the standby mode before the semiconductor memory element starts operating, the cell data is transmitted when the element operates while the semiconductor memory element is precharged to 1/2 Vcc and changes to another potential having a minute potential difference. That is, when the sense amplifier starts operating in this state, the potentials of the bit lines (BL, / BL) that maintain a minute potential difference change to the power supply potential (Vcc) and the ground potential (Vss), respectively. If the data of the bit line amplified in this way is transmitted to the data bus lines (DB, / DB) by the column decoder output signal (Yi), the potential of the bit line is changed for the next operation. 1 / 2Vcc by equalizing transistor
Equalize to

In order to equalize the bit lines in this way, the precharge operation is not performed immediately according to a precharge command input from the outside so as to prevent the cell data from being destroyed. After this delay time, the free charge operation is completed. FIG. 1 is a partial circuit diagram of a DRAM including a conventional sense amplifier.
A memory cell array (1) composed of cells (5);
Row that selects and drives word line by row address
A decoder (2), a sense amplifier (6) for sensing and amplifying data of a bit line connected to the selected word line, and a pull-up / pull-down bias potential signal for driving the sense amplifier (6). When the sense amplifier driver (9) and the sense amplifier (6) do not operate, the sense amplifier driving bias potential is changed to (1/1 /
2) An equalizing circuit (MN1) for equalizing to Vcc, and a data transmitting circuit (10) for transmitting the data of the bit line to the data bus lines (11, 12) by the output signal (Yi) of the column decoder (10). MN2, MN3).

The sense amplifier (6) amplifies a data signal from the memory cell array (1) or a data signal transmitted from the data bus lines (11, 12) with a power supply voltage (Vcc) and a ground voltage (Vss). For this purpose, it is composed of two inverters formed in a latch structure.

[0007]

In the conventional DRAM having the above operation, a pull-up / pull-down bias potential (S) is used in an active period in which the sense amplifier (6) operates.
A_P, SA_N) are the power supply potential (Vcc) and the ground potential (Vs
If the standby mode is entered in which the sense amplifier (6) does not operate while holding s), the equalizing circuit (MN) operates to raise the pull-up and pull-down bias potentials to (1/1).
2) It will be equalized to Vcc. In the operation section, the pull-up / pull-down bias potential having the power supply potential and the ground potential is not used for other purposes, and immediately enters the standby mode (1
/ 2) Equalized to Vcc, resulting in large current consumption. This applies not only to normal operation, but also to self-refresh operation in which an operation signal is automatically generated internally (refer to FIG. 2: here, t1: interval between one internal self-refresh operation, N: self-refresh cycle). , T2:
(Representing a refresh cycle).

According to the present invention, the equalizing operation is performed after transmitting the sense amplifier bias potential, which is the power supply potential and the ground potential after the sensing operation, to the sense amplifier bias that operates next, so that the next operation is performed. It is an object of the present invention to provide a DRAM that reduces current consumption when the sense amplifier operates.

[0009]

According to one aspect of the present invention, there is provided a sense amplifier for sensing and amplifying data of a bit line connected to a selected word line, and driving the sense amplifier. Sense amplifier to generate pull-up / pull-down bias potential signal
A driver and a dram having first and second sense amplifier arrays each including equalizing means for equalizing a sense amplifier drive bias potential when the sense amplifier does not operate, wherein a sense amplifier of the first sense amplifier array; A signal transmitting means connected between the sense amplifiers of the second array for switching the connection of the two bias potentials; and a control for generating signals for controlling the operations of the signal transmitting means, the sense amplifier driver and the equalizing means, respectively. Provided is a dram comprising signal generation means.

According to the operation of the present invention, the control signal generating means transmits, for example, a control signal to the sense amplifier driver of the first array to operate the sensing of the sense amplifier of the first array. A control signal is transmitted to the signal transmitting means, and the pull-up / pull-down bias potential, which is the power supply potential and the ground potential, is transmitted to the sense amplifier of the second array that operates next, and then transmitted to the equalizing means. A control signal is sent to equalize the pull-up / pull-down bias potential of the first array.

According to a second aspect of the present invention, in the diram of the first aspect, the sense amplifier bias potential equalizing means of the first sense amplifier array and the sense amplifier driver of the second sense amplifier array are the signal transmitting means. Operates after being turned on for a certain period of time.

According to a third aspect of the present invention, in the first aspect of the present invention, the signal transmission means includes first and second MOS transistors.
It is characterized by being made of a transistor.

According to a fourth aspect of the present invention, in the DRAM of the third aspect, the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the accompanying drawings. FIG. 3 is a partial circuit diagram of a DRAM according to an embodiment of the present invention, which includes two first and second sense amplifier arrays, each of which has a large number of memory cells (5, 25). Memory cell array (1, 2)
1) a row decoder (2, 22) for selectively driving a word line according to a row address; a sense amplifier (6, 26) for sensing and amplifying data of a bit line connected to the selected word line; Pull up / pull down to drive the sense amplifier (6, 26)
Sense amplifier driver (9,
29) and an equalizing circuit section (MN1, MN4) for equalizing the sense amplifier drive bias potential to (1/2) Vcc when the sense amplifiers (6, 26) do not operate; A data transmission circuit section (MN2, MN3, MN5, MN6) for transmitting data bus lines (11, 12) by an output signal (Yi) of the column decoder. Also, a signal transmission circuit unit (40) connected between the sense amplifier of the first sense amplifier array, the sense amplifier of the second sense amplifier array, and a sense amplifier driver (9). , 29)
And a control signal generation circuit section (41) for generating a signal for controlling the operation of each of the equalization circuit sections (MN1, MN4).
The signal transmission circuit unit (40) includes first and second MOS transistors. In the embodiment of the present invention, the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor.
It is composed of transistors.

The operation of the above configuration will be described with reference to the operation timing chart shown in FIG. 4. First, after the first sense amplifier array is operated, the bias potentials (SA_P, SA_N) of the sense amplifier are immediately equalized. , And the potential is continuously held. (T3 section) In the operation of the second sense amplifier array, the sensing operation first operates the word line (WL_2) (t3 section).
The transfer circuit units (MP1 and MN7) configured between the first sense amplifier array and the second sense amplifier array operate (section t4), and the sense amplifier driver (2
9) and the sense amplifier (26), the pull-up / pull-down bias potential (7,
8) is formed. When such an operation is performed, power is not directly used at the power supply potential or the ground potential in the operation of performing the sensing operation of the second array, but is first performed by charge sharing with the bias end of the first array. Thereafter, sensing occurs by the operation of the sense amplifier driver of the second array.

Table 1 below shows the pull-up / pull-down voltages of the first and second sense amplifier arrays.

[0017]

[Table 1]

Here, the first SA_P is the pull-up bias potential of the first array, the first SA_N is the pull-down bias potential of the first array, the second SA_P is the pull-up bias potential of the second array, and the second SA_N is the pull-up bias of the second array. down
Refers to the bias potential. Pull the first and second arrays from t4
The up bias potential (SA_P) becomes (3/4) Vcc because the pull-up bias potential (SA_P) of the first array which is the power supply potential Vcc and the second potential which is a half potential ((1/2) Vcc).
This is because charge sharing occurs between the array pull-up bias potential (SA_P). Since these have almost similar capacitance values, they become an intermediate potential when they are combined.

[0019]

As described above, the diram of the present invention equalizes the sense amplifier bias potential, which has been the power supply potential and the ground potential after the sensing operation, to the sense amplifier bias that is operated next, after the sensing operation. Performing the operation has an effect of reducing current consumption when the next sense amplifier operates.

[Brief description of the drawings]

FIG. 1 is a partial circuit diagram of a DRAM including a conventional sense amplifier.

FIG. 2 shows a timing diagram illustrating a conventional self-refresh operation.

FIG. 3 shows a partial circuit diagram of a diram according to one embodiment of the present invention.

FIG. 4 shows an operation timing chart of FIG. 3;

[Explanation of symbols]

 1, 21 ... memory cell array 2, 22 ... row decoder 3, 4, 23, 24 ... bit line 5, 25 ... memory cell 6, 26 ... bit line Sense amplifier 7, 8, 27, 28 ... sense amplifier enable signal 9 , 29 Sense amplifier driver 10 Column decoder 11, 12, 30, 31 Data bus line 40 Switch circuit section C1, C2 Bit line capacitor MN1, MN4 Bit line equalization circuit MN2, MN3, MN5, MN6 Column selection circuit

Claims (4)

[Claims] A sense amplifier for sensing and amplifying data on a bit line connected to a selected word line; a sense amplifier driver for generating a pull-up / pull-down bias potential signal for driving the sense amplifier;
In a DRAM having first and second sense amplifier arrays each including equalizing means for equalizing a sense amplifier drive bias potential when the sense amplifier does not operate, a sense amplifier of the first sense amplifier array;
A signal transmitting means connected between the sense amplifiers of the second array for switching the connection of the two bias potentials; and a control for generating signals for controlling the operations of the signal transmitting means, the sense amplifier driver and the equalizing means, respectively. A dram comprising signal generation means. 2. The method of claim 1, wherein the sense amplifier bias potential equalizing means of the first sense amplifier array and the sense amplifier driver of the second sense amplifier array operate after the signal transmission means has been turned on for a predetermined time. The dram of claim 1, wherein 3. The diram according to claim 1, wherein said signal transmission means comprises first and second MOS transistors. 4. The DRAM according to claim 3, wherein said first MOS transistor is a PMOS transistor, and said second MOS transistor is an NMOS transistor.