JPH1041385A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To facilitate manufacturing of a buried wiring and effectively reduce the parasitic capacitance of the wiring, by forming an insulation film having a higher etching rate and lower specific dielectric const. than those of an insulation film beneath a wiring pattern on a region between the wiring patterns. SOLUTION: The device has a first insulation film 11 on element regions on a semiconductor substrate 10 or wiring layer and wiring pattern 17' on this film 11. It also has a second insulation film 12 having a higher etching rate and lower specific dielectric const. than those of the first film 11 at least at a region formed between the patterns 17'. A first silicon oxide film 11 is deposited e.g. on the semiconductor substrate 10 having element regions, and SiOF film 12 is deposited thereon and used as an etching stopper to form wiring grooves 13. After forming contact holes 14, a second silicon oxide film 15, TiN film 16 and Al 17 are deposited to form the wiring 17'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a method of forming a wiring layer having a low parasitic capacitance using embedded wiring.

[0002]

2. Description of the Related Art A method of forming a wiring pattern by forming a wiring groove and filling the groove with a conductor is a conventional method of forming a wiring pattern by etching a wiring metal because there is no halation due to the wiring metal at the time of exposure. It is easier to form a fine groove pattern in the insulating film as compared with the method described above, and the fineness of the wiring pattern is easy because the flatness is excellent. For this reason, embedded wiring is an indispensable manufacturing method in LSI circuits that will be miniaturized in the future. For details on how to form grooved wiring,
For example, there is a method as disclosed in JP-A-6-244180. This conventional example is shown in FIG. As shown in this example, a silicon oxide film or BPSG 51 or 52 is mainly used as an interlayer insulating film, and silicon with a low etching rate is used as an etching stopper in order to suppress variations in the depth of the wiring groove 54 when forming the groove. The nitride film 53 is used. As described above, in forming the groove wiring, it is necessary to provide an etching stopper at the bottom of the groove in order to make the depth of the groove uniform. In FIG. 5, 1 is a source / drain region, 2 is a gate electrode, and 3 is a field oxide film.

On the other hand, in a large-scale integrated circuit, with the recent miniaturization of semiconductor elements, circuit delay due to resistance and parasitic capacitance of wiring connecting elements has become a serious problem. In particular, as the distance between adjacent wirings becomes shorter, the capacitance between the adjacent wirings becomes larger, which leads to an increase in wiring delay, crosstalk, etc., which hinders a high-speed circuit,
It also causes malfunction. As a countermeasure, a method using an insulating film having a low dielectric constant is generally used in order to reduce the parasitic capacitance between wirings. As such a low dielectric constant film, an organic film such as a fluorine-containing silicon oxide film (SiOF) or Teflon has been proposed. These films often contain fluorine, have problems such as corrosion of wiring metal, and have poor adhesion to metal, so that they cannot directly contact with wiring metal, and the film that directly contacts metal is different from conventional ones. Similarly, a silicon oxide film is used. FIG. 6 shows a conventional example of a method of forming a multilayer wiring using a low dielectric constant film. In FIG. 6, reference numeral 60 denotes a substrate, 61 denotes a first silicon oxide film, 62 denotes a second silicon oxide film, 63 denotes a low dielectric constant film, 64 denotes a third silicon oxide film, and 65 denotes a wiring metal. .

[0004]

In the conventional method of forming a trench wiring using a silicon oxide film as a main interlayer insulating film, a film used as a stopper is a film having a high relative dielectric constant like a silicon nitride film. Therefore, in a circuit having highly integrated wiring, the capacitance between adjacent wirings is increased as compared with a method in which wiring is formed by patterning a metal, resulting in delay and crosstalk. For this reason, it is necessary to make the silicon nitride film thin, but in this case, if the selectivity between the silicon oxide film and the silicon nitride film at the time of trench etching is not sufficiently high, the nitride film may come off and may not function sufficiently as an etching stopper. is there. As the degree of integration of the wiring increases, the effect of the increase in the capacitance between wirings due to the silicon nitride film increases,
It is necessary to make the silicon nitride film thinner, and it is difficult to apply the silicon trench film to next generation integrated circuits in the conventional trench wiring process. For example, when the nitride thickness of the etching stopper is 100 nm in the conventional example of FIG. 5, the wiring parasitic capacitance increases by about 10%.

As for the use of a low dielectric constant film, the thickness of the interlayer insulating film does not tend to be reduced. Therefore, in a highly integrated circuit, it is most preferable to reduce the capacitance between adjacent wirings than the capacitance between the substrate and the capacitance between wiring layers. Importantly, if a low dielectric constant film is provided between the wirings, the wiring parasitic capacitance can be effectively reduced. That is, there is no need to provide a low dielectric constant film above the wiring. FIG. 7 shows how the capacitance between adjacent wirings in the total wiring capacitance increases as the wiring pitch becomes finer.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to use a low dielectric constant film in a buried wiring manufacturing method to facilitate the manufacture of the buried wiring and to effectively reduce the parasitic capacitance of the wiring.

[0007]

According to the present invention, a first insulating film is provided on an element region or a wiring layer on a semiconductor substrate, and a wiring pattern is formed on the first insulating film. And a semiconductor device characterized by having a second insulating film having a higher etching rate and a lower relative dielectric constant than the first insulating film in at least a region between the wiring patterns.

According to a second aspect of the present invention, the first insulating film is a silicon oxide film, and the second insulating film is a fluorine-containing silicon oxide film or a fluorine-containing amorphous carbon film. A semiconductor device according to claim 1 is obtained.

According to the third aspect of the present invention, the step of forming the first insulating film on the element region or the wiring layer on the semiconductor substrate is performed at a higher etching rate than the first insulating film, and Forming a second insulating film having a low dielectric constant, and covering a region other than a region corresponding to a desired wiring pattern on the second insulating film with a resist by a normal exposure method;
Forming a wiring groove by etching a region of the second insulating film corresponding to the wiring pattern using the resist as a mask and the first insulating film as an etching stopper; Forming a conductor on the entire surface of the insulating film, and forming a wiring pattern by removing the conductor in a region other than inside the wiring groove and leaving the conductor only inside the wiring groove. A method for manufacturing a semiconductor device according to claim 1 or 2 is obtained.

As described above, in the semiconductor device and the method of manufacturing the same according to the present invention, a conventional interlayer insulating film such as a silicon oxide film is used between wiring layers, a low dielectric constant film is used as a wiring groove forming layer, and a lower interlayer insulating film is used. The first is to use the film as an etching stopper.
The second feature is that the wiring groove formed in the low dielectric constant film layer is buried with a wiring metal so that the insulating film between adjacent wirings has a low dielectric constant.

[0011]

By using a sufficiently thick interlayer insulating film between wiring layers as an etching stopper, it is easy to form a wiring groove having a uniform depth, and by using a low dielectric constant film as an insulating film of the wiring layer, wiring parasitic capacitance can be reduced. Effectively reduce.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 1 and 2 show a first embodiment of the present invention in the order of steps. A first silicon oxide film 11 having a thickness of 0.6 μm is formed on a semiconductor substrate 10 having an element region (source / drain region 1, gate electrode 2, field silicon oxide film 3) including a MOS transistor by a plasma CVD method. Is deposited. Next, the first silicon oxide film 11 is polished and flattened by a chemical mechanical polishing method. At this time, the thickness of the first silicon oxide film 11 is set to be 0.5 μm from the field silicon oxide film 3. On the flattened first silicon oxide film 11, an SiOF film 12 is formed by a plasma CVD method to a thickness of 0.5 μm.
m. The SiOF film is made of, for example, SiF ₄
/ O ₂ / Ar, each of which is 40 sccm / 8
Supply into the reaction layer at a flow rate of 0 sccm / 70 sccm,
The film is formed at an RF power of 1.4 kW. At this time, Si
The dielectric constant of the OF film becomes 3.5.

Next, a resist mask for forming a wiring groove is formed on the SiOF film 12 by ordinary photolithography, and a wiring groove 13 is formed by anisotropic dry etching. The dry etching conditions are the same as ordinary silicon oxide film etching conditions, for example, in RF with an output of 1000 W, pressure of 300 mT, Ar / CF ₄
/ CHF ₃ at 200 sccm / 20 sccm /
When supplied at a flow rate of 20 sccm, the etching rate of the SiOF film 12 can be made about three times as large as that of the SiO ₂ film. Therefore, the variation in the thickness of the SiOF film 12 and the variation in the etching amount in the substrate surface are taken into consideration. And the desired SiOF
Even if overetching is performed more than the etching amount calculated from the film thickness, all layers of the first silicon oxide film 11 serve as an etching stopper, and the wiring groove 13 having a uniform depth can be formed. After forming the wiring groove, a resist mask for forming a contact hole is formed by a usual photolithography technique, and the contact hole 14 is opened by anisotropic dry etching. This etching condition is performed under the same conditions as ordinary silicon oxide film etching.

After forming the wiring groove 13 and the contact hole 14 as described above, a second silicon oxide film 15 is deposited on the entire surface of the substrate 10 including the wiring groove 13 and the contact hole 14 to a thickness of 50 nm by the plasma CVD method. Then, this is etched back so that the second silicon oxide film 15 remains in a sidewall shape only on the side wall portions of the wiring groove 13 and the contact hole 14. Next, a TiN film 16 serving as a barrier metal is formed to a thickness of 50 nm by a CVD method or a sputtering method using a wiring groove 13 and a contact hole 14.
Deposited on the side wall of These second silicon oxide films 15
One of the roles of the TiN16 film and the TiN16 film is that the wiring metal and SiON
The purpose is to prevent the fluorine in the F film from reacting.

Subsequently, the contact hole 14 and the wiring groove 1 are formed.
Aluminum 17 is deposited as a wiring metal on the entire surface of the wafer including the inside of the substrate 3 by the CVD method, and the wiring 17 'is formed by removing aluminum other than the wiring grooves 13 and the contact holes 14 by a chemical mechanical polishing method. .

As described above, according to the first embodiment of the present invention, the first silicon oxide film 11 under the wiring layer is formed.
Are all used as etching stoppers at the time of etching the wiring groove 13, so that there is no possibility that they are removed at the time of etching as in the conventional example, the margin of the etching amount is increased, and the processing is facilitated. Furthermore, a low dielectric constant SiOF between adjacent wirings
The presence of the film 12 can reduce the parasitic capacitance of the wiring by about 10%.

Next, sectional views showing a second embodiment of the present invention in the order of steps are shown in FIGS. As in the first embodiment, the device regions (source / drain region 1, gate electrode 2,
A first silicon oxide film 21 is deposited to a thickness of 0.6 μm on a semiconductor substrate 20 including the field silicon oxide film 3). Next, the first silicon oxide film 21 is polished and flattened by a chemical mechanical polishing method. At this time, the thickness of the first silicon oxide film 21 is set to be 0.5 μm from the field silicon oxide film 3. This flattened first
First, a hydrogen-containing amorphous carbon film 22 is deposited to a thickness of 10 nm on the silicon oxide film 21 of FIG.
3 is deposited to a thickness of 0.5 μm. These are all plasma C
This is performed by the VD method. The hydrogen-containing amorphous carbon film 22 has a role of a buffer film for improving the adhesion between the first silicon oxide film 21 and the fluorine-containing amorphous carbon film 23.

The conditions for forming the hydrogen-containing amorphous carbon film 22 and the fluorine-containing amorphous carbon film 23 are, for example, RF power 2 k
In a reaction layer of W and a pressure of 2 mT, the deposition gas is changed from CH ₄ to C
_By converting to ₂ F ₆ (each flow rate is 50 sccm), a film can be continuously formed. At this time, the relative dielectric constant of the fluorine-containing amorphous carbon film 23 becomes 2.5.

Thereafter, a wiring groove 24 and a contact hole 25 are formed in the same manner as in the first embodiment. At this time, the etching condition of the wiring groove 24 is, for example, the same as in the first embodiment, in RF of output 1000 W, pressure of 300 mT, A
r / CF ₄ / CHF ₃ at 200 sccm / 20
Supply at a flow rate of sccm / 20 sccm. At this time, the etching rate of the fluorine-containing amorphous carbon film 23 can be made five times that of the silicon oxide film 21. Even if overetching is performed over the etching amount calculated from the desired film thickness of the fluorine-containing amorphous carbon film 23 in consideration of the variation in the thickness, the entire first silicon oxide film 21 becomes an etching stopper, The wiring groove 24 having a small depth can be formed. Thereafter, similarly to the first embodiment, the side walls of the wiring groove 24 and the contact hole 25 are
Then, a TiN film 27 serving as a barrier metal is deposited to a thickness of 50 nm. Subsequently, aluminum 28 is deposited as a wiring metal by CVD on the entire surface of the substrate including the inside of the contact hole 25 and the wiring groove 24, and aluminum other than the inside of the wiring groove 24 and the contact hole 25 is removed by chemical mechanical polishing. Thus, a wiring 28 'is formed.

As described above, according to the second embodiment of the present invention, the first silicon oxide film 21 under the wiring layer is formed.
Are all used as etching stoppers at the time of etching the wiring groove, so that there is no possibility of being removed at the time of etching as in the conventional example, and the margin of the etching amount is increased, and the processing becomes easy. Furthermore, since the fluorine-containing amorphous carbon film 23 having a low dielectric constant is provided between the adjacent wirings, the parasitic capacitance of the wirings can be reduced by about 30%.

The film forming methods and etching conditions described in the first and second embodiments are examples of the manufacturing method of the present invention, and gas conditions and deposition methods other than the methods described here can be used. is there. Although the method of manufacturing the wiring layer on the semiconductor element has been described here, the same method can be applied to the formation of the second and subsequent wiring layers in the multilayer wiring.

[0022]

As described above, in the semiconductor device and the manufacturing method according to the present invention, a SiOF film or an organic insulating film having a low dielectric constant and a high etching rate is used for a wiring layer portion.
Since the silicon oxide film between the wiring layers functions as an etching stopper, the formation of the trench wiring is facilitated as compared with the conventional case where the stopper film is particularly formed. Further, compared with the conventional structure using an etching stopper of a high dielectric constant film such as a nitride film, since an insulating film having a low dielectric constant is provided between adjacent wirings, for example, as shown in FIG. It can be reduced by 10 to 30%.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a process until a contact hole is formed in a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a process until a wiring is formed in the first embodiment of the present invention.

FIG. 3 is a cross-sectional view illustrating a process until a contact hole is formed in a second embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a process until a wiring is formed in a second embodiment of the present invention.

FIG. 5 is a cross-sectional view after a buried wiring is formed by a conventional method.

FIG. 6 is a cross-sectional view of a case where a low dielectric constant film according to a conventional method is applied without using an embedded wiring.

FIG. 7 is a diagram comparing each component of a wiring parasitic capacitance according to a wiring pitch;

[Explanation of symbols]

 Reference Signs List 1 source / drain region 2 gate electrode 3 field silicon oxide film 10 semiconductor substrate 11 first silicon oxide film 12 SiOF film 13 wiring groove 14 contact hole 15 second silicon oxide film 16 TiN film 17 aluminum 17 'wiring 20 semiconductor substrate Reference Signs List 21 first silicon oxide film 22 hydrogen-containing amorphous carbon film 23 fluorine-containing amorphous carbon film 24 wiring groove 25 contact hole 26 second silicon oxide film 27 TiN film 28 aluminum 28 'wiring 50 semiconductor substrate 51 first Silicon oxide film or BPSG film 52 second silicon oxide film or BPSG film 53 silicon nitride film 54 wiring groove 60 semiconductor substrate 61 first silicon oxide film 62 second silicon oxide film 63 low dielectric constant film 64 third Silicon oxide film 65 Wiring metal 66 Burr Ametal

Claims (3)

[Claims] A first insulating film on an element region or a wiring layer on a semiconductor substrate, a wiring pattern on the first insulating film, and at least a region sandwiched between the wiring patterns; A semiconductor device comprising a second insulating film having a higher etching rate and a lower relative dielectric constant than the first insulating film. 2. The method according to claim 1, wherein said first insulating film is a silicon oxide film, and said second insulating film is a fluorine-containing silicon oxide film or a fluorine-containing amorphous carbon film. Semiconductor device. 3. A step of forming a first insulating film on an element region or a wiring layer on a semiconductor substrate, and a step of forming a second insulating film having a higher etching rate and a lower relative dielectric constant than the first insulating film. Forming a film, covering a region other than a region corresponding to a desired wiring pattern on the second insulating film with a resist by a normal exposure method, and using the resist as a mask to form the first insulating film.
Forming a wiring groove by etching a region of the second insulating film corresponding to the wiring pattern using the insulating film as an etching stopper;
Forming a conductor on the entire surface of the insulating film, and forming a wiring pattern by removing the conductor in a region other than inside the wiring groove and leaving the conductor only inside the wiring groove. Claim 1 or Claim 2
The manufacturing method of the semiconductor device described in the above.