JP3183238B2 - Method for manufacturing semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device having a multilayer wiring structure.

[0002]

2. Description of the Related Art In LSI devices, wiring layer processing by dry etching of an Al alloy film is mainly used. However, with the miniaturization of the wiring pitch, the fine processing by dry etching of the Al alloy film has become extremely difficult. In addition, a trench wiring (damascene process) is being studied as a technology that can replace dry etching, because a material that is difficult to dry-etch, such as a Cu film, is used as a wiring layer as a low-resistance wiring material instead of an Al alloy.

[0003] For example, as shown in FIG.
An insulating film 1 such as a field oxide film on a semiconductor substrate such as silicon is selectively covered to form a plurality of wiring layers,. . . , 2
i, 2j, 2k,. . . To form Next, a silicon oxide film 31 is formed to a thickness of, for example, 1000 nm, and a silicon nitride film (hereinafter referred to as a plasma nitride film) 32 formed by a plasma CVD method is formed to a thickness of, for example, 200 nm.
As shown in FIG. 3 (b), the opening diameter is adjusted to a predetermined wiring layer 2j using KrF excimer lithography.
A photoresist film 5 having an opening 4 of about 2 μm is formed, and then the opening 4a is formed by anisotropically etching the plasma nitride film by dry etching using the photoresist film 5 as a mask. Next, after the photoresist film 5 is peeled off, as shown in FIG.
3 is formed, for example, to a thickness of 500 nm. Subsequently, the opening width 0.3 μm aligned with the opening 4 a of the plasma nitride film 32.
A photoresist film 7 having an opening 6 of about m is formed. Next, as shown in FIG. 14A, a groove 8 is formed in the silicon oxide film 33 by dry etching using the photoresist film 7 as a mask, and the plasma nitride film 32 is continuously formed.
Using silicon oxide as a mask, silicon oxide film 31 is anisotropically etched to form via hole 9 tight to wiring layer 2j. Next, as shown in FIG. 14B, after the photoresist film is stripped, the trench 8 and the via hole 9 are filled to form a metal film 10, and the metal film 33 on the silicon oxide film 33 is removed by CMP or etch back. The buried metal 11 which is an upper wiring layer is formed as shown in FIG. 14C by removing and leaving the trench 8 and the via hole 9.

[0004] By repeating such a method, a multilayer wiring structure can be formed.

[0005]

In the above-described conventional method for manufacturing a semiconductor device, a plasma nitride film is used as an intermediate layer, and this plasma nitride film layer is used as an etching stopper film when forming a wiring groove and an etching mask when forming a via hole. Used as When a via hole having a large aspect ratio is formed in a silicon oxide film under the plasma nitride film as a mask using a plasma nitride film as a mask, if a silicon oxide film / plasma nitride film has a high etch rate ratio (selectivity), etching is stopped halfway. "Occurs. Beer hole 9
Oxygen atoms generated when the silicon oxide film 31 is etched to form the oxide film have an action of removing the deposition film formed on the plasma nitride film 32. This is because if a deposition film is to be formed, an unnecessary amount of the deposition film is formed on the side surface of the via hole during the formation. There is a trade-off relationship between the selectivity of the silicon oxide film / plasma nitride film and the etching depth of the via hole. In order to form a fine via hole, the silicon oxide film / plasma nitride film becomes larger as the aspect ratio of the via hole increases. You have to lower the selectivity. At this time, since the plasma nitride film on the bottom of the wiring groove is shaved, the buried metal in the wiring groove, that is, the plasma nitride film having a large dielectric constant is present on the side surface of the upper wiring layer. Therefore, there is a problem that the parasitic capacitance between adjacent wiring layers next to the same layer increases.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for forming a wiring layer which can further reduce the parasitic capacitance between adjacent wiring layers and has good controllability.

[0007]

[0008]

According to the present invention, in order to solve the problems] After forming a plurality of first wiring layer to selectively cover the first insulating film on a semiconductor substrate, a second insulating film, etch stop film
Forming an interlayer insulating film by sequentially depositing a third insulating film and a first opening covering the interlayer insulating film and having a first opening aligned with the predetermined first wiring layer; Forming a resist film, anisotropically etching the interlayer insulating film using the first resist film as a mask to form a first via hole connected to the predetermined first wiring layer;
After one of the resist film stripping, and the step of filling the first via hole to form a first organic film by a coating method, the first
Organic film covering the second resist film having a second opening that is visual alignment with the first via hole, by etching the first organic film using the second resist film as a mask, Subsequently, the interlayer insulating film is etched
Forming a first wiring groove by performing anisotropic etching up to the stop film , removing the second resist film and the first organic film,
Exposing a surface of the predetermined first wiring layer;
A step of depositing a first metal film fills the first wiring groove and the first via hole, the interlayer insulating film to leave said first metal film on the first wiring groove and the first via hole Forming a buried metal as an upper wiring layer connected to the predetermined wiring layer via the first via hole by removing the buried metal from the semiconductor device. In this case , a first silicon oxide film, a plasma nitride film, and a second silicon oxide film can be formed as the second insulating film, the etching stopper film, and the third insulating film, respectively.

[0009]

According to the configuration of the present invention, the first via hole is formed by etching the interlayer insulating film, since the filling in the first organic film to form a first interconnection groove, a first wiring groove It is possible to prevent the shape of the first via hole from being adversely affected during the formation.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a semiconductor device related to the present invention will be described.
The technology of the method of manufacturing the device will be described first.
As shown in (a), an insulating film 1 such as a field insulating film on a semiconductor substrate such as silicon is selectively covered to form a plurality of wiring layers,..., 2i, 2j, 2k,. The silicon oxide film 31A is formed, for example, to a thickness of 1000 nm,
The plasma nitride film 32A (etching stop film) has a thickness of, for example, 50 nm, and the silicon oxide film 33A has a thickness of, for example, 500 nm.
The layers are sequentially deposited to form an interlayer insulating film.

Subsequently, as shown in FIG. 1B, a photoresist film 7A having an opening 6A having a width of about 0.3 μm is formed above the wiring layer 2j by using KrF excimer lithography. Next, the silicon oxide film 33 is dry-etched using the photoresist film 7A as a mask.
A is selectively etched with respect to the plasma nitride film 32A to form a wiring groove 8A. At this time, a parallel plate type narrow gap RIE apparatus was used as an etching apparatus, and a first mixed gas obtained by mixing C ₄ F ₈ , CO, Ar and O ₂ at a predetermined ratio was used as an etching gas. In the conventional example, the etching must be continued to form the via hole 9 even after the formation of the wiring groove 8 is temporarily completed, and therefore, there is a problem that the plasma nitride film 32 is etched. This is because even if a deposition film is formed on the plasma nitride film 32 due to the action of oxygen generated at the time of etching the silicon oxide film 31 for forming the via hole, it is removed. In the present embodiment, since the etching can be stopped immediately after the formation of the wiring groove 8A, such a problem does not occur.

After removing the photoresist film 7A, an organic material is applied to the entire surface of the semiconductor substrate and baked on a hot plate at about 180 ° C. to form an organic coating film 12 as shown in FIG. I do. This organic coating film may be the same as the photoresist film except that it does not contain a photosensitive agent.

Subsequently, as shown in FIG. 2A, a photoresist film 14 having an opening 13 having an opening diameter of about 0.2 μm aligned with a predetermined wiring layer 2j is formed, and this photoresist film 14 is formed. The organic coating film 12 is dry-etched as a mask, and the plasma nitride film 32 under the organic coating film 12 is used as a mask.
A and the silicon oxide film 31A are continuously anisotropically etched to form a via hole 9A tight to the wiring layer 2j.
However, Cl ₂ and O ₂ are used for etching the organic coating film 12.
(Since the photoresist film 14 is also etched, its thickness must be sufficiently thickened in advance.) In the etching of the plasma nitride film 32A, the mixed gas of O ₂ in the first mixed gas is used. The second mixed gas having a higher ratio was used, and the first mixed gas was used for etching the silicon oxide film 31A. Since the wiring groove 8A is filled with the organic coating film when the via hole is formed, only a hole is formed on the bottom surface, and no other shape change occurs.

Photoresist film 14 and organic coating film 12
Is removed by a plasma ashing method or the like, thereby completing the formation of the wiring groove 8A and the via hole 9Aa as shown in FIG. 2B.

Next, as shown in FIG.
An aluminum film (metal film 10A) having a thickness of at least one, for example, 0.2 μm, is deposited every two minutes of 0.3 μm width of A to fill the wiring groove 8A and the via hole 9Aa.

Next, the metal film 1 on the silicon oxide film 33A
OA was removed by a CMP method or an etch-back method, and FIG.
As shown in FIG. 6, the buried metal 11A is left only in the wiring groove 8A and the via hole 9Aa. This embedded metal 1
1A is an upper wiring layer (groove wiring) connected to the wiring layer 2j via the via hole 9Aa. Thus, a two-layer wiring structure can be formed.

Further, by repeating the steps after the formation of a wiring layer (not shown) on the silicon oxide film 33A,
It is possible to form a multilayer wiring structure having more than one layer.

By making the etching condition of the silicon oxide film 33A for forming the wiring groove 8A selective with respect to the plasma nitride film 32A, the depth of the wiring groove 8A can be made approximately the same as the thickness of the silicon oxide film 33A. Can be controlled.
Further, since the via hole 9A is formed after filling the wiring groove 8A with the organic coating film 12, there is no undesired change in shape other than the formation of the via hole through the bottom surface of the wiring groove 8A.

The silicon oxide film 31 used in FIGS.
It goes without saying that a fluorine-added silicon oxide film (usually abbreviated as SiOF) having a lower dielectric constant and other inorganic insulating films can be used in place of A and 33A. SiO
The F film can be formed by a plasma CVD method by adding a fluorine-based gas such as NF3 to a mixed gas of tetraethylorthosilicate (TEOS) and oxygen. Further, instead of the plasma nitride film, a plasma C
Silicon oxynitride film (hereinafter referred to as plasma Si
ON film) can also be used.

Next, a first embodiment of the present invention will be described. First, as shown in FIG. 4A, an insulating film 1 such as a field insulating film on a semiconductor substrate such as silicon is formed.
., 2i, 2
are formed, the silicon oxide film 31A is, for example, 1000 nm in thickness, the plasma nitride film 32A (etching stop film) is, for example, 50 nm in thickness, and the silicon oxide film 3 is formed.
3A is sequentially deposited, for example, to a thickness of 500 nm to form an interlayer insulating film.

Subsequently, using KrF excimer lithography, as shown in FIG. 4B, a photoresist film 14A having an opening 13A with an opening diameter of about 0.2 μm aligned with the wiring layer 2j is formed. Next, using the photoresist film 14A as a mask, the silicon oxide film 33A, the plasma nitride film 32A and the silicon oxide film 31A are successively anisotropically etched by dry etching to form the wiring layer 2j.
Is formed. At this time, a parallel plate type narrow gap RIE apparatus was used as an etching apparatus, and a mixed gas of C ₄ F ₈ , CO, Ar and O ₂ was used as an etching gas. That is, as in the first embodiment, the first mixed gas was used for etching the silicon oxide films 33A and 31A, and the second mixed gas was used for etching the plasma nitride film.

After the photoresist film 14A is removed, an organic material is applied to the entire surface of the semiconductor substrate and baked on a hot plate at about 180 ° C. in the same manner as in the first embodiment, to thereby obtain FIG. As shown in a), an organic coating film 12A is formed. This organic coating film may be the same as the photoresist film except that it does not contain a photosensitive agent.

Subsequently, as shown in FIG. 5B, an opening 6 having a width of about 0.3 μm aligned with the via hole 9B.
A photoresist film 7B having B is formed. Next, the organic coating film 12A is anisotropically etched by dry etching using the photoresist film 7B as a mask. At this time, an ICP plasma etching apparatus was used as an etching apparatus, and a mixed gas of Cl ₂ and O ₂ was used as an etching gas.

Next, using the photoresist film 7B and the organic coating film 12A as a mask, the silicon oxide film 33A is selectively etched with respect to the plasma nitride film 32A by dry etching, and as shown in FIG. Groove 8B
To form At this time, a parallel plate type narrow gap RIE apparatus was used as an etching apparatus as in the case of via hole etching, and a first mixed gas was used as an etching gas.

Next, after the photoresist 7B and the organic coating film 12A are peeled off, as shown in FIG. 6A, at least one-half of the 0.3 μm width of the wiring groove 8B, for example, 0.2 μm,
An aluminum film (metal film 10B) having a thickness of 10 nm is deposited to fill the wiring groove 8B and the via hole 9B.

Next, the metal film 1 on the silicon oxide film 33A
OB was removed by a CMP method or an etch-back method, and FIG.
As shown in (b), the buried metal 11B is left only in the wiring groove 8B and the via hole 9B. The buried metal 11B is an upper wiring layer (groove wiring) connected to the wiring layer 2j via the via hole 9B. Thus, a two-layer wiring structure can be formed.

Further, by repeating the steps after the formation of a wiring layer (not shown) on the silicon oxide film 33A,
It is possible to form a multilayer wiring structure having more than one layer.

A via hole 9B is formed, and the organic coating film 12 is formed.
Since the wiring groove 8B is formed after filling with A, the wiring groove 8B
The etching condition of the silicon oxide film 33A for forming the via is made selective with respect to the plasma nitride film 32A, so that an undesired shape change other than the removal of the upper part of the via hole 9B does not occur, and the wiring groove 8B The depth can be controlled to the same level as the thickness of the silicon oxide film 33A.

The silicon oxide film 31 used in the present embodiment
It goes without saying that a fluorine-added silicon oxide film (usually abbreviated as SiOF) having a lower dielectric constant and other inorganic insulating films can be used in place of A and 33A. Also,
As the etching stopper film, a plasma SiON film can be used instead of the plasma nitride film.

Next, a second technique related to the present invention will be described. As shown in FIG. 7A, first, an insulating film 1 such as a field insulating film on a semiconductor substrate such as silicon is formed.
., 2i, 2
are formed, and a silicon oxide film is deposited to a thickness of, for example, 1500 nm to form an interlayer insulating film 3.

Subsequently, as shown in FIG. 7B, a photoresist film 7C having an opening 6C having a width of about 0.3 μm is formed above the wiring layer 2j by using KrF excimer lithography. Next, the silicon oxide film (3) is dry-etched using the photoresist film 7C as a mask.
Is etched to a depth of about 500 nm to form a wiring groove 8C. At this time, a parallel plate type narrow gap RIE apparatus was used as an etching apparatus, and a first mixed gas in which C ₄ F ₈ , CO, Ar and O ₂ were mixed was used as an etching gas.

After the removal of the photoresist film 7C, an organic material is applied to the entire surface of the semiconductor substrate and baked on a hot plate at about 180 ° C. in the same manner as in the first embodiment, to thereby obtain FIG. ), The organic coating film 12
Form B. This organic coating film may be the same as the photoresist film except that it does not contain a photosensitive agent.

Subsequently, as shown in FIG. 8A, a photoresist film 14B having an opening 13B having an opening diameter of about 0.2 μm aligned with a predetermined wiring layer 2j is formed.
Using the photoresist film 14B as a mask, the organic coating film 12B and the underlying silicon oxide film (3) are anisotropically dry-etched using a mixed gas of Cl ₂ and O ₂ and a first mixed gas, respectively, to form a wiring layer. A via hole 9C extending to 2j is formed.

Photoresist film 14B and organic coating film 1
By stripping 2B by a plasma ashing method or the like, as shown in FIG. 8B, the formation of the wiring groove 8C and the via hole 9C is completed.

Next, as shown in FIG.
An aluminum film (metal film 10C) having a thickness of at least half the width of C of 0.3 μm, for example, 0.2 μm, is deposited to fill the wiring groove 8C and the via hole 9C.

Next, the metal film 1 on the silicon oxide film (3)
9C is removed by a CMP method or an etch-back method, and FIG.
As shown in FIG. 7, the buried metal 11C is left only in the wiring groove 8C and the via hole 9C. This embedded metal 11
C is an upper wiring layer (groove wiring) connected to the wiring layer 2j via the via hole 9C. Thus, a two-layer wiring structure can be formed.

Further, by repeating the steps after the formation of a wiring layer (not shown) on the silicon oxide film (3),
It is possible to form a multilayer wiring structure having more than one layer.

This second technique is inferior in the controllability of the depth of the wiring groove 8C when the plasma nitride film 32A is not formed by the technique of FIGS. 1 to 3, but the other effects are the same. Yes, because an etching stop film such as a plasma nitride film having a large dielectric constant is not used, the upper wiring layer (11C) is used.
There is an advantage that the parasitic capacitance between the wiring layer 2j and the lower wiring layer 2j can be reduced.

It goes without saying that, instead of the silicon oxide film (3) used in the present embodiment, a fluorine-added silicon oxide film SiOF having a lower dielectric constant and other inorganic insulating films can be used. The SiOF film is formed by mixing NF ₃ with a mixed gas of tetraethylorthosilicate (TEOS) and oxygen.
Can be formed by a plasma CVD method by adding a fluorine-based gas such as

Next , a third technique related to the present invention will be described. As shown in FIG. 10A, first, an insulating film 1 such as a field insulating film on a semiconductor substrate such as silicon is formed.
., 2i, 2
are formed, and a silicon oxide film is deposited to a thickness of, for example, 1500 nm to form an interlayer insulating film 3.

Subsequently, using KrF excimer lithography, as shown in FIG. 10B, a photoresist film 14C having an opening 13C having an opening diameter of about 0.2 μm aligned with the wiring layer 2j is formed. Next, using the photoresist film 14C as a mask, the silicon oxide film (3) is anisotropically etched by dry etching to form a wiring layer 2j.
Is formed. At this time, a parallel plate type narrow gap RIE apparatus was used as an etching apparatus, and a first mixed gas in which C ₄ F ₈ , CO, Ar and O ₂ were mixed was used as an etching gas. After the removal of the photoresist film 14C, in the same manner as in the first embodiment,
An organic material is applied to the entire surface of the semiconductor substrate and baked on a hot plate at about 180 ° C.
As shown in (a), an organic coating film 12C is formed. This organic coating film may be the same as the photoresist film except that it does not contain a photosensitive agent.

Subsequently, as shown in FIG. 11B, an opening 6 having a width of about 0.3 μm aligned with the via hole 9D.
A photoresist film 7D having D is formed. Next, the organic coating film 12C is anisotropically etched by dry etching using the photoresist film 7D as a mask. At this time, an ICP plasma etching apparatus was used as an etching apparatus, and a mixed gas of Cl ₂ and O ₂ was used as an etching gas.

Next, using the photoresist film 7D and the organic coating film 12C as a mask, the silicon oxide film (3) is etched to an etching depth of about 500 nm by dry etching to form a wiring groove 8D as shown in FIG. Form. At this time, as in the via hole etching, a parallel plate type narrow gap RIE apparatus is used as an etching apparatus, and C ₄ F ₈ , CO, Ar and O are used as etching gases.
The first mixed gas obtained by mixing ₂ was used.

Photoresist film 14C and organic coating film 1
After the 2C is peeled off by a plasma ashing method or the like, as shown in FIG. 12A, an aluminum film (metal film 10D) having a thickness of at least half the width of 0.3 μm of the wiring groove 8D, for example, 0.2 μm, is formed. ) To fill the wiring groove 8D and the via hole 9D.

Next, the metal film 1 on the silicon oxide film (3)
OD was removed by a CMP method or an etch-back method, and FIG.
As shown in FIG. 2B, the wiring groove 8D and the via hole 9D
Only as buried metal 11D. The buried metal 11D is an upper wiring layer (groove wiring) connected to the wiring layer 2j via the via hole 9D. Thus, a two-layer wiring structure can be formed.

Further, by repeating the steps after the formation of a wiring layer (not shown) on the silicon oxide film (3),
It is possible to form a multilayer wiring structure having more than one layer.

This third technique is inferior in controllability of the depth of the wiring groove 8D when the plasma nitride film 32A is not formed in the first embodiment, but other effects are the same. Similarly to the second technique , since an etching stop film such as a plasma nitride film having a large dielectric constant is not used, there is an advantage that the parasitic capacitance between the upper wiring layer (11D) and the lower wiring layer 2j can be reduced.

It goes without saying that, instead of the silicon oxide film (3) used in this embodiment, a fluorine-added silicon oxide film SiOF having a lower dielectric constant and other inorganic insulating films can be used. The SiOF film is formed by mixing NF ₃ with a mixed gas of tetraethylorthosilicate (TEOS) and oxygen.
Can be formed by a plasma CVD method by adding a fluorine-based gas such as

[0050]

The present invention described above, according to the present invention, when forming a via hole for connecting to the bottom portion and the wiring grooves in the interlayer insulating film, a via-hole Le leading to the lower wiring layer is first through the interlayer insulating film filled with organic coating film after formation, then Yes
By forming an upper wiring trench via hole filled with machine coating film can be formed wiring groove without adversely change in shape bi Aho Le previously formed, also using an etching stop layer Since the etching stopper film can be prevented from coming to the side surfaces of the upper trench wiring, there is an effect that the parasitic capacitance between adjacent wirings in the same layer can be reduced.

[Brief description of the drawings]

FIGS. 1A to 1C are cross-sectional views in the order of steps for explaining a technique related to the present invention.

FIG. 2 is a cross-sectional view in the order of steps, which is separated from (a) to (c) following FIG. 1;

FIG. 3 is a cross-sectional view shown after FIG. 2;

FIGS. 4A and 4B are cross-sectional views in the order of steps for explaining the first embodiment of the present invention.

FIG. 5 is a cross-sectional view in the order of steps, which is separated from (a) to (c) following FIG. 4;

FIG. 6 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 5;

FIGS. 7A to 7C are cross-sectional views in the order of steps for explaining a second technique related to the present invention.

FIG. 8 is a sectional view in the order of steps, which is shown separately in FIGS.

FIG. 9 is a sectional view showing a state following FIG. 8;

FIGS. 10A and 10B are cross-sectional views in the order of steps for explaining a third technique related to the present invention , which are shown separately in FIGS.

FIG. 11 is a cross-sectional view in the order of steps, which is separated from (a) to (c) following FIG. 10;

FIG. 12 is a cross-sectional view in the order of steps, which is separated from (a) and (b) following FIG. 11;

13A to 13C are views for explaining a conventional example.
FIG. 4C is a sectional view in the order of steps, which is shown separately in FIG.

FIG. 14 is a sectional view in the order of steps, which is shown separately in FIGS.

[Explanation of symbols]

Reference Signs List 1 insulating film 2i, 2j, 2k wiring layer 3 interlayer insulating film 31, 31A silicon oxide film 32, 32A plasma nitride film 33, 33A silicon oxide film 4, 4a opening 5 photoresist film 6, 6A, 6B, 6C, 6D opening 7, 7A, 7B, 7C, 7D Photoresist film 8, 8A, 8B, 8C, 8D Groove 9, 9A, 9B, 9C, 9D Via hole 10, 10A, 10B, 10C, 10D Metal film 11, 11A, 11B, 11C , 11D buried metal 12, 12A, 12B, 12C Organic coating film 13, 13A, 13B, 13C Opening 14, 14A, 14B, 14C Photoresist film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/28-21/288 H01L 21/3205-21/3213 H01L 21/768

Claims (2)

(57) [Claims] [Claim 1] After selectively covering the first insulating film on a semiconductor substrate to form a plurality of first interconnection layer, a second insulating
Sequentially depositing a film, an etching stopper film and a third insulating film.
Forming an interlayer insulating film Te, the interlayer insulating film to form a first resist film having a first opening which is visual alignment to a predetermined first wiring layer coating, the first resist Anisotropically etching the interlayer insulating film using the film as a mask to form a first via hole connected to the predetermined first wiring layer; and, after peeling the first resist film, forming a first organic film by a coating method. a step of forming a film filling the first via hole, forming the first of the second resist film having a second opening that is visual alignment to the organic film is covering the first via hole, the etching the first organic film and the second resist film as a mask, and subsequently forming a first wiring trench by anisotropically etching the interlayer insulating film to above the etch stop layer, the second resist Membrane and second
Removing the first organic layer, thereby exposing the surface of the predetermined first wiring layer, a step of depositing a first metal film fills the first wiring groove and the first via hole, the first
Removing the metal film from the interlayer insulating film while leaving the metal film in the first wiring groove and the first via hole, thereby embedding a metal as an upper wiring layer connected to the predetermined wiring layer via the first via hole. Forming a semiconductor device. 2. The manufacturing of a semiconductor device according to claim 1 , wherein the second insulating film, the etching stopper film, and the third insulating film are a first silicon oxide film, a plasma nitride film, and a second silicon oxide film, respectively. Method.