JPH10335576A - Structure of semiconductor device having ic chips - Google Patents
Structure of semiconductor device having ic chipsInfo
- Publication number
- JPH10335576A JPH10335576A JP9145095A JP14509597A JPH10335576A JP H10335576 A JPH10335576 A JP H10335576A JP 9145095 A JP9145095 A JP 9145095A JP 14509597 A JP14509597 A JP 14509597A JP H10335576 A JPH10335576 A JP H10335576A
- Authority
- JP
- Japan
- Prior art keywords
- chip
- sub
- main
- semiconductor device
- chips
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 18
- 239000002313 adhesive film Substances 0.000 claims description 13
- 239000000853 adhesive Substances 0.000 claims description 7
- 230000001070 adhesive effect Effects 0.000 claims description 7
- 239000002245 particle Substances 0.000 claims description 7
- 229920003002 synthetic resin Polymers 0.000 claims description 7
- 239000000057 synthetic resin Substances 0.000 claims description 7
- 239000000806 elastomer Substances 0.000 claims description 5
- 229920001971 elastomer Polymers 0.000 claims description 5
- 238000010438 heat treatment Methods 0.000 abstract description 3
- 239000000758 substrate Substances 0.000 abstract 1
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000007789 sealing Methods 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 238000001721 transfer moulding Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
- H01L2224/83101—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、複数個のＩＣチッ
プを、一体的に接合した半導体装置の構造に関するもの
である。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure of a semiconductor device in which a plurality of IC chips are integrally joined.
【０００２】[0002]
【従来の技術と発明が解決しようとする課題】一般に、
半導体装置は、各種の回路素子を形成したＩＣチップ
を、リードフレーム又はプリント基板等に搭載し、この
ＩＣチップにおける各外部接続端子と、リードフレーム
における各リード端子又はプリント基板における配線パ
ターンとの間を、金属ワイヤによるワイヤーボインディ
ングにて接続したのち、これらの全体を合成樹脂製のパ
ッケージにて密封すると言う構成にしていることは周知
の通りである。2. Description of the Related Art In general,
A semiconductor device mounts an IC chip on which various circuit elements are formed on a lead frame or a printed circuit board, etc., and interposes between each external connection terminal on the IC chip and each lead terminal on the lead frame or a wiring pattern on the printed circuit board. Is connected by wire binding with a metal wire, and the entirety is sealed with a package made of synthetic resin, as is well known.
【０００３】従って、この従来の半導体装置において、
そのＩＣチップにおける回路素子の数を多くするには、
当該ＩＣチップの横幅及び長さ寸法を大きくするか、複
数個のＩＣチップを横に並べた形態にしなければなら
ず、半導体装置における横幅及び長さ寸法が大きくなる
から、この半導体装置をプリント基板に装着したときに
大きい占有領域を必要することになるから、プリント基
板に対する各種電子部品の実装密度が低下し、プリント
基板の大型化、ひいては、電気機器の大型化を招来する
と言う問題があった。Therefore, in this conventional semiconductor device,
To increase the number of circuit elements in the IC chip,
Since the width and length of the IC chip must be increased or a plurality of IC chips must be arranged side by side, the width and length of the semiconductor device are increased. Since a large occupied area is required when mounted on a printed circuit board, there is a problem that the mounting density of various electronic components on the printed circuit board is reduced, and the printed circuit board is increased in size and, consequently, the electric equipment is increased in size. .
【０００４】本発明は、この問題を、複数のＩＣチップ
を使用して解消した半導体装置の構造を提供することを
技術的課題とするものである。An object of the present invention is to provide a structure of a semiconductor device which solves this problem by using a plurality of IC chips.
【０００５】[0005]
【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「少なくとも上面に回路素子を形成し
たメインＩＣチップと、少なくとも片面に回路素子を形
成して成る一つのサブＩＣチップとから成り、前記サブ
ＩＣチップを、前記メインＩＣチップの上面側に、当該
サブＩＣチップの片面における回路素子が前記メインＩ
Ｃチップにおける回路素子に対面するよう下向きにして
配設し、このサブＩＣチップの下面に形成した各電極パ
ッドと、前記メインＩＣチップの上面に形成した各電極
パッドとを、これら両電極パッドの各々に設けたバンプ
を介して接合する。」と言う構成にした。In order to achieve this technical object, the present invention provides a main IC chip having circuit elements formed on at least an upper surface and a sub IC chip having circuit elements formed on at least one side. The sub IC chip is placed on the upper surface side of the main IC chip, and the circuit element on one side of the sub IC chip is attached to the main IC chip.
The respective electrode pads formed on the lower surface of the sub IC chip and the respective electrode pads formed on the upper surface of the main IC chip are arranged downward so as to face the circuit elements of the C chip. Bonding is performed via the bumps provided for each. ".
【０００６】[0006]
【発明の作用・効果】このように構成したことにより、
半導体装置を、メインＩＣチップの上面に、サブＩＣチ
ップを重ね合わせた形態にすることができるから、半導
体装置における回路素子の数を、当該半導体装置におけ
る横幅及び長さ寸法を大きくすることなく、多くするこ
とができるのである。Operation and effect of the present invention
Since the semiconductor device can be formed by superimposing a sub IC chip on the upper surface of a main IC chip, the number of circuit elements in the semiconductor device can be reduced without increasing the width and length of the semiconductor device. You can do much.
【０００７】従って、半導体装置における高さ寸法が、
メインＩＣチップの上面にサブＩＣチップを重ねる分だ
け高くなるものの、この半導体装置をプリント基板等に
装着したときにおける占有面積を大幅に縮小できるか
ら、プリント基板等の小型化、ひいては、電気機器の小
型化を図ることができるのである。しかも、前記メイン
ＩＣチップにおける回路素子と、その上面に配設したサ
ブＩＣチップにおける回路素子が互いに対面すると言う
形態にすることに加えて、サブＩＣチップの下面に形成
した各電極パッドと、メインＩＣチップの上面に形成し
た各電極パッドとを、これら両電極パッドの各々に設け
たバンプを介して接合すると言う構成にしたことによ
り、両ＩＣチップにおける回路素子を、両ＩＣチップの
各々にて確実に保護することができると共に、両ＩＣチ
ップの接合に際して、サブＩＣチップの各電極パッドに
おけるバンプと、メインＩＣチップの各電極パッドにお
けるバンプとが互いに接当して、この部分に接合力を集
中することができるから、両ＩＣチップの相互間を電気
的に接続することが確実に達成できるのである。Therefore, the height dimension of the semiconductor device is
Although the height is increased by the amount of the sub IC chip on the upper surface of the main IC chip, the occupied area when this semiconductor device is mounted on a printed circuit board or the like can be greatly reduced. The size can be reduced. Further, in addition to the configuration in which the circuit elements in the main IC chip and the circuit elements in the sub IC chip disposed on the upper surface face each other, each of the electrode pads formed on the lower surface of the sub IC chip, Each of the electrode pads formed on the upper surface of the IC chip is joined to the corresponding electrode pad via a bump provided on each of the two electrode pads. In addition to being able to reliably protect, the bumps on each electrode pad of the sub IC chip and the bumps on each electrode pad of the main IC chip are in contact with each other when joining both IC chips, and the joining force is applied to this portion. Since concentration can be performed, electrical connection between the two IC chips can be reliably achieved.
【０００８】また、「請求項２」に記載したように、メ
インＩＣチップの上面と、前記サブＩＣチップの下面と
の間に、接着剤又はエラストマーを充填すると言う構成
にすることにより、メインＩＣチップとサブＩＣチップ
とを、その間に充填した合成樹脂の接着剤又はエラスト
マーにて強固に一体化できると共に、その各々における
回路素子の保護を、その間に充填にした合成樹脂の接着
剤又はエラストマーにて一層向上できる利点がある。According to a second aspect of the present invention, an adhesive or an elastomer is filled between the upper surface of the main IC chip and the lower surface of the sub IC chip. The chip and the sub IC chip can be firmly integrated with the synthetic resin adhesive or elastomer filled therebetween, and the protection of the circuit elements in each of them can be protected by the synthetic resin adhesive or elastomer filled between them. There is an advantage that can be further improved.
【０００９】更にまた、「請求項３」に記載したよう
に、メインＩＣチップの上面と、前記サブＩＣチップの
下面との間に、導電粒子を混入した接着フィルムを介挿
したことにより、両ＩＣチップの一体化と回路素子の保
護とを前記接着フィルムにて達成できる一方、この接着
フィルムにおける導電粒子が、両ＩＣチップにおけるバ
ンプの相互間に挟まれて、その間を電気的に接続するこ
とになるから、両ＩＣチップの相互間における電気的な
接続の確実性を更に助長できるのである。Further, as described in the third aspect, an adhesive film containing conductive particles is interposed between the upper surface of the main IC chip and the lower surface of the sub IC chip. While the integration of the IC chip and the protection of the circuit element can be achieved by the adhesive film, the conductive particles in the adhesive film are sandwiched between the bumps of the two IC chips and electrically connected therebetween. Therefore, the reliability of the electrical connection between the two IC chips can be further promoted.
【００１０】[0010]
【発明の実施の形態】以下、本発明の実施の形態を図面
について説明する。図１〜図６は、第１の実施形態を示
す。この図において符号１は、矩形状のチップマウント
部１ａと、このチップマウント部１ａにおける四つの各
辺から外向きに延びる複数本のリード端子１ｂとを備え
たリードフレームを示す。Embodiments of the present invention will be described below with reference to the drawings. 1 to 6 show a first embodiment. In this drawing, reference numeral 1 denotes a lead frame including a rectangular chip mount 1a and a plurality of lead terminals 1b extending outward from four sides of the chip mount 1a.
【００１１】また、符号２は、前記リードフレーム１に
おけるチップマウント部１ａの上面にマウントされるメ
インＩＣチップを示し、このメインＩＣチップ２の上面
には、図示しない能動素子又は受動素子等のような回路
素子の多数個が形成されていると共に、その周囲にワイ
ヤボンディング用パッド２ｃの多数個が、その内側に後
述するサブＩＣチップ３に対する接続用の電極パッド２
ａの多数個が各々形成されている。Reference numeral 2 denotes a main IC chip mounted on the upper surface of the chip mounting portion 1a of the lead frame 1. The upper surface of the main IC chip 2 is provided with an active element or a passive element (not shown). And a plurality of wire bonding pads 2c around which a plurality of electrode pads 2 for connection to a sub IC chip 3 described later are formed.
a are formed respectively.
【００１２】更にまた、符号３は、前記メインＩＣチッ
プ２の上面にマウントされるサブＩＣチップを示し、こ
のサブＩＣチップ３における表裏両面のうち片面には、
前記メインＩＣチップ２と同様に図示しない能動素子又
は受動素子等のような回路素子の多数個が形成されてい
ると共に、前記メインＩＣチップ２の上面における各電
極パッド２ｂの各々に対応する箇所ごとに接続用の電極
パッド３ａが形成されている。Reference numeral 3 denotes a sub IC chip mounted on the upper surface of the main IC chip 2. One of the front and back surfaces of the sub IC chip 3 has
Similarly to the main IC chip 2, a large number of circuit elements such as active elements or passive elements (not shown) are formed, and each portion corresponding to each of the electrode pads 2 b on the upper surface of the main IC chip 2. Are formed with connection electrode pads 3a.
【００１３】そして、前記メインＩＣチップ２における
各電極パッド２ａ、及び前記サブＩＣチップ３における
各電極パッド３ａの各々に、金又は半田によるパンプ２
ｂ，３ｂを設ける一方、前記サブＩＣチップ３を、図３
に示すように、その回路素子及び電極パッド３ａを形成
した面を下向きにして、前記メインＩＣチップ２の上面
側に、当該サブＩＣチップ３の各電極パッド３ａにおけ
るバンプ３ｂの各々が、メインＩＣチップ２の各電極バ
ンプ２ｂにおけるバンプ２ｂの各々に接当するように載
置したのち、全体を加熱しながら、サブＩＣチップ３を
メインＩＣチップ２に対して押圧（この押圧と同時に超
音波を振動を付与しても良い）することにより、互いに
接当するバンプ２ｂ，３ｂの部分に押圧力が集中するか
ら、互いに接当するバンプ２ｂ，３ｂを確実に電気的に
接合することができる。Each of the electrode pads 2a of the main IC chip 2 and each of the electrode pads 3a of the sub IC chip 3 is provided with a pump 2 made of gold or solder.
b, 3b, while the sub IC chip 3 is
As shown in FIG. 5, the bumps 3b of the respective electrode pads 3a of the sub IC chip 3 are provided on the upper surface of the main IC chip 2 with the surface on which the circuit elements and the electrode pads 3a are formed facing downward. After placing the bumps 2b on each of the electrode bumps 2b of the chip 2 so as to be in contact with the bumps 2b, the sub IC chip 3 is pressed against the main IC chip 2 while heating the whole (ultrasonic wave is applied simultaneously with the pressing) By applying vibration, the pressing force concentrates on the bumps 2b and 3b that come into contact with each other, so that the bumps 2b and 3b that come into contact with each other can be reliably electrically connected.
【００１４】次いで、前記メインＩＣチップ２の上面
と、前記サブＩＣチップ３の下面との間の隙間に、エポ
キシ樹脂等の合成樹脂による接着剤４又はエラストマー
を充填したのち、これらの全体を、図４に示すように、
前記リードフレーム１におけるチップマウント部１ａの
上面に、前記メインＩＣチップ２を接着剤等にて固着す
るようにしてマウントする。Next, the gap between the upper surface of the main IC chip 2 and the lower surface of the sub IC chip 3 is filled with an adhesive 4 or an elastomer made of a synthetic resin such as an epoxy resin. As shown in FIG.
The main IC chip 2 is mounted on the upper surface of the chip mount section 1a of the lead frame 1 so as to be fixed with an adhesive or the like.
【００１５】次いで、前記メインＩＣチップ２の上面に
おける各ワイヤボンディング用パッド２ｃと、リードフ
レーム１における各リード端子１ｂとの間を、細い金属
線５によるワイヤボンディングにて電気的に接続する。
そして、図５に示すように、全体を密封する合成樹脂製
のパッケージ部６を、トランスファ成形によって成形す
る。次いで、図６に示すように、リードフレーム１から
切り放したのち、各リード端子１ｂのうちパッケージ部
６から突出する部分を、パッケージ部６の下面と略同一
平面状になるように折り曲げすることにより、完成品と
するのである。Next, each wire bonding pad 2c on the upper surface of the main IC chip 2 and each lead terminal 1b on the lead frame 1 are electrically connected by a thin metal wire 5 by wire bonding.
Then, as shown in FIG. 5, the package part 6 made of synthetic resin for sealing the whole is formed by transfer molding. Next, as shown in FIG. 6, after being cut off from the lead frame 1, a portion of each lead terminal 1 b projecting from the package portion 6 is bent so as to be substantially flush with the lower surface of the package portion 6. , And make it a finished product.
【００１６】次に、図７及び図８は、第２の実施形態を
示す。この第２の実施形態は、メインＩＣチップ２の上
面にサブＩＣチップ３をマウントすることに、導電粒子
を混入した接着フィルム７を使用した場合である。すな
わち、この接着フィルム７を、前記メインＩＣチップ２
とサブＩＣチップ３との間に介挿したのち、サブＩＣチ
ップ３を、メインＩＣチップ２に向かって、その間の接
着フィルム７を圧縮変形するように押圧し、この押圧を
保持した状態で、加熱等にて前記接着フィルム７を乾燥
・硬化することにより、サブＩＣチップ３を、メインＩ
Ｃチップ２に対してマウントするのである。Next, FIGS. 7 and 8 show a second embodiment. In the second embodiment, the sub IC chip 3 is mounted on the upper surface of the main IC chip 2 using an adhesive film 7 mixed with conductive particles. That is, the adhesive film 7 is used as the main IC chip 2
After being inserted between the sub IC chip 3 and the sub IC chip 3, the sub IC chip 3 is pressed toward the main IC chip 2 so that the adhesive film 7 therebetween is compressed and deformed. By drying and curing the adhesive film 7 by heating or the like, the sub IC chip 3 is
It is mounted on the C chip 2.
【００１７】前記したサブＩＣチップ３のメインＩＣチ
ップ２に向う押圧により、前記メインＩＣチップ２にお
ける各バンプ２ｂ及びサブＩＣチップ３における各バン
プ３ｂの両方が、前記接着フィルム７の中に食い込むこ
とにより、この接着フィルム７に混入した導電粒子が、
当該両バンプ２ｂ，３ｂの相互間にに挟まれ、この導電
粒子を介して両バンプ２ｂ，３ｂが互いに電気的に接続
されることになるのである。The above-mentioned pressing of the sub IC chip 3 toward the main IC chip 2 causes both the bumps 2 b of the main IC chip 2 and the bumps 3 b of the sub IC chip 3 to bite into the adhesive film 7. As a result, the conductive particles mixed into the adhesive film 7
The bumps 2b and 3b are sandwiched between the bumps 2b and 3b, and the bumps 2b and 3b are electrically connected to each other via the conductive particles.
【００１８】すなわち、この第２の実施形態によると、
サブＩＣチップ３を、メインＩＣチップ２に対して、そ
の間に導電粒子を混入した接着フィルム７を介挿した状
態で押圧し、この押圧したままで前記接着フィルム７を
乾燥・硬化するだけで、電気的な接続とマウントとが同
時にできるから、これに要するコストを、前記第１の実
施形態の場合よりも低減できるのである。That is, according to the second embodiment,
The sub IC chip 3 is pressed against the main IC chip 2 with the adhesive film 7 mixed with conductive particles interposed therebetween, and the adhesive film 7 is dried and cured while keeping the pressing, Since the electrical connection and the mounting can be performed at the same time, the cost required for this can be reduced as compared with the case of the first embodiment.
【００１９】また、前記した実施の形態は、サブＩＣチ
ップ３をマウントしたメインＩＣチップ２を、リードフ
レーム１に対してマウントして半導体装置を構成する場
合であったが、本発明は、これに限らず、サブＩＣチッ
プ３をマウントしたメインＩＣチップ２を、プリント基
板に対してマウントして半導体装置を構成する場合にも
適用できることは言うまでなく、更には、メインＩＣチ
ップ２にマウントするサブＩＣチップ３は、一個に限ら
ず、複数個のサブＩＣチップを横に並べてマウントする
ようにしても良いのである。In the embodiment described above, the main IC chip 2 on which the sub IC chip 3 is mounted is mounted on the lead frame 1 to form a semiconductor device. The present invention is not limited to this, and it goes without saying that the present invention can be applied to a case where the main IC chip 2 on which the sub IC chip 3 is mounted is mounted on a printed circuit board to form a semiconductor device. The number of sub IC chips 3 is not limited to one, and a plurality of sub IC chips may be mounted side by side.
【図１】第１の実施形態を示す分解斜視図である。FIG. 1 is an exploded perspective view showing a first embodiment.
【図２】図１の縦断正面図である。FIG. 2 is a vertical sectional front view of FIG.
【図３】第１の実施形態においてメインＩＣチップにサ
ブＩＣチップをマウントした状態を示す縦断正面図であ
る。FIG. 3 is a longitudinal sectional front view showing a state where a sub IC chip is mounted on a main IC chip in the first embodiment.
【図４】第１の実施形態においてサブＩＣチップをマウ
ントしたメインＩＣチップをリードフレームに対してマ
ウントした状態を示す縦断正面図である。FIG. 4 is a longitudinal sectional front view showing a state in which a main IC chip on which a sub IC chip is mounted in the first embodiment is mounted on a lead frame;
【図５】第１の実施形態において全体を密封するパッケ
ージ部を成形した状態を示す縦断正面図である。FIG. 5 is a longitudinal sectional front view showing a state in which a package portion for sealing the whole is molded in the first embodiment.
【図６】第１の実施形態における半導体装置の縦断正面
図である。FIG. 6 is a vertical sectional front view of the semiconductor device according to the first embodiment.
【図７】第２の実施形態において分解した状態を示す縦
断正面図である。FIG. 7 is a longitudinal sectional front view showing a disassembled state in the second embodiment.
【図８】第２の実施形態においてメインＩＣチップにサ
ブＩＣチップをマウントした状態を示す縦断正面図であ
る。FIG. 8 is a longitudinal sectional front view showing a state where a sub IC chip is mounted on a main IC chip in the second embodiment.
１ リードフレーム １ａ チップマウント部 １ｂ リード端子 ２ メインＩＣチップ ２ａ 電極パッド ２ｂ バンプ ３ サブＩＣチップ ３ａ 電極パッド ３ｂ バンプ ４ 合成樹脂の接着剤 ５ 金属線 ６ パッケージ部 ７ 接着フィルム DESCRIPTION OF SYMBOLS 1 Lead frame 1a Chip mount part 1b Lead terminal 2 Main IC chip 2a Electrode pad 2b Bump 3 Sub IC chip 3a Electrode pad 3b bump 4 Synthetic resin adhesive 5 Metal wire 6 Package part 7 Adhesive film
Claims (3)
ンＩＣチップと、少なくとも片面に回路素子を形成して
成る一つのサブＩＣチップとから成り、前記サブＩＣチ
ップを、前記メインＩＣチップの上面側に、当該サブＩ
Ｃチップの片面における回路素子が前記メインＩＣチッ
プにおける回路素子に対面するよう下向きにして配設
し、このサブＩＣチップの下面に形成した各電極パッド
と、前記メインＩＣチップの上面に形成した各電極パッ
ドとを、これら両電極パッドの各々に設けたバンプを介
して接合したことを特徴とする複数のＩＣチップを備え
た半導体装置の構造。1. A main IC chip having a circuit element formed on at least an upper surface thereof and one sub IC chip having a circuit element formed on at least one side, wherein the sub IC chip is formed on the upper surface side of the main IC chip. The sub-I
The circuit elements on one side of the C chip are disposed facing downward so as to face the circuit elements on the main IC chip, and each electrode pad formed on the lower surface of this sub IC chip and each electrode pad formed on the upper surface of the main IC chip A structure of a semiconductor device comprising a plurality of IC chips, wherein the electrode pads are joined via bumps provided on each of the two electrode pads.
Ｃチップの上面と、前記サブＩＣチップの下面との間
に、合成樹脂の接着剤又はエラストマーを充填したこと
を特徴とする複数のＩＣチップを備えた半導体装置の構
造。2. The method according to claim 1, wherein the main I
A structure of a semiconductor device comprising a plurality of IC chips, wherein an adhesive or an elastomer of a synthetic resin is filled between an upper surface of a C chip and a lower surface of the sub IC chip.
Ｃチップの上面と、前記サブＩＣチップの下面との間
に、導電粒子を混入した接着フィルムを介挿したことを
特徴とする複数のＩＣチップを備えた半導体装置の構
造。3. The method according to claim 1, wherein the main I
A structure of a semiconductor device comprising a plurality of IC chips, wherein an adhesive film containing conductive particles is interposed between an upper surface of the C chip and a lower surface of the sub IC chip.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14509597A JP3543253B2 (en) | 1997-06-03 | 1997-06-03 | Structure of a semiconductor device having a plurality of IC chips |
| PCT/JP1998/000281 WO1998033217A1 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
| KR10-1998-0707403A KR100522223B1 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
| EP98900725A EP0890989A4 (en) | 1997-01-24 | 1998-01-22 | Semiconductor device and method for manufacturing thereof |
| US09/155,134 US6133637A (en) | 1997-01-24 | 1998-01-22 | Semiconductor device having a plurality of semiconductor chips |
| KR10-2004-7000090A KR100467946B1 (en) | 1997-01-24 | 1998-01-22 | Method for manufacturing a semiconductor chip |
| US09/612,480 US6458609B1 (en) | 1997-01-24 | 2000-07-07 | Semiconductor device and method for manufacturing thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14509597A JP3543253B2 (en) | 1997-06-03 | 1997-06-03 | Structure of a semiconductor device having a plurality of IC chips |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10335576A true JPH10335576A (en) | 1998-12-18 |
| JP3543253B2 JP3543253B2 (en) | 2004-07-14 |
Family
ID=15377266
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14509597A Expired - Fee Related JP3543253B2 (en) | 1997-01-24 | 1997-06-03 | Structure of a semiconductor device having a plurality of IC chips |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3543253B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635969B1 (en) | 1999-02-23 | 2003-10-21 | Rohm Co., Ltd. | Semiconductor device having chip-on-chip structure, and semiconductor chip used therefor |
| JPWO2008054012A1 (en) * | 2006-10-31 | 2010-02-25 | 住友ベークライト株式会社 | Adhesive tape and semiconductor device using the same |
| WO2012107972A1 (en) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | Semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102190382B1 (en) | 2012-12-20 | 2020-12-11 | 삼성전자주식회사 | Semiconductor package |
-
1997
- 1997-06-03 JP JP14509597A patent/JP3543253B2/en not_active Expired - Fee Related
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6635969B1 (en) | 1999-02-23 | 2003-10-21 | Rohm Co., Ltd. | Semiconductor device having chip-on-chip structure, and semiconductor chip used therefor |
| JPWO2008054012A1 (en) * | 2006-10-31 | 2010-02-25 | 住友ベークライト株式会社 | Adhesive tape and semiconductor device using the same |
| WO2012107972A1 (en) * | 2011-02-10 | 2012-08-16 | パナソニック株式会社 | Semiconductor device |
| US8866284B2 (en) | 2011-02-10 | 2014-10-21 | Panasonic Corporation | Semiconductor device comprising an extended semiconductor chip having an extension |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3543253B2 (en) | 2004-07-14 |
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