KR100788341B1 - Chip Stacked Semiconductor Packages - Google Patents

Abstract

The present invention provides a chip stacked semiconductor package having excellent workability by stacking a plurality of chips but occupying a minimum area and volume using a flexible circuit film and conveniently stacking chips.

The present invention provides a plurality of semiconductor chips; A circuit film electrically connected to a connection pad of the chip and having a circuit patterned thereon; An encapsulant for encapsulating a connection portion between the chip and the circuit film, wherein the circuit film is continuously connected to a plurality of chips and provides a chip stacked semiconductor package in which the circuit film is bent to stack the chips.

Circuit Film, Flexible, Chip Lamination

Description

Chip Stacked Semiconductor Package

1 is a schematic cross-sectional view of a conventional chip stacked semiconductor package.

Figure 2 is a view showing an embodiment of a chip stacked semiconductor package according to the present invention, a side view showing a state in which the circuit film unfolded before stacking the chips.

3 is an enlarged cross-sectional view of the chip assembly of FIG. 2.

FIG. 4 is a cross-sectional view of a chip assembly including an external lead terminal located at a lower end of the chip stacked semiconductor package of FIG. 2.

5 is a cross-sectional view showing a completed form of a chip stacked semiconductor package according to the present invention.

6 and 7 are schematic side and sectional views showing a second embodiment of a chip stacked semiconductor package according to the present invention;

8 and 9 are schematic side and sectional views showing a third embodiment of a chip stacked semiconductor package according to the present invention;

Figure 10a is a cross-sectional view showing another embodiment of the individual chip assembly in the chip stacked semiconductor package according to the present invention.

FIG. 10B is a top view of a portion of a state before encapsulating the embodiment of FIG. 10A. FIG.

11 is a top view showing still another embodiment of the chip stacked semiconductor package according to the present invention.

** Explanation of symbols for main parts of drawings **

5: bonding means 6,6a to 6f: semiconductor chip

62: center pad 64: side pad

7: encapsulant 9: wire

10,100: circuit film 12: lead

14: hall

The present invention relates to a semiconductor package, and more particularly, to a chip stacked semiconductor package in which a plurality of semiconductor chips are stacked vertically.

In general, packaging technology for integrated circuits in the semiconductor industry continues to evolve to increase memory capacity while satisfying the demand for miniaturization and mounting reliability.

In other words, the demand for miniaturization is accelerating the development of packages close to the chip scale, and the demand for mounting reliability emphasizes the importance of package manufacturing technology that can improve the efficiency of mounting work and the mechanical and electrical reliability after mounting. In addition, the development and importance of stacked package manufacturing technology for increasing memory capacity is also emerging.                         

1 is a cross-sectional view illustrating a schematic form of a conventional chip stacked semiconductor package.

Referring to the drawings, a conventional chip stack semiconductor package includes a lead 2 consisting of an outlead 2a and an inner lead 2b, a chip pad 4 on which a semiconductor chip is stacked, and a first semiconductor chip 6. And a second semiconductor chip 8 stacked on the first semiconductor chip 6, and an encapsulant 7 which encapsulates and protects the above-mentioned components at a glance.

In more detail, the first semiconductor chip 6 is deposited on the central chip pad 4, and the conductive wire 9 is connected between the connection pad 6a and the inner lead 2a on the surface of the first semiconductor chip 6. Bonded

The second semiconductor chip 8 is stacked on the first semiconductor chip 6, and the second semiconductor chip 8 is somewhat smaller in size than the first semiconductor chip 6. The size of the second semiconductor chip 8 is smaller than that of the first semiconductor chip 6 in order to secure an area of the connection pad 6a in which the wire 9 is bonded in the first semiconductor chip 6.

As described above, in the state where the second semiconductor chip 8 is stacked, the wire 9 is bonded between the connection pad 8a and the inner lead 2b of the second semiconductor chip 8 again.

In the chip stack package having the above-described configuration, the thickness of the semiconductor package is increased in order to secure the wire loop, and since the first semiconductor chip 6 and the second semiconductor chip 8 must be wire bonded, the chips of the same size There is a problem that is not easy to stack the.

In addition, in the conventional method, it is also difficult to stack more than two semiconductor chips.

The present invention has been made in order to solve the above problems of the prior art, a stack of a plurality of chips, but using a flexible circuit film occupies the minimum area and volume, and conveniently stacks the chip excellent chip workability It is an object to provide a stacked semiconductor package.

The present invention provides a plurality of semiconductor chips having an integrated circuit to achieve the above object; A circuit film of a flexible material in which a circuit for connecting each chip is electrically connected to a connection pad of the chip; An encapsulant for encapsulating a connection portion to which the chip and the circuit film are connected; wherein the circuit film is continuously connected between the plurality of chips, and the chips are bent to be interviewed with each other by bending the circuit film. A chip stacked semiconductor package is provided. .

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The structure of this invention is demonstrated in detail, referring an accompanying drawing. For reference, prior to describing the configuration of the present invention, in order to avoid duplication of description of the prior art reference will be referred to the same reference numerals.

FIG. 2 is a cross-sectional view showing a preferred embodiment of a chip stacked semiconductor package according to the present invention, showing a state before stacking semiconductor chips, and FIG. 3 is an enlarged cross-sectional view of an individual chip assembly in FIG.

Referring to FIG. 2, the chip stacked semiconductor package according to the present invention has a structure in which semiconductor chips 6 spaced apart from each other in a continuous circuit film 10 are attached to the center before being stacked. For reference, for convenience of description, the same chips are described, respectively, divided into (6a), (6b), (6c), (6d), (6e), and (6f).

The semiconductor chips 6a... 6f are respectively attached to one surface of the circuit film 10, and the chip attaching surface is selected from one surface and the other surface of the circuit film 10, but is attached to the same surface. Bonding means for bonding the encapsulant 7 encapsulating the bonding portion and the chip 6 and the chip 6 when wire bonding not only a semiconductor chip but also a chip pad and a circuit film to each semiconductor chip assembly; It is provided with the bar details will be described later with reference to FIG.

The circuit film 10 is a circuit pattern on the film, and has a characteristic that can be bent (flexible). The encapsulant 7 generally uses EMC (Epoxy Mold Compound). In the present invention, it is preferable to use an encapsulation material that is cured by applying a syringe or the like in a liquid or paste state.

The adhering means 5 is a kind of general advice to bond the encapsulant 7 and the encapsulant 7 or the chip and the chip.

Since the chip package shown on the right side is mounted on the motherboard at the bottom of the stack, the solder ball 32 serving as a connection terminal is attached to the drawing.

Hereinafter, with reference to the cross-sectional view of Figure 3 will be described in more detail the chip package portion constituting the sub-unit of the chip stacked semiconductor package of the present invention.                     

FIG. 3 is a view illustrating a chip package part F stacked on an uppermost side in FIG. 2, and as shown in the drawing, a circuit film 10 is attached to a surface of a semiconductor chip 6f. ) Is preferably flexible, such as FPC (Flexible PCB). When the circuit film 10 is attached to the surface of the semiconductor chip 6f, the circuit film 10 is attached with the connection pad 62 of the semiconductor chip 6f exposed.

The semiconductor chip 6f is a chip in which a connection pad is formed in the center, that is, provided with a center pad as shown in the drawing. The connecting pads 62 of the semiconductor chip 6f and the leads 12 of the circuit film 10 are connected by wire 9 bonding. The wire 9 generally uses gold, aluminum, or copper wire having excellent conductivity, and improves connection force between the connection pad 62 of the semiconductor chip and the lead 12 of the circuit film.

In the present embodiment, a semiconductor chip having a center pad is used, but a semiconductor chip having a side pad may be applied, and a package to which the semiconductor chip having the side pad is applied will be described later.

When the connection pad 62 and the wire 9 of the semiconductor chip 6f are exposed, the connection pad 62 and the wire 9 are easily damaged by oxidation and the like, and thus are susceptible to external impact. The encapsulant 7 generally uses a thermosetting encapsulant, and preferably uses an encapsulant 7 in the form of an epoxy mold compound or a paste.

An adhesive means 5 is applied to the back surface of the semiconductor chip or the top surface of the encapsulant. The adhesive means may be cured by attaching a film type or may be injected from a syringe in liquid or paste form.                     

FIG. 4 is an enlarged cross-sectional view of the chip package portion A illustrated at the right end of FIG. 2 and constituting the lower end portion of the chip stacked semiconductor package of the present invention. The example shown for reference is shown opposite to the direction in which the motherboard is mounted.

As shown in the figure, a circuit film 10 is attached to the surface on which the connection pad 62 of the semiconductor chip 6a is formed, and the connection pad part 62 is exposed to expose the wire 9 to the circuit film 10. Bonded As illustrated, the chip package portion A is located at the lower end of the chip stacked semiconductor package, and thus requires a lead terminal when mounted on the motherboard.

To this end, an external drawing terminal 30 for transmitting an electrical signal of the semiconductor chip to the outside is provided on a surface opposite to the surface to which the semiconductor chip is attached in the circuit film. As the external drawing terminal 30, a conductive metal material is used, and in this embodiment, a solder ball 32 is used.

The solder ball 32 is connected to the end of each lead wire 12 formed in the circuit film 10 and is fusion-spliced to the connection pad (not shown) of the motherboard when mounted on the motherboard.

In FIG. 3, most of the circuit film 10 is encapsulated to protect the connection pad 62 and the wire 9 of the chip. However, in this embodiment, the wire 9 is secured to secure an area to which the solder ball 32 is attached. ) Only the smallest part was sealed.

FIG. 5 is a cross-sectional view illustrating a structure in which each semiconductor chip is stacked as the present invention intends while the circuit film 10 is unfolded as shown in FIG. 2.

A process of stacking semiconductor chips will be described with reference to FIG. 2. First, the circuit film 10 is bent so that the rear surface of the first chip 6a and the rear surface of the second chip 6b come into contact with each other. The first chip 6a and the second chip 6b are adhered to each other with the adhesive 5 applied on the back surface of the sheet.

Thereafter, the second chip 6b is bent with the adhesive 5 applied to the top surface of the encapsulant 7 of the third chip 6c by bending the circuit film 10 connected to the third chip 6c and the second chip 6b. Contact with the top surface of the encapsulant (7). In this manner, the back surface of the fourth chip 6d and the back surface of the third chip 6c are adhered to each other, and the encapsulant 7 of the fifth chip 6e and the encapsulant 7 of the fourth chip 6d are attached. And the back surface of the sixth chip 6f and the back surface of the fifth chip 6e.

By stacking the chips one by one using the adhesive 5 in the above-described manner, the structure shown in FIG. 5 is achieved. Each semiconductor chip is connected to a continuous circuit film so that the maximum number of chips can be stacked with a minimum vertical height.

FIG. 6 is a schematic side view illustrating a second embodiment of a chip stacked semiconductor package according to the present invention, and FIG. 7 is a cross-sectional view illustrating a stacked state of each of the chips arranged as shown in FIG. 6.

As shown in FIG. 6, the semiconductor package is formed by stacking two semiconductor chips 6 so as to face each other, and then stacking the two stacked chips as a unit and again in the unit unit.

As can be seen in the stacked state of FIG. 7, two chips facing each other become a unit so that each unit is stacked again, so that chips are more easily stacked, and as shown in FIG. 5, a chip stacked semiconductor package can be implemented with a minimum thickness. do.

8 and 9 illustrate a third embodiment of the present invention, as shown in FIG. 8, each of the semiconductor chips 6 is not bonded to each other so that the chips are opposed to each other, and the circuit film 10 only in the direction of the arrow. ) Only bent to stack on top of adjacent chips in the same shape.

As a result, as illustrated in FIG. 9, the semiconductor chips may be continuously stacked such that the encapsulation portion 7 is positioned in one direction.

10A and 10B are cross-sectional views illustrating another embodiment of the chip stacked semiconductor package according to the present invention.

2 to 9 illustrate a structure in which chips are stacked by using a chip having a center pad.

FIG. 10A shows a portion of the chip package portion attached to the continuous circuit film, in which a connection pad 64 of the semiconductor chip 6 is formed at the edge of the chip. The semiconductor chip 6 having the side pads 64 as described above forms a shape in which the wires 9 are bonded to the outer side of the chip and encapsulates the upper surface of the chip including the wire bonding portion.

FIG. 10B is a top view illustrating a state before sealing with the encapsulant 7 in the chip package shown in FIG. 10A.

As shown in the figure, holes 14 are formed in slots around the circuit film 10, and the holes 14 expose the connection pads 64 of the semiconductor chip 6. The exposed connection pads 64 and the bonding pads of the circuit film 10 are bonded to each other by a conductive wire 9, and the circuit film 10 may be connected to a lead 12 serving as a bus to the center and the side. The electrical signal between each chip can be transmitted to the center and the side lead (12).

As described above, the circuit film 10 is widely configured to form the holes 14, and the connection pads 64 of the chip 6 are wire-bonded at the holes, and the buses are moved toward the center and side of the circuit film 10. By providing the line 12, it becomes possible to employ a chip with the side pads 64.

FIG. 11 is a view showing another embodiment of a chip stacked semiconductor package according to the present invention, and is a top view showing a top view before encapsulating the wire bonding portion between the circuit film and the chip with an encapsulant.

In the circuit film 100 shown in FIG. 11, it can be seen that the semiconductor chips 6 are arranged in two rows while having a width twice that of the circuit film 10 shown in FIG. 6B. This arrangement allows two chips to be arranged horizontally and multiple chips stacked vertically.

In addition, it is possible to easily configure a chip stacked semiconductor package of three rows, four rows or more.

Of course, the semiconductor chips used in the above embodiments preferably have the same size and the same function, but it is also possible to stack chips of different sizes by appropriately designing the circuit of the circuit film.

By connecting chips stacked using a flexible bending circuit film, an existing package manufacturing process can be applied, and the number of chips stacked horizontally or vertically can be limited.

In particular, when packaging chips having the same function and capacity, a significant capacity increase and a function improvement effect can be expected.

Claims (5)

A plurality of semiconductor chips having integrated circuits; A circuit film of a flexible material in which a circuit for connecting each chip is electrically connected to a connection pad of the chip; And an encapsulation material encapsulating a connection portion to which the chip and the circuit film are connected. And the circuit film is continuously connected between the plurality of chips, and each chip is laminated to be in contact with each other by bending the circuit film. The method of claim 1, The circuit film is a chip laminated semiconductor package, characterized in that the FPCB (Flexible PCB). The method of claim 1, And the semiconductor chips are the same size. The method according to claim 1 or 2, The circuit film is a chip laminated semiconductor package, characterized in that the semiconductor chip is provided with two or more rows. The method of claim 1, When the semiconductor chip is stacked, the chip and chip, the encapsulant and the encapsulant, or the chip and the encapsulant are bonded by an adhesive means.

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