JPH10326949A - Circuit board - Google Patents
Circuit boardInfo
- Publication number
- JPH10326949A JPH10326949A JP13470797A JP13470797A JPH10326949A JP H10326949 A JPH10326949 A JP H10326949A JP 13470797 A JP13470797 A JP 13470797A JP 13470797 A JP13470797 A JP 13470797A JP H10326949 A JPH10326949 A JP H10326949A
- Authority
- JP
- Japan
- Prior art keywords
- metal
- metal circuit
- bonding layer
- circuit
- insulation resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 229910052751 metal Inorganic materials 0.000 claims abstract description 93
- 239000002184 metal Substances 0.000 claims abstract description 93
- 239000000919 ceramic Substances 0.000 claims abstract description 25
- 238000009413 insulation Methods 0.000 claims abstract description 13
- 239000000758 substrate Substances 0.000 claims description 27
- 238000000034 method Methods 0.000 claims description 24
- 230000015556 catabolic process Effects 0.000 abstract description 2
- 230000007423 decrease Effects 0.000 abstract description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 14
- 238000005219 brazing Methods 0.000 description 14
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000010949 copper Substances 0.000 description 13
- 238000005530 etching Methods 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 5
- 238000005304 joining Methods 0.000 description 5
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- HEMHJVSKTPXQMS-UHFFFAOYSA-M Sodium hydroxide Chemical compound [OH-].[Na+] HEMHJVSKTPXQMS-UHFFFAOYSA-M 0.000 description 3
- YXFVVABEGXRONW-UHFFFAOYSA-N Toluene Chemical compound CC1=CC=CC=C1 YXFVVABEGXRONW-UHFFFAOYSA-N 0.000 description 3
- 230000008646 thermal stress Effects 0.000 description 3
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- 230000000052 comparative effect Effects 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001111 Fine metal Inorganic materials 0.000 description 1
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 1
- 229910017309 Mo—Mn Inorganic materials 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- WUOACPNHFRMFPN-UHFFFAOYSA-N alpha-terpineol Chemical compound CC1=CCC(C(C)(C)O)CC1 WUOACPNHFRMFPN-UHFFFAOYSA-N 0.000 description 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- OMZSGWSJDCOLKM-UHFFFAOYSA-N copper(II) sulfide Chemical compound [S-2].[Cu+2] OMZSGWSJDCOLKM-UHFFFAOYSA-N 0.000 description 1
- 229960003280 cupric chloride Drugs 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- SQIFACVGCPWBQZ-UHFFFAOYSA-N delta-terpineol Natural products CC(C)(O)C1CCC(=C)CC1 SQIFACVGCPWBQZ-UHFFFAOYSA-N 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical compound [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 238000007517 polishing process Methods 0.000 description 1
- 229920000205 poly(isobutyl methacrylate) Polymers 0.000 description 1
- 239000002243 precursor Substances 0.000 description 1
- 239000000376 reactant Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000005728 strengthening Methods 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 229940116411 terpineol Drugs 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0254—High voltage adaptations; Electrical insulation details; Overvoltage or electrostatic discharge protection ; Arrangements for regulating voltages or for using plural voltages
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
Landscapes
- Structure Of Printed Boards (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、電子部品のパワー
モジュール等に使用される回路基板に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board used for a power module of an electronic component.
【0002】[0002]
【従来の技術】近年、ロボットやモーター等の産業機器
の高性能化に伴い、大電力・高能率インバーター等パワ
ーモジュールの変遷が進んでおり、半導体素子から発生
する熱も増加の一途をたどっている。この熱を効率よく
放散させるため、パワーモジュール基板では従来より様
々な方法が取られてきた。特に最近、良好な熱伝導を有
するセラミックス基板が利用できるようになったため、
その基板上に銅板等の金属板を接合し、回路を形成後、
そのままあるいはNiメッキ等の処理を施してから半導
体素子を実装する構造も採用されつつある。2. Description of the Related Art In recent years, power modules such as high-power and high-efficiency inverters have been changing with the advancement of the performance of industrial equipment such as robots and motors, and the heat generated from semiconductor devices has been increasing steadily. I have. In order to efficiently dissipate this heat, various methods have conventionally been used for power module substrates. Especially recently, ceramic substrates with good thermal conductivity have become available,
After joining a metal plate such as a copper plate on the board and forming a circuit,
A structure in which a semiconductor element is mounted as it is or after performing a process such as Ni plating has been adopted.
【0003】このようなモジュールは、当初、簡単な工
作機械に使用されてきたが、ここ数年、溶接機、電車の
駆動部、電気自動車に使用されるようになり、より厳し
い環境条件下における耐久性と更なる小型化が要求され
るようになってきた。[0003] Such modules have initially been used in simple machine tools, but in recent years have been used in welding machines, train drives, electric vehicles and in more severe environmental conditions. Durability and further miniaturization have been required.
【0004】[0004]
【発明が解決しようとする課題】この要求を満たすに
は、例えば電流密度を上げるための金属回路厚の増加
や、金属回路パターンの微細化等があるが、それをヒー
トサイクルに対する耐久性と生産性に優れる活性金属ろ
う付け法によって実現させることは困難であった。何故
なら、活性金属ろう付け法においては、金属回路パター
ン形成時にろう材除去を行う必要があるからである。To meet this demand, for example, there is an increase in the thickness of a metal circuit to increase the current density and a finer metal circuit pattern. It has been difficult to achieve this by an active metal brazing method having excellent properties. This is because, in the active metal brazing method, it is necessary to remove the brazing material when forming a metal circuit pattern.
【0005】本発明の目的は、ヒートサイクルに対する
耐久性が高く、金属回路パターンの微細化を実現させた
回路基板を生産性よく製造することである。本発明の目
的は、活性金属を含む接合層の金属回路の下端部からの
はみ出し長さ及び金属回路パターン間隔の長さを最適化
することによって達成することができる。An object of the present invention is to manufacture a circuit board having high durability against a heat cycle and realizing miniaturization of a metal circuit pattern with high productivity. The object of the present invention can be achieved by optimizing the length of the bonding layer containing the active metal protruding from the lower end of the metal circuit and the length of the metal circuit pattern interval.
【0006】[0006]
【課題を解決するための手段】すなわち、本発明は、活
性金属を含む接合層を、金属回路の下端部から内側及び
/又は外側にはみ出させて金属回路がセラミックス基板
に接合されてなるものであって、金属回路同士間、接合
層同士間及び金属回路と接合層との間の間隔のうち最短
間隔が0.5〜1.0mmであり、しかもその最短間隔
における150℃の絶縁抵抗が1×1011Ω・cm以上
であることを特徴とする回路基板である。That is, the present invention provides a method in which a bonding layer containing an active metal is protruded inward and / or outward from a lower end portion of a metal circuit and the metal circuit is bonded to a ceramic substrate. The shortest distance between the metal circuits, between the bonding layers, and between the metal circuit and the bonding layer is 0.5 to 1.0 mm, and the insulation resistance at 150 ° C. in the shortest distance is 1 mm. × 10 11 Ω · cm or more.
【0007】更に、本発明は、活性金属を含む接合層
を、金属回路の下端部から内側及び/又は外側にはみ出
させて金属回路がセラミックス基板に接合されてなるも
のであって、金属回路同士間、接合層同士間及び金属回
路と接合層との間の間隔のうち最短間隔が0.5〜1.
0mm、金属回路の下端部からのはみ出し接合層の長さ
が−50μm(内側に50μm)〜+30μm(外側に
30μm)、及び金属回路の下端部と上端部との寸法差
が50〜100μmであることを特徴とする回路基板で
ある。Further, the present invention provides a method in which a bonding layer containing an active metal is protruded inward and / or outward from a lower end portion of a metal circuit so that the metal circuit is bonded to a ceramic substrate. , Between the bonding layers, and between the metal circuit and the bonding layer, the shortest distance is 0.5 to 1.
0 mm, the length of the bonding layer protruding from the lower end of the metal circuit is −50 μm (inside 50 μm) to +30 μm (outside 30 μm), and the dimensional difference between the lower end and upper end of the metal circuit is 50 to 100 μm. It is a circuit board characterized by the above-mentioned.
【0008】[0008]
【発明の実施の形態】以下、更に詳しく本発明について
説明すると、銅等の金属回路と窒化アルミニウム基板等
のセラミックス基板が接合層を介して接合されてなる回
路基板の信頼性については、接合層の厚みも以外に、ヒ
ートサイクルに伴う金属回路のセラミックス基板からの
剥離は金属回路端部から生じるため、その端部形状を適
正化し、熱応力を緩和させることが重要なことである
(例えば特開平3−261669号公報、特開平4−3
43287号公報)。BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below in more detail. The reliability of a circuit board formed by bonding a metal circuit such as copper and a ceramic substrate such as an aluminum nitride substrate via a bonding layer will be described. In addition to the thickness of the metal circuit, the peeling of the metal circuit from the ceramic substrate due to the heat cycle occurs from the edge of the metal circuit, so it is important to optimize the edge shape and reduce the thermal stress (for example, JP-A-3-261669, JP-A-4-3
No. 43287).
【0009】従来までの認識は、エッチングファクター
すなわち金属回路の下端部と上端部との寸法差が大き
く、しかも金属回路下端部からの接合層のはみ出し長さ
の大きい方が熱応力が分散されるので、金属回路が剥離
し難いとういことであった。しかしながら、エッチング
ファクターの小さい金属回路パターンの設計を行うに
は、パターン間距離を長くする必要があったので、小型
化や金属回路パターンの微細化に対応できないという問
題があった。そこで、本発明者らは、エッチングファク
ターと接合層のはみ出し長さを規定することによって、
信頼性を保持しつつ、小型化と金属回路パターンの微細
化を可能とした。Conventionally, it has been recognized that the larger the etching factor, that is, the dimensional difference between the lower end and the upper end of the metal circuit, and the larger the length of the protrusion of the bonding layer from the lower end of the metal circuit, the more the thermal stress is dispersed. Therefore, it was difficult for the metal circuit to peel off. However, in order to design a metal circuit pattern having a small etching factor, it is necessary to increase the distance between the patterns. Therefore, the present inventors defined the etching factor and the length of protrusion of the bonding layer,
While maintaining reliability, miniaturization and miniaturization of metal circuit patterns were made possible.
【0010】本発明の回路基板の形状の一例を示す部分
概略断面図を図1、図2に示す。図1は、接合層が金属
回路の下端部から外側にはみ出た例であり、図2は接合
層が外側と内側にはみ出た例である。図において、1は
金属回路、2は接合層、3はセラミックス基板であり、
またtは金属回路の厚み、aははみ出し接合層の長さ
(+が外側、−が内側にはみ出ていることを示す)、b
は金属回路の下端部と上端部との寸法差、cは金属回路
同士間、接合層同士間及び金属回路と接合層との間の間
隔のうちの最短間隔である。FIG. 1 and FIG. 2 are partial schematic sectional views showing an example of the shape of the circuit board of the present invention. FIG. 1 shows an example in which the bonding layer protrudes outside from the lower end of the metal circuit, and FIG. 2 shows an example in which the bonding layer protrudes outside and inside. In the figure, 1 is a metal circuit, 2 is a bonding layer, 3 is a ceramic substrate,
In addition, t is the thickness of the metal circuit, a is the length of the protruding bonding layer (+ indicates that it protrudes outside, and-indicates that it protrudes inside), b
Is the dimensional difference between the lower end and the upper end of the metal circuit, and c is the shortest distance among the metal circuits, between the bonding layers, and between the metal circuit and the bonding layer.
【0011】本発明の回路基板の前提条件は、金属回路
とセラミックス基板とが活性金属を含む接合層により接
合されていることであり、これは活性金属ろう付け法に
よって製造することができる。この場合、セラミックス
基板の一方の面に金属回路、他方の面に金属放熱板を形
成する方法としては、セラミックス基板と金属板との接
合体をエッチングする方法、金属板から打ち抜かれた金
属回路、放熱金属板のパターンをセラミックス基板に接
合する方法等によって行うことがでる。A prerequisite of the circuit board of the present invention is that the metal circuit and the ceramic substrate are joined by a joining layer containing an active metal, which can be manufactured by an active metal brazing method. In this case, as a method of forming a metal circuit on one surface of the ceramic substrate and a metal radiator plate on the other surface, a method of etching a joined body of the ceramic substrate and the metal plate, a metal circuit punched from the metal plate, It can be performed by a method of joining the pattern of the heat dissipating metal plate to the ceramic substrate or the like.
【0012】金属とセラミックスの接合方法としては、
活性金属ろう付け法以外に、Mo−Mn法、硫化銅法、
DBC法、銅メタライズ法等があるが、本発明で活性金
属ろう付け法を採用している理由は、この方法はヒート
サイクルに対する耐久性と生産性に優れるからである。[0012] As a joining method of metal and ceramics,
In addition to the active metal brazing method, the Mo-Mn method, the copper sulfide method,
Although there are a DBC method, a copper metallization method, and the like, the reason why the active metal brazing method is employed in the present invention is that this method is excellent in durability against heat cycles and productivity.
【0013】活性金属ろう付け法については、例えば特
開昭60−177634号公報に記載されている。活性
金属ろう付け法におけるろう材の金属成分は、銀と銅を
主成分とし、溶融時のセラミックス基板との濡れ性を確
保するために活性金属を副成分とする。活性金属成分
は、セラミックス基板と反応して酸化物や窒化物を生成
し、ろう材とセラミックス基板との結合を強固なものに
する。活性金属の具体例をあげれば、チタン、ジルコニ
ウム、ハフニウム、ニオブ、タンタル、バナジウムやこ
れらの化合物である。これらの比率としては、銀80〜
95重量部と銅20〜5重量部の合計量100重量部あ
たり活性金属1〜7重量部である。接合温度は800〜
840℃が望ましい。また、このろう材で形成される接
合層の厚みは、10〜20μm程度であることが好まし
い。The active metal brazing method is described in, for example, JP-A-60-177634. The metal component of the brazing material in the active metal brazing method contains silver and copper as main components, and uses the active metal as a sub-component in order to ensure wettability with the ceramic substrate during melting. The active metal component reacts with the ceramic substrate to generate an oxide or a nitride, thereby strengthening the bond between the brazing material and the ceramic substrate. Specific examples of the active metal include titanium, zirconium, hafnium, niobium, tantalum, vanadium, and compounds thereof. As a ratio of these, silver 80 to
The active metal is 1 to 7 parts by weight per 100 parts by weight of the total of 95 parts by weight and 20 to 5 parts by weight of copper. The joining temperature is 800 ~
840 ° C. is desirable. The thickness of the bonding layer formed of the brazing material is preferably about 10 to 20 μm.
【0014】次に、本発明の回路基板においては、金属
回路の厚みtが0.3mm以上、特に0.3〜0.5m
mが好ましい。0.3mmよりも薄いと高電流密度の要
求に対応することができない。金属放熱板を形成させる
場合は、その厚みは0.2mm以上であることが好まし
い。金属回路及び金属放熱板の材質としては、銅又は銅
合金が一般的であるが、これに限定されることはない。Next, in the circuit board of the present invention, the thickness t of the metal circuit is 0.3 mm or more, especially 0.3 to 0.5 m.
m is preferred. If it is thinner than 0.3 mm, it cannot meet the demand for high current density. When a metal heat sink is formed, its thickness is preferably 0.2 mm or more. The material of the metal circuit and the metal radiator plate is generally copper or a copper alloy, but is not limited thereto.
【0015】また、本発明においては、金属回路同士
間、接合層同士間及び金属回路と接合層との間の間隔の
うち最短間隔cが0.5〜1.0mmである。最短間隔
cが0.5mmよりも狭いと絶縁抵抗が小さくなり、
1.0mmよりも広くなると、もはやファインパターン
とはいえない。In the present invention, the shortest distance c among the metal circuits, between the bonding layers, and between the metal circuit and the bonding layer is 0.5 to 1.0 mm. If the shortest interval c is smaller than 0.5 mm, the insulation resistance decreases,
If it is wider than 1.0 mm, it can no longer be said to be a fine pattern.
【0016】更に、本発明においては、上記最短間隔c
における150℃の絶縁抵抗が1×1011Ω・cm以上
である。絶縁抵抗がこれよりも小さいと5.0kV及び
0.5mAの電流が流れたときに絶縁破壊を起こしてし
まう。Further, in the present invention, the shortest interval c
The insulation resistance at 150 ° C. is 1 × 10 11 Ω · cm or more. If the insulation resistance is smaller than this, insulation breakdown occurs when a current of 5.0 kV and 0.5 mA flows.
【0017】このような絶縁抵抗にするには、上記最短
間隔cを0.5mm以上とすると共に、金属回路の下端
部からのはみ出し接合層の長さaを−50μm(内側に
50μmはみ出している意味)から+30μm(外側に
30μmはみ出している意味)、好ましくは−20μm
〜+20μmとすることである。なお、−50μmより
も更に内側に接合層をはみ出させることによって絶縁抵
抗を更に大きくすることができるが、この場合はセラミ
ックス基板と金属回路との空隙に微少な異物が入り込み
易くなり、実装時の加熱によってその異物が外に出て不
具合を起こしたり、ヒートサイクルに対する耐久性が悪
くなる。In order to achieve such an insulation resistance, the shortest distance c is set to 0.5 mm or more, and the length a of the bonding layer protruding from the lower end of the metal circuit is -50 μm (extending inward by 50 μm). Meaning) to +30 μm (meaning protruding 30 μm outside), preferably -20 μm
To +20 μm. Note that the insulation resistance can be further increased by protruding the bonding layer further inside than -50 μm, but in this case, minute foreign matters easily enter the gap between the ceramic substrate and the metal circuit, and the The heating causes the foreign matter to go out, causing a problem or deteriorating the durability to a heat cycle.
【0018】更に、本発明の回路基板にあっては、エッ
チングファクターを示す金属回路の下端部と上端部との
寸法差bが50〜100μmであることが好ましい。5
0μmよりも小さいと、熱応力の集中が大きく回路基板
の耐久性に問題があり、また100μmよりも大きい
と、実際にシリコンチップ等を搭載する金属回路面の広
さが狭くなりファインパターン化に支障を来し小型化が
困難となる。Further, in the circuit board of the present invention, it is preferable that the dimensional difference b between the lower end and the upper end of the metal circuit indicating the etching factor is 50 to 100 μm. 5
If it is smaller than 0 μm, the thermal stress concentration is large and there is a problem in the durability of the circuit board. If it is larger than 100 μm, the width of the metal circuit surface on which a silicon chip or the like is actually mounted becomes narrow, resulting in fine patterning. This will hinder the miniaturization.
【0019】本発明で使用されるセラミックス基板の材
質としては、窒化ケイ素、窒化アルミニウム、アルミナ
等であるが、パワーモジュールには窒化アルミニウムが
適している。セラミックス基板の厚みとしては、厚すぎ
ると熱抵抗が大きくなり、薄すぎると耐久性がなくなる
ため、0.5〜0.8mm程度が好ましい。The material of the ceramic substrate used in the present invention is silicon nitride, aluminum nitride, alumina or the like, but aluminum nitride is suitable for the power module. When the thickness of the ceramic substrate is too large, the thermal resistance increases, and when the thickness is too small, the durability is lost. Therefore, the thickness is preferably about 0.5 to 0.8 mm.
【0020】また、セラミックス基板の表面性状は重要
であり、微少な欠陥や窪み等は、金属回路、金属放熱板
あるいはそれらの前駆体である金属板をセラミックス基
板に接合する際に悪影響を与えるため、平滑であること
が望ましい。従って、セラミックス基板は、ホーニング
処理や機械加工等による研磨処理が施されていることが
好ましい。Further, the surface properties of the ceramic substrate are important, and minute defects and dents have an adverse effect when joining a metal circuit, a metal radiator plate or a metal plate which is a precursor thereof to the ceramic substrate. It is desirable that the surface be smooth. Therefore, it is preferable that the ceramic substrate has been subjected to a honing process or a polishing process such as machining.
【0021】[0021]
【実施例】以下、本発明を実施例と比較例をあげて具体
的に説明する。The present invention will be specifically described below with reference to examples and comparative examples.
【0022】実施例1〜6 比較例1〜6 重量割合で、銀粉末90部、銅粉末10部、ジルコニウ
ム粉末3部、チタン粉末3部及びテルピネオール15部
を配合し、ポリイソブチルメタアクリレートのトルエン
溶液を加えてよく混練し、ろう材ペーストを調整した。
このろう材ペーストを窒化アルミニウム基板(サイズ:
60mm×36mm×0.65mm 曲げ強さ:40k
g/mm2 熱伝導率:135W/mK)の両面にスク
リーン印刷によって全面に塗布した。その際の塗布量
(乾燥後)は9mg/cm2 とした。Examples 1 to 6 Comparative Examples 1 to 6 90 parts of silver powder, 10 parts of copper powder, 3 parts of zirconium powder, 3 parts of titanium powder and 15 parts of terpineol were mixed in a weight ratio, and toluene of polyisobutyl methacrylate was mixed. The solution was added and kneaded well to prepare a brazing filler metal paste.
This brazing material paste is applied to an aluminum nitride substrate (size:
60mm × 36mm × 0.65mm Flexural strength: 40k
g / mm 2 ( thermal conductivity: 135 W / mK). The coating amount (after drying) at that time was 9 mg / cm 2 .
【0023】次に、金属回路形成面に60mm×36m
m×0.3mmの銅板を、また金属放熱板形成面に60
mm×36mm×0.15mmの銅板をそれぞれ接触配
置してから、真空度1×10-5Torr以下の真空下、
830℃で30分加熱した後、2℃/分の降温速度で冷
却して接合体を製造した。Next, the metal circuit forming surface is 60 mm × 36 m
An mx 0.3 mm copper plate and 60
mm × 36 mm × 0.15 mm copper plates were placed in contact with each other, and then under a vacuum of 1 × 10 −5 Torr or less,
After heating at 830 ° C. for 30 minutes, the mixture was cooled at a temperature lowering rate of 2 ° C./min to produce a joined body.
【0024】次いで、この接合体の銅板上にUV硬化タ
イプのエッチングレジストをスクリーン印刷で塗布後、
塩化第2銅溶液を用い、表1に示す種々の処理時間でエ
ッチング処理を行って銅板不要部分を溶解除去し、更に
エッチングレジストを5%苛性ソーダ溶液で剥離した。
このエッチング処理後の接合体には、銅回路パターン間
に残留不要ろう材や活性金属成分と窒化アルミニウム基
板との反応物があるので、それを除去するため、表1に
示す濃度のフッ化アンモニウム(NH4 F)と過酸化水
素(H2 O2 )の混合溶液からなる薬液に浸漬し、表1
に示される寸法の回路基板を製造した。Next, an UV-curable etching resist is applied on the copper plate of the joined body by screen printing.
Using a cupric chloride solution, etching treatment was performed for various treatment times shown in Table 1 to dissolve and remove unnecessary portions of the copper plate, and the etching resist was peeled off with a 5% sodium hydroxide solution.
In the joined body after the etching process, there is a residual unnecessary brazing material or a reactant between the active metal component and the aluminum nitride substrate between the copper circuit patterns. (NH 4 F) and hydrogen peroxide (H 2 O 2 ).
The circuit board of the dimensions shown in was manufactured.
【0025】これら一連の処理を経て製作された回路基
板について、気中、−40℃×30分保持後、25℃×
10分間放置、更に125℃×30分保持後、25℃×
10分間放置を1サイクルとするヒートサイクル試験を
行い、銅回路又は放熱銅板が剥離開始したヒートサイク
ル回数を測定した。The circuit board manufactured through these series of processes was kept in the air at -40.degree. C. for 30 minutes and then at 25.degree.
Leave for 10 minutes, keep at 125 ° C x 30 minutes, then 25 ° C x
A heat cycle test in which one cycle was left for 10 minutes was performed, and the number of heat cycles at which the copper circuit or the heat-dissipating copper plate started peeling was measured.
【0026】また、最短間隔cにおける温度150℃の
絶縁抵抗をJIS C 6481に準じて測定した。更
に、パターン間の絶縁耐圧試験を、絶縁油中、AC5.
0kV、カットオフ電流0.5mAを1分間印加して行
った。それらの結果を表1に示す。The insulation resistance at a temperature of 150 ° C. at the shortest interval c was measured according to JIS C6481. Further, a withstand voltage test between patterns was carried out in an insulating oil under AC5.
The test was performed by applying 0 kV and a cutoff current of 0.5 mA for 1 minute. Table 1 shows the results.
【0027】[0027]
【表1】 [Table 1]
【0028】[0028]
【発明の効果】本発明によれば、ヒートサイクルに対す
る耐久性が高く、金属回路パターンの微細化を実現させ
た回路基板を生産性よく製造することができる。According to the present invention, a circuit board having high durability against a heat cycle and realizing a fine metal circuit pattern can be manufactured with high productivity.
【図1】本発明の回路基板の形状の一例を説明する部分
概略断面図。FIG. 1 is a partial schematic cross-sectional view illustrating an example of the shape of a circuit board according to the present invention.
【図2】本発明の回路基板の形状の一例を説明する部分
概略断面図。FIG. 2 is a partial schematic cross-sectional view illustrating an example of the shape of a circuit board according to the present invention.
1 金属回路 2 接合層 3 セラミックス基板 t 金属回路の厚み a はみ出し接合層の長さ b 金属回路の下端部と上端部との寸法差 c 金属回路同士間、接合層同士間及び金属回路と接合
層との間の間隔のうちの最短間隔Reference Signs List 1 metal circuit 2 bonding layer 3 ceramic substrate t thickness of metal circuit a length of protruding bonding layer b dimensional difference between lower end and upper end of metal circuit c between metal circuits, between bonding layers and between metal circuit and bonding layer Shortest of the intervals between
Claims (2)
端部から内側及び/又は外側にはみ出させて金属回路が
セラミックス基板に接合されてなるものであって、金属
回路同士間、接合層同士間及び金属回路と接合層との間
の間隔のうち最短間隔が0.5〜1.0mmであり、し
かもその最短間隔における150℃の絶縁抵抗が1×1
011Ω・cm以上であることを特徴とする回路基板。1. A metal circuit bonded to a ceramic substrate by protruding a bonding layer containing an active metal from a lower end portion of a metal circuit to the inside and / or the outside, wherein the metal circuit is bonded to a ceramic substrate. The shortest distance among the distances between them and between the metal circuit and the bonding layer is 0.5 to 1.0 mm, and the insulation resistance at 150 ° C. in the shortest distance is 1 × 1.
A circuit board having a resistance of 0 11 Ω · cm or more.
端部から内側及び/又は外側にはみ出させて金属回路が
セラミックス基板に接合されてなるものであって、金属
回路同士間、接合層同士間及び金属回路と接合層との間
の間隔のうち最短間隔が0.5〜1.0mm、金属回路
の下端部からのはみ出し接合層の長さが−50μm(内
側に50μm)〜+30μm(外側に30μm)、及び
金属回路の下端部と上端部との寸法差が50〜100μ
mであることを特徴とする回路基板。2. A method in which a bonding layer containing an active metal protrudes inward and / or outward from a lower end portion of a metal circuit so that the metal circuit is bonded to a ceramic substrate. The shortest distance among the distances between the metal circuits and the bonding layer is 0.5 to 1.0 mm, and the length of the bonding layer protruding from the lower end of the metal circuit is −50 μm (inside 50 μm) to +30 μm ( 30 μm on the outside), and the dimensional difference between the lower end and the upper end of the metal circuit is 50-100 μm
m.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13470797A JP3449458B2 (en) | 1997-05-26 | 1997-05-26 | Circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP13470797A JP3449458B2 (en) | 1997-05-26 | 1997-05-26 | Circuit board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH10326949A true JPH10326949A (en) | 1998-12-08 |
JP3449458B2 JP3449458B2 (en) | 2003-09-22 |
Family
ID=15134726
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JP13470797A Expired - Lifetime JP3449458B2 (en) | 1997-05-26 | 1997-05-26 | Circuit board |
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