JPH10326899A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain with high productivity a TFT having a high-resistance region such as an LDD and an offset region. SOLUTION: After a gate electrode 105 has been formed, light doping is carried out. Then, an anode oxide film 113 is formed. At this time, a method which advances anode oxidation inside and outside is adopted. Then, an exposed gate-insulating film 104 is removed and doping is carried out again under heavy doping conditions. Thus, a high-resistance region is formed nearly by self- matching. In this process, no insulating film is present on the surface of the doped region at the time of the heavy doping, so that the doping can be performed with high efficiency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD [0001] The invention disclosed in the present specification is:
The present invention relates to a structure of a thin film transistor. Further, the present invention relates to a manufacturing method thereof. In addition, the present invention relates to an apparatus using a thin film transistor.

[0002]

2. Description of the Related Art Thin film transistors (hereinafter, referred to as TFTs) using a thin film semiconductor as an active layer are known. A typical configuration of a TFT is that used for an active matrix type liquid crystal display device, and uses a thin film semiconductor manufactured on a glass substrate or a quartz substrate.

In general, since it is difficult to form a single crystal silicon film on a glass substrate or a quartz substrate, an amorphous silicon film or a polycrystalline silicon film is usually used. A silicon film other than a single-crystal silicon film is called a non-single-crystal silicon film.

A non-single-crystal silicon film has a relatively high defect density as compared with a single crystal. Because of the relatively high defect density, a TFT using a non-single-crystal silicon film exhibits relatively high OFF current characteristics (also referred to as leak current characteristics).

[0005] The presence of the OFF current is also a problem in a MOS transistor using a single crystal silicon wafer, but the tendency is particularly remarkable in a TFT.

A TFT (a-Si) using an amorphous silicon film
In TFT), since the channel resistance is high, the OFF current value is small (however, the ON current value is also small), and the presence of the OFF current does not cause a serious problem.

As a method of reducing the OFF current value of the TFT, Japanese Patent Publication No. Hei 3-38755 and Japanese Patent Laid-Open No. 4-360
The configurations described in JP-A-580-580 and JP-A-5-166637 are known.

The configuration described in the above publication is called an LDD technology and an offset technology. This technology is
A high-resistance region which does not function as a channel or a drain is arranged between the channel region and the drain region to reduce a high electric field applied between the channel region and the drain region.

By doing so, during the OFF operation,
This is to suppress the movement of carriers via defects existing near the boundary between the channel region and the drain region.

The type of the high-resistance region is roughly classified into a non-doped region and a lightly-doped region.

Japanese Patent Laid-Open Publication Nos. Hei 4-360580 and Hei 5-16837 disclose a method of forming a high-resistance region by forming an anodic oxide film on the surface of a gate electrode and forming a film of the anodic oxide film. A technique for defining a high resistance region in a self-aligned manner by the thickness is disclosed.

This method is characterized in that a high resistance region can be formed with high controllability.

[0013]

An object of the invention disclosed in this specification is to provide a novel structure with respect to the above-described technique for forming a high-resistance region. In particular, it is an object to provide a structure having higher controllability and higher productivity in relation to a doping technique.

[0014]

One of the inventions disclosed in the present specification is an active layer, a gate insulating film formed on the active layer, and an anodizable film formed on the gate insulating film. A gate electrode made of a suitable material, an anodic oxide film is formed on at least a side surface of the gate electrode, and a channel region, an offset region, a low concentration impurity region, and a source / drain are formed in the active layer. Region is formed,
A boundary between the channel region and the offset region is defined by a boundary between the gate electrode and the anodic oxide film, and a boundary between the low-concentration impurity region and the source / drain region is a position of the surface of the anodic oxide film on the side surface of the gate electrode. Wherein the gate insulating film is patterned with the anodic oxide film.

According to another aspect of the present invention, there is provided an active layer, a gate insulating film formed on the active layer, and a gate electrode made of an anodizable material formed on the gate insulating film. An anodic oxide film is formed on at least a side surface of the gate electrode; a channel region, an offset region, a low-concentration impurity region, and a source / drain region are formed in the active layer; The boundary between the gate electrode and the anodic oxide film is defined by the boundary between the gate electrode and the anodic oxide film. The boundary between the low-concentration impurity region and the source / drain region at the position of the surface of the anodic oxide film on the side surface of the gate electrode, and the gate insulation A semiconductor device, wherein an end of the film is defined.

In the above two structures, tantalum can be cited as a material forming the gate electrode. Besides tantalum, aluminum can be mentioned. These anodizable materials may contain a small amount of impurities. Further, the material constituting the gate electrode may be a silicide material which can be anodized.

As the gate electrode, it is preferable to use a material that can be anodized and has high heat resistance. In addition, TaN-
A material in which Ta-TaN and three layers are stacked can also be used.

"Defined" in the structures disclosed herein means that the position is determined. For example, "the boundary between the channel region and the offset region is defined by the boundary between the gate electrode and the anodic oxide film" means that the position of the boundary between the channel region and the offset region is determined by the boundary between the gate electrode and the anodic oxide film. It means that it is decided. At this time, since there is wraparound and diffusion of the impurities (these differ depending on the doping means and conditions, and also on the annealing means and conditions), the boundaries between the two do not always coincide.

According to another aspect of the invention, a step of forming an active layer pattern, a step of forming a gate insulating film on the active layer pattern, and a step of forming a pattern made of an anodizable material on the gate insulating film Performing a step of acceleratingly implanting impurity ions for imparting conductivity to the active layer using the pattern made of the anodizable material as a mask, and forming an anode on at least a side surface of the pattern made of the anodizable material. Forming an oxide film; etching the exposed region of the gate insulating film using the pattern made of the anodizable material and the anodized film formed on the surface thereof as a mask; Selectively accelerating and implanting the impurity ions in a region of the layer with a larger dose amount, wherein the anodic oxide film is made of an anodizable material. Characterized by growing toward the outside and inside of that pattern.

According to another aspect of the present invention, in the above structure, an offset region, a low-concentration impurity region, and a source / drain region are formed in the active layer pattern, and the offset region is formed by an anodic oxide film grown inside. And the low concentration impurity region is defined by an anodic oxide film grown outside.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A tantalum pattern 105 is formed as shown in FIG. Thereafter, using the tantalum pattern 105 as a mask, light doping is selectively performed on the regions 106 and 108 as shown in FIG. (FIG. 1 (B))

After the end of the doping, laser light irradiation is performed to anneal damage caused during doping and activate the dopant. It is important that this step be performed before the subsequent anodizing step.

This is because a portion where laser light cannot be irradiated after anodic oxidation is formed. Note that when heat treatment is performed instead of laser light irradiation, annealing may be performed after the last doping step.

Next, the outer region 111 and the inner region 110
Then, an anodic oxide film 113 in which anodic oxidation proceeds is formed.
(Fig. 1 (C))

In this anodic oxidation, the anodic oxidation proceeds by substantially the same distance between the outside and the inside. Here, the anodic oxidation distance is 200 nm.

Next, the exposed gate insulating film 104 is removed. In this state, a silicon oxide film 114 remains. In this step, the silicon oxide film 104 is formed by the anodic oxide film 113.
Is a step of patterning. (Figure 1
(D))

The second doping is performed under the condition of heavy doping. As a result, offset regions 117 and 119 defined inside by the anodized region 110 in which anodization has progressed are formed in a self-aligned manner. (Figure 2
(A))

The low-concentration impurity region 116 defined by the anodized region 111 in which the anodization has progressed outward.
And 120 are formed in a self-aligned manner.

This process is characterized in that an offset region and a low-concentration impurity region are separately formed depending on the growth direction (outside or inside) of anodic oxidation.

Since heavy doping is performed on the region where the gate insulating film 104 has been removed, the heavy doping can be performed with high efficiency and stability.

[0031]

【Example】

[Embodiment 1] FIGS. 1 and 2 show a manufacturing process of this embodiment. Here, an example of manufacturing an N-channel TFT is described.

First, as shown in FIG. 1A, a silicon oxide film 102 is formed as a base film on a glass substrate 101 to a thickness of 300 nm by a sputtering method.

Here, a glass substrate or a substrate having an insulating film formed on the surface of the glass substrate is referred to as a substrate having an insulating surface.

Examples of the substrate having an insulating surface include a quartz substrate, a substrate having an insulating film formed on a surface of a quartz substrate, and a substrate having an insulating film formed on a silicon substrate.

After forming the silicon oxide film 102 as a base film, an amorphous silicon film (not shown) serving as a starting film for forming an active layer later is formed to a thickness of 50 nm by a low pressure thermal CVD method. Film. (Fig. 1 (A))

The film is formed by the low pressure thermal CVD method because it is the densest and has a low content of a hydrogen component which is problematic in crystallization later.

Next, a KrF excimer laser (wavelength 248)
nm), an amorphous silicon film (not shown) is crystallized to obtain a crystalline silicon film.

The crystallization method may be heating or lamp irradiation.

After obtaining the crystalline silicon film, patterning is performed to obtain a pattern indicated by 103. The pattern 103 made of the crystalline silicon film will later become an active layer of the TFT. (Fig. 1 (A))

Next, a silicon oxide film 104 serving as a gate insulating film
Is formed to a thickness of 100 nm by a plasma CVD method.

Further, a tantalum film (not shown) is
The film is formed by a sputtering method to a thickness of. Then, by patterning this tantalum film, a pattern shown by 105 is obtained. This tantalum pattern 105 will later become a gate electrode. (Fig. 1 (A))

After the state shown in FIG. 1A is obtained, doping of phosphorus is performed by a plasma doping method. This doping is performed with a lower dose compared to the subsequent phosphorus doping. Here, the doping in this step is referred to as light doping for convenience.

This doping is performed under the condition that the dose is lower by about one or two digits than the condition for forming the source / drain regions.

In this step, light doping is performed on the regions 106 and 108 as shown in FIG.

At this time, doping is not performed in the region 107 because the tantalum pattern 105 exists.
(FIG. 1 (B))

Next, anodic oxidation is performed using the tantalum pattern 105 as an anode, and as shown in FIG.
13 is formed. At this time, the anodic oxidation proceeds in both the outer side 111 and the inner side 110. Where 10
Reference numeral 9 denotes the surface of the base tantalum pattern 105.

Reference numeral 112 denotes a tantalum pattern functioning as a gate electrode.

After the anodic oxidation step shown in FIG. 1C is completed, the exposed silicon oxide film 104 is removed by a dry etching method. Here, dry etching having perpendicular anisotropy is used.

In this step, the tantalum pattern 112 and the anodic oxide film 113 serve as a mask, and the silicon oxide film 104 in a region other than the region covered with the mask is removed.

Thus, the state shown in FIG. 1D is obtained. Here, 114 is the remaining silicon oxide film.

Next, doping is performed again. here,
FIG. 1 shows a phosphor doping method using a plasma doping method.
This is performed with a higher dose than in the case of (C).

In this step, the source / drain regions may be formed at a dose (the other conditions are the same) for forming the source / drain regions.

In this step, the regions 115 and 121 are doped with phosphorus at a high dose.
(Fig. 2 (A))

At this time, doping is not performed on some of the regions 116 and 120 which have been previously doped with a low dose. Therefore, the regions 116 and 120 remain as low concentration impurity regions. (Fig. 2 (A))

The dimensions of this low concentration impurity region are shown in FIG.
Anodized region 11 advanced outward in step (C)
It is determined by a thickness (growth distance) of 1.

The active layer region 118 below the gate electrode 112 becomes a channel region. 117 and 11
The area 9 is an offset area.

This region corresponds to the thickness (growth distance) of the region 110 in which anodization has progressed inward in FIG.

This offset region is a region where doping has not been performed during the doping step in FIGS. 1 (D) and 2 (A). Since it is off the region immediately below the gate electrode, the region does not function as a channel. (It doesn't mean that it doesn't completely function as a channel, but here we simply think so.)

After the doping is completed, by irradiating a KrF excimer laser, annealing for damage to the crystal structure caused at the time of doping and activation of the dopant are simultaneously performed.

Next, as shown in FIG.
25 is formed to a thickness of 200 nm by a plasma CVD method.

Further, an acrylic resin film 122 is formed.
This acrylic resin film has a minimum thickness of 600 nm.

In addition to acrylic, materials such as polyimide, polyamide, polyimide amide, and epoxy can be used. Here, the resin film is formed because its surface can be made flat.

After obtaining the state shown in FIG. 2B, an opening for contact is formed. Then, a source electrode 128 and a drain electrode 124 are formed.

Thus, the N-channel TFT shown in FIG. 2C is completed.

In the structure shown in this embodiment, it is assumed that a silicon oxide film (an insulating film constituting a gate insulating film) does not exist on the surface of the source region 115 and the drain region 121 at the time of doping for forming the region. Has become.

In consideration of productivity, it is not preferable to perform the doping through an insulating film at the time of doping. In particular, doping of phosphorus cannot be performed through an insulating film unless the acceleration voltage is set to a relatively high level due to the large atomic weight of phosphorus.

When doping is performed at a high accelerating voltage, the proportion of ions shielded by the insulating film is increased, so that the doping efficiency is considerably reduced. In addition, if the acceleration voltage is increased, it becomes difficult to maintain the voltage, so that the acceleration state becomes unstable, which is a factor that impairs the reproducibility and stability of doping.

These facts can be applied not only to the plasma doping method but also to the case where the ion implantation method is used. The above tendency becomes more remarkable as the dose increases.

Therefore, it is very preferable that the region to be doped is exposed during doping as shown in this embodiment.

[Embodiment 2] This embodiment is an example in which the manufacturing process shown in Embodiment 1 is improved. In the configuration shown in the first embodiment, the region to be doped is exposed in the heavy doping process shown in FIG.

This has the advantage that the doping effect and the doping efficiency can be increased. However, when the doping is performed at a high dose, the exposed region to be doped has a problem that the surface of the region to be doped is roughened (fine irregularities are formed).

The present embodiment has been devised to solve this problem.

In this embodiment, first, the state shown in FIG. 4A is obtained according to the steps shown in FIGS. FIG.
(A) is the same as the state shown in FIG. 1 (D).

After obtaining the state shown in FIG.
01 is formed. (FIG. 4 (B))

Here, as the insulating film 401, a 20-nm-thick silicon nitride film formed by a plasma CVD method is used.

It is important that the insulating film is dense and strong. The thickness of the active layer is smaller than the thickness of the active layer. Specifically, the thickness is selected from a thickness of 5 nm to 100 nm and is smaller than the thickness of the active layer.

Next, heavy doping of the dopant is performed. In this step, high-concentration doping is performed on the regions 115 and 121 as shown in FIG.

In this step, since the surface of the region to be doped is covered with the silicon nitride film, the surface of the region to be doped which is generated at the time of doping can be suppressed from being roughened.

[Embodiment 3] In this embodiment, an example of a semiconductor device utilizing the invention disclosed in this specification will be described. That is, an example of a semiconductor device using a TFT utilizing the invention disclosed in this specification is shown.

FIG. 3 shows examples of various semiconductor devices. These semiconductor devices use TFTs at least in part.

FIG. 3A shows a portable information processing terminal. This information processing terminal includes an active matrix type liquid crystal display or an active matrix type EL display in a main body 2001, and further includes a camera unit 2002 for taking in information from outside.

The camera unit 2002 includes an image receiving unit 2003 and operation switches 2004.

It is considered that information processing terminals will become thinner and lighter in order to improve their portability.

In such a configuration, it is preferable that the peripheral drive circuit, the arithmetic circuit, and the storage circuit on the substrate on which the active matrix type display 2005 is formed be integrated with TFTs.

FIG. 3B shows a head mounted display. This device includes an active matrix type liquid crystal display and an EL display 2102 in a main body 2101. The main body 2101 can be attached to the head with a band 2103.

FIG. 3C shows a projection type liquid crystal display device which is called a front projection type.

This device transmits light from a light source source 2202 provided in a main body 2201 to a reflection type liquid crystal display device 220.
3 and has a function of projecting an image on a screen 2205 by enlarging the image with an optical system 2204.

In such a configuration, the optical system 2204
Is required to be as small as possible in terms of cost. Accordingly, the display device 2203 is also required to be reduced in size.

When the size of an active matrix type flat panel display is reduced, it is required that a peripheral drive circuit for driving the active matrix circuit be integrated on the same substrate as the active matrix circuit.

This is because, when the size of the active matrix circuit is reduced, the circuit constituting the peripheral drive circuit is connected to an external I / O circuit.
This is because it is difficult to mount the device even if it is configured with C.

Therefore, in the display device 2203, the active matrix circuit and the peripheral drive circuit are mounted on the same substrate.
A configuration for integration by FT is adopted.

Here, an example is shown in which a reflection type liquid crystal display device 2503 is used. However, a transmissive liquid crystal display device may be used here. In this case, the optical system is different.

FIG. 3D shows a mobile phone.
This device includes an active matrix type liquid crystal display device 2304, operation switches 2305, a sound input portion 2303, a sound output portion 2302, and an antenna 2306 in a main body 2301.
It has.

Recently, a configuration in which a portable information processing terminal shown in (A) and a mobile phone shown in (D) are combined has been commercialized.

FIG. 3E shows a portable video camera. This is because the main body 2401 has an image receiving unit 2406,
An audio input unit 2403, operation switches 2404, an active matrix liquid crystal display 2402, and a battery 2405 are provided.

FIG. 3F shows a rear projection type liquid crystal display device. This configuration is similar to that of the main body 2501.
And a projection screen. The display is such that the light from the light source 2502 is
04, the separated light is optically modulated by a reflection type liquid crystal display device 2503, the optically modulated image is reflected and reflected by reflectors 2505 and 2506, and projected on a screen 2507. is there.

Here, an example is shown in which a reflection type liquid crystal display device 2503 is used. However, a transmissive liquid crystal display device may be used here. In this case, the optical system may be changed.

[Embodiment 4] This embodiment is an improvement of the manufacturing process shown in Embodiment 1. In the manufacturing process shown in Embodiment 1, in the process shown in FIG. 1D, the exposed silicon oxide film (constituting the gate insulating film) is completely removed.

The reason for this is to increase the doping efficiency by exposing the region to be doped in the subsequent heavy doping step (performed in the step shown in FIG. 2A).

However, on the other hand, the region to be doped is completely exposed at the time of doping (at the time of ion implantation).
In addition, problems such as rough surface condition may occur.

Therefore, in this embodiment, a manufacturing process as shown in FIG. 5 is employed. Here, first, FIG.
The state shown in FIG. 5A is obtained according to the process shown in FIG.
In this state, the silicon oxide film 104 is exposed in a region other than the portion where the gate electrode and the surrounding anodic oxide film are provided.

After the state shown in FIG. 5A is obtained, a dry etching method having perpendicular anisotropy (RIE method) is used.
The exposed silicon oxide film 104 is etched. On this occasion,
The conditions are such that all are etched.

For example, if the silicon oxide film 104 has a thickness of 100
nm, the thickness to be etched is 80 nm,
Leave 20 nm.

Thus, the state shown in FIG. 5B is obtained. Here, reference numeral 501 denotes a silicon oxide film remaining without being etched, and reference numeral 502 denotes a silicon oxide film left with a partial thickness left.

Thus, in heavy doping in a later step, the doping efficiency can be increased and the region to be doped can be protected at the same time.

That is, it is possible to prevent the remaining silicon oxide film 502 from remaining in a thickness that does not hinder doping, and to prevent the surface of the region to be doped from being roughened by the impact of dopant ions during doping.

By performing heavy doping on the regions to be the source / drain regions in this manner, the region shown in FIG.
The state shown in is obtained. This state corresponds to FIG.

Incidentally, the structure other than the gate insulating film is the same as that shown in FIGS. 1 and 2.

[Embodiment 5] In this embodiment, an example in which a part of an active matrix type liquid crystal display device is manufactured will be described. Here, an example is shown in which an active matrix circuit and a peripheral driver circuit are formed over the same substrate.

FIG. 6 shows a manufacturing process of this embodiment. First,
Three active layers made of a crystalline silicon film are formed on a glass substrate 601. Here, the existence of the base film is omitted.

The active layer has a first pattern represented by 602, 603, and 600, a second pattern represented by 604, 605, and 606, and a third pattern represented by 607, 608, and 609. Is shown.

Here, the first pattern and the second pattern correspond to two Ts constituting the CMOS circuit of the peripheral drive circuit.
It is an active layer of FT. The third pattern is an active layer of the TFT arranged in the pixel matrix.

After the pattern of each active layer is formed, a silicon oxide film 610 serving as a gate insulating film is formed, and gate electrodes 611, 612, and 613 made of tantalum are formed.

Further, light doping of impurities is selectively performed using a mask to form an N-type light doping region 6.
02, 600, and 607, 609 are formed. Further, P-type lightly doped regions 604 and 606 are formed. Thus, the state shown in FIG. 6A is obtained.

Next, each of the gate electrodes 611, 612, 613
Anodic oxidation is performed with the anode as an anode, and the anodic oxide films 614 and 61 are formed.
5, 616 are formed. This anodization proceeds outward and inward as shown in the first embodiment. (FIG. 6 (B))

Next, the exposed silicon oxide film 610 is removed by dry etching. Then, the state shown in FIG. 6C is obtained, and then doping of phosphorus and boron is selectively performed under heavy doping conditions.

Thus, regions 620 and 622 heavily doped with phosphorus and a region 621 heavily doped with boron are formed. (FIG. 6 (C))

Next, a silicon nitride film 629 and a resin film 630 are formed as an interlayer insulating film. Then, a contact hole is formed, and a source electrode 631 and a drain electrode 632 of the NTFT are formed. At the same time, a source electrode 634 and a drain electrode 633 of the PTFT are formed.

Further, N arranged in the pixel matrix circuit
A source electrode 635 and a drain electrode 636 of the TFT are formed. A pixel electrode (not shown) is connected to the drain electrode 636.

Here, NTFT is an N-channel type TF.
T and PTFT are P-channel TFTs.

Thus, NT arranged in the peripheral drive circuit
The CMOS circuit including the FT and the PTFT and the NTFT disposed in the pixel matrix circuit can be formed over the same substrate.

[0122]

According to the present invention, a novel technique for forming a high resistance region can be provided. Also, especially in relation to doping technology,
A configuration having higher controllability and higher productivity can be provided.

[Brief description of the drawings]

FIG. 1 illustrates a manufacturing process of a TFT.

FIG. 2 illustrates a manufacturing process of a TFT.

FIG. 3 is a diagram showing an outline of various devices.

FIG. 4 is a diagram showing a manufacturing process of a TFT.

FIG. 5 is a diagram showing a manufacturing process of a TFT.

FIG. 6 shows T of an active matrix type liquid crystal display device.
FIG. 5 illustrates a manufacturing process of an FT substrate.

[Explanation of symbols]

101 Glass Substrate 102 Underlayer (Silicon Oxide Film) 103 Active Layer 104 Silicon Oxide Film 105 Tantalum Pattern 106 Highly Doped Region 107 Undoped Region 108 Highly Doped Region 109 Surface of tantalum pattern before anodization 110 Anodized region proceeding inward 111 Anodized region proceeding outward 112 Gate electrode (remaining tantalum pattern) 113 Anodized film 114 Residual gate insulating film (silicon oxide film) 115 Source Region 116 low concentration impurity region 117 offset region 118 channel region 119 offset region 120 low concentration impurity region 121 drain region 125 silicon nitride film 122 acrylic resin film 123 source electrode 124 drain electrode

Claims (11)

[Claims] An active layer; a gate insulating film formed on the active layer; and a gate electrode made of an anodizable material formed on the gate insulating film. An anodic oxide film is formed on at least a side surface, and a channel region, an offset region, a low-concentration impurity region, and a source / drain region are formed in the active layer. A boundary is defined by a boundary between the gate electrode and the anodic oxide film. A boundary between the offset region and the source / drain region is defined at a position of the surface of the anodic oxide film on the side surface of the gate electrode. A semiconductor device characterized in that a gate insulating film is patterned. 2. An active layer, a gate insulating film formed on the active layer, and a gate electrode made of an anodizable material formed on the gate insulating film. An anodic oxide film is formed on at least a side surface, and a channel region, an offset region, a low-concentration impurity region, and a source / drain region are formed in the active layer, and a boundary between the channel region and the offset region is formed. Is defined by the boundary between the gate electrode and the anodic oxide film, the boundary between the low-concentration impurity region and the source / drain region at the position of the surface of the anodic oxide film on the side surface of the gate electrode, and the end of the gate insulating film. A semiconductor device characterized in that it is defined. 3. The semiconductor device according to claim 1, wherein tantalum is used as a material forming the gate electrode. 4. The semiconductor device according to claim 1, wherein an anodically oxidizable heat-resistant metal is used as a material for forming the gate electrode. 5. The semiconductor device according to claim 1, wherein the gate electrode has a structure in which TaN, Ta, and TaN are stacked. 6. A semiconductor device comprising a circuit in which the semiconductor device according to claim 1 or 2 is integrated. 7. A step of forming an active layer pattern, a step of forming a gate insulating film on the active layer pattern, a step of forming a pattern made of an anodizable material on the gate insulating film, A step of acceleratingly implanting impurity ions for imparting a conductivity type to the active layer using the pattern made of the anodizable material as a mask; and forming an anodized film on at least a side surface of the pattern made of the anodizable material. A step of etching the exposed region of the gate insulating film by using the pattern made of the anodizable material and the anodized film formed on the surface thereof as a mask; Selectively accelerating and implanting impurity ions at a larger dose, wherein the anodic oxide film is a pattern made of an anodizable material The method for manufacturing a semiconductor device, characterized in that to grow towards the outside and inside. 8. The method of manufacturing a semiconductor device according to claim 7, wherein tantalum is used as a material forming the gate electrode. 9. The method of manufacturing a semiconductor device according to claim 7, wherein an anodically oxidizable heat-resistant metal is used as a material forming the gate electrode. 10. The method according to claim 7, wherein T is used as a gate electrode.
A method for manufacturing a semiconductor device, comprising employing a structure in which aN, Ta, and TaN are stacked. 11. The active layer pattern according to claim 7, wherein an offset region, a low-concentration impurity region, and a source / drain region are formed in the active layer pattern, and the offset region is defined by an anodic oxide film grown inside. The method of manufacturing a semiconductor device, wherein the low-concentration impurity region is defined by an anodic oxide film grown outside.