JPH10322212A - Multi-channel d/a converter - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-channel D/A converter where production of an output offset voltage is prevented. SOLUTION: An offset adder circuit 14 adds a voltage to an output of a D/A converter 32 to cancel a maximum offset voltage in each offset voltage of two-stages of sample-and-hold circuits, and a conversion corresponding to each channel in a LUT 12 that converts image data for each channel received from an image memory 10 according to a prescribed rule and provides an output of the converted data to the D/A converter 32 is rewritten in advance for each channel so that each offset voltage of each sample-and-hold circuit is cancelled by applying the prescribed voltage to the output of the D/A converter 32.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a multi-channel digital / analog converter, and more particularly, to a multi-channel digital / analog converter for performing offset correction.

[0002]

2. Description of the Related Art A digital / analog converter (hereinafter, referred to as DA) for converting an input digital signal into an analog signal.
Converter) is expensive per channel, and in a system requiring a large number of DA converters, the cost of the entire system is high.

In order to solve such a problem, conventionally, as shown in FIG. 14, an analog switch 34 _n (where n is 1) is provided at an output terminal of a DA converter 32 for converting a digital signal for one channel into an analog signal. To N, the same applies hereinafter), sample-and-hold circuits composed of capacitors 36 _n and buffer amplifiers 38 _n are connected in parallel for the number of channels (for N channels in FIG. 14), and the input terminal of the DA converter 32 corresponds to each channel. The digital signal to be input is divided for each channel and input, and a sampling signal having a timing synchronized with the input timing is generated by the timing generation circuit 46, and the analog switch _34n is turned on / off for each channel by the sampling signal. Of the channel output from the DA converter 32 by controlling the switching of The analog signals of each Le sampled and held in the capacitor 36 _n, it has been used output signals from the buffer amplifiers 38 _n of the analog signal for each channel is the sample hold (1ch~Nch) as an analog signal for each channel.

[0004]

However, in the above-mentioned prior art, in order to increase the number of channels of the D / A converter for one channel, a sample and hold circuit for the number of channels is connected in parallel to the output terminal of the D / A converter. Therefore, there is a problem that an offset voltage different for each channel is generated in an output due to the influence of a buffer amplifier or the like constituting a sample-and-hold circuit. When such a multi-channel D / A converter is used as an LED drive current generation circuit for causing LED chips for the number of channels to emit light, for example, the LED chip emits light under the influence of the offset voltage even when the LED chips do not want to emit light. Would be.

The present invention has been made to solve the above problems, and has as its object to provide a multi-channel digital / analog converter capable of preventing generation of an output offset voltage.

[0006]

In order to achieve the above object, a multi-channel digital / analog converter according to claim 1 converts a digital signal of one channel into an analog signal, and the digital / analog converter. Input means for dividing a digital signal of a plurality of channels into the analog converter for each channel and inputting them;
A plurality of sample-and-hold circuits connected in parallel to output terminals of the digital-to-analog converter, each of which samples and holds an analog signal for each channel output from the digital-to-analog converter; And an adder circuit for applying a voltage for canceling each offset voltage.

The multi-channel digital / digital converter according to claim 1
According to the analog converter, a digital / analog converter that converts a one-channel digital signal into an analog signal receives a plurality of channels of digital signals that are divided for each channel by an input unit and input. Therefore, the analog signal output from the digital / analog converter is divided for each channel.

Thereafter, the analog signals for each channel output from the digital / analog converter are sampled and held by a plurality of sample / hold circuits respectively connected in parallel to the output terminals of the digital / analog converter.

Thus, in the multi-channel digital / analog converter according to the first aspect, one digital / analog converter is provided.
By sampling and holding the analog signal output from the analog converter for each channel in a time-division manner by a plurality of sample and hold circuits, a digital / analog converter corresponding to multiple channels is realized.

Further, in the multi-channel digital / analog converter according to the first aspect, a voltage for canceling the offset voltage of each of the plurality of sample and hold circuits is added by the addition circuit.

As described above, according to the multi-channel digital / analog converter according to the first aspect, since the voltage for canceling the offset voltage of each of the plurality of sample and hold circuits is added, the output offset voltage is generated. Can be prevented.

According to a second aspect of the present invention, there is provided a multi-channel digital / analog converter for converting a digital signal of one channel into an analog signal, and dividing the digital signal of a plurality of channels into the digital / analog converter for each channel. A plurality of sample-and-hold circuits respectively connected in parallel to output terminals of the digital / analog converter, and each of which samples and holds an analog signal for each channel output from the digital / analog converter; An adder circuit for applying a predetermined voltage to the output of the digital / analog converter; and a digital / analog converter so that the offset voltage of each of the plurality of sample and hold circuits is canceled by the application of the predetermined voltage. It comprises a converting means for converting the digital signals of each channel to be input to the data, the.

The multi-channel digital / digital converter according to claim 2
According to the analog converter, a digital / analog converter that converts a one-channel digital signal into an analog signal receives a plurality of channels of digital signals that are divided for each channel by an input unit and input. Therefore, the analog signal output from the digital / analog converter is divided for each channel.

After that, the analog signals for each channel output from the digital / analog converter are sampled and held by a plurality of sample / hold circuits respectively connected in parallel to the output terminals of the digital / analog converter.

As described above, in the multi-channel digital / analog converter according to the second aspect, like the multi-channel digital / analog converter according to the first aspect, the multi-channel digital / analog converter includes one channel.
An analog signal output for each channel from one digital / analog converter is sampled and held in a time-division manner by a plurality of sample / hold circuits, whereby a digital / analog converter corresponding to multiple channels is realized.

In the multi-channel digital / analog converter according to the present invention, a predetermined voltage is applied to the output of the digital / analog converter by the addition circuit, and the predetermined voltage is applied to each of the plurality of sample and hold circuits. The digital signal for each channel input to the digital / analog converter is converted by the conversion means so that the offset voltage is canceled.

As described above, according to the multi-channel digital / analog converter according to the second aspect, the predetermined voltage is applied to the output of the digital / analog converter and the predetermined voltage is applied, so that a plurality of sample-and-hold circuits are provided. Since a digital signal for each channel input to the digital / analog converter is converted so that each offset voltage is canceled, generation of an output offset voltage can be prevented.

Preferably, the predetermined voltage in the multi-channel digital / analog converter according to claim 2 is a voltage for canceling a maximum offset voltage among offset voltages of each of the plurality of sample and hold circuits. .

A multi-channel digital / analog converter according to claim 4, wherein a first digital / analog converter for converting a one-channel digital signal into an analog signal, and a multi-channel digital signal for the first digital / analog converter. Input means for dividing and inputting for each channel, and for each channel output from the first digital / analog converter while being connected in parallel to the output terminal of the first digital / analog converter. And a second digital / analog converter for converting a one-channel digital signal into an analog signal and adding the analog signal to an output of the first digital / analog converter And the first digital / analog Storage means for storing, for each channel, digital data for causing the second digital / analog converter to generate a voltage which is applied to an output of the analog / digital converter to cancel an offset voltage of each of the plurality of sample / hold circuits, In synchronization with the input of the digital signal for each channel to the first digital / analog converter, the digital data for each channel stored in the storage means is stored in the second digital / analog converter.
Second input means for inputting to the analog converter.

The multi-channel digital / digital converter according to claim 4
According to the analog converter, the digital signal of a plurality of channels is divided and input for each channel by the first input means to the first digital / analog converter which converts a digital signal of one channel into an analog signal. Therefore, the analog signal output from the first digital / analog converter is divided for each channel.

After that, the analog signals for each channel output from the first digital / analog converter are sampled and held by a plurality of sample / hold circuits respectively connected in parallel to the output terminals of the first digital / analog converter. You.

As described above, in the multi-channel digital / analog converter according to the fourth aspect, the analog signal output for each channel from one first digital / analog converter is sampled in a time division manner by the plurality of sample-and-hold circuits. By holding, a digital / analog converter corresponding to multiple channels is realized.

In the multi-channel digital / analog converter according to the fourth aspect, the digital signal of one channel is converted into an analog signal, and the analog signal is added to the output of the first digital / analog converter. An analog converter is provided and the first
Is applied to the output of the digital / analog converter to cancel the offset voltage of each of the plurality of sample and hold circuits.
The digital data generated by the analog converter is stored in the storage means for each channel, and the digital data for each channel stored in the storage means is synchronized with the input of the digital signal for each channel to the first digital / analog converter. The signal is input to the second digital / analog converter by the second input means.

Therefore, the output of the first digital / analog converter is supplied to each channel by the second digital / analog converter in synchronization with the input of a digital signal for each channel to the first digital / analog converter. A voltage for canceling the offset voltage of each of the corresponding plurality of sample and hold circuits is applied.

As described above, according to the multi-channel digital / analog converter of the fourth aspect, the second digital / analog converter is synchronized with the input of the digital signal for each channel to the first digital / analog converter. Since the voltage at which the offset voltage of each of the plurality of sample and hold circuits corresponding to each channel is canceled by the converter is applied to the output of the first digital / analog converter, the generation of the output offset voltage can be prevented.

[0026]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS In this embodiment, a multi-channel digital / analog converter according to the present invention is applied to an image recording apparatus which controls the light emission of an LED chip based on image data to record an image on a photosensitive material. Will be described.

[First Embodiment] In the first embodiment, the invention according to claims 1 to 3 will be described.

(Overall Configuration “Appearance”) FIGS.
1 shows an image recording apparatus 100 according to the first embodiment.

The image recording apparatus 100 is a CD-ROM
Image data recorded on an image data 102 and an FD (floppy disk) 104 (see FIG. 3) are read, an image based on the image data is exposed on a photosensitive material 106, and the image recorded on the photosensitive material 106 is Image receiving paper 10
8) This is a device for transferring and outputting.

The upper portion of the front surface (left side in FIG. 3) of the box-shaped casing 110 has an inclined surface, and an operation display unit 112 is provided.

As shown in FIG. 2, the operation display unit 112
Are classified into a monitor unit 114 located on the right side and an input unit 116 located on the left side, and the monitor unit 114 is configured to project the read image.

The input unit 116 is provided with a plurality of operation keys 1.
18 and an input data confirmation display unit 120, and the number of recordings, size setting, color balance adjustment, negative /
Data required for image recording, such as positive selection, can be input.

Below the operation display section 112, a deck section 1 is provided.
22 are provided. The deck section 122 includes a CD-ROM deck section 124 located on the right side of FIG. 2 and an FD deck section 126 located on the left side.

The CD-ROM deck 124 can open and close the tray 130 by pressing an open / close button 128. C on this tray 130
By mounting the D-ROM 102, a CD-ROM
102 can be loaded inside the device.

On the other hand, the FD deck section 126 is provided with an FD insertion throttle 132, and when the FD 104 is inserted, the drive system inside the apparatus operates to draw in the FD 104. When the FD 104 is taken out, the operation button 134 is pressed to
D104 can be pulled out.

The CD-ROM deck 124 and F
Each of the D deck units 126 has an access lamp 13
6, 138 are provided, and the access lamps 136, 138 are turned on during access in the apparatus.

Below the deck section 122, a discharge tray 140 is provided. This discharge tray 140
Is usually housed in the device, and can be pulled out by putting a finger on the grip portion 142 (FIG. 1).
reference).

The image receiving paper 108 on which the image is recorded is discharged onto the discharge tray 140.

The image receiving paper 108 is stored in a layer on a tray 144 in advance.
0 is provided in the tray loading port 146 provided on the upper surface of the tray. The image receiving paper 108 is taken out one by one from the tray 144 loaded in the tray loading port 146, the image is transferred, and then guided to the discharge tray 140.

Two circular cover members 148 and 150 are attached to the right side surface (the front side in FIG. 1) of the casing 110. The cover members 148, 150
The cover members 148, 1
As shown in FIG. 3, a supply reel 152 and a take-up reel 154 for winding the rolled photosensitive material 106 are disposed inside the apparatus 50 along the axial direction. The members 148 and 150 can be taken out or loaded with the members removed.

(Image Receiving Paper Conveying System) As shown in FIG. 3, the tray 144 loaded in the tray loading port 146 has a top end portion facing the half-moon roller 156.

The semicircular roller 156 has a part of its peripheral surface cut out in a plane parallel to the axis.
Is opposed to the uppermost image receiving paper 108 in the tray 144 at a predetermined interval. Here, half moon roller 156
Is rotated, the uppermost layer of the image receiving paper 108 comes into contact with the peripheral surface of the half-moon roller 156, and the half-moon roller 156 makes one rotation, whereby the image receiving paper 108 is slightly pulled out. The pulled-out image receiving paper 108 is nipped by the first roller pair 160, and is completely pulled out of the tray 144 by the driving force of the first roller pair 160.

On the downstream side of the first roller pair 160, a second roller
Roller pair 162, guide plate 164, third roller pair 1
66 are arranged in order, and the image receiving paper 108 is nipped by the first roller pair 160, is nipped by the second roller pair 162, is guided by the guide plate 164, and is received by the third roller pair 166. Be pinched.

The third roller pair 166 also overlaps the photosensitive material 106. That is, the third roller pair 166 is also used as a transport path for the photosensitive material 106.

(Photosensitive Material Conveying System) The photosensitive material 106 is loaded in the apparatus in a long form wound around a supply reel 152 in a layered manner. The supply reel 152 can be loaded at a predetermined position by removing the cover member 150 (on the rear side of the apparatus) and inserting the cover member 150 in the axial direction.

With the photosensitive material 106 loaded at a predetermined position, the outermost layer is pulled out and loaded along a predetermined transport path as an initial setting. In the loading procedure, the outermost layer is pulled out from the supply reel 152, and the fourth roller pair 1 near the loading position of the supply reel 152
68, via the reservoir 170 and the guide plate 172, between the third roller pair 166, around the heat roller 174, and around the take-up reel 154. In this case, a leader tape of a length necessary for loading may be provided at the leading end of the photosensitive material 106 wound around the supply reel 152.

It should be noted that in the transport path of the photosensitive material 106,
An exposure section 176 is provided between the fourth roller pair 168 and the reservoir section 170. In addition, the reservoir 170
A water application unit 178 is provided between the guide plate 172 and the guide plate 172. The details of the exposure unit 176 and the water application unit 178 will be described later. However, after the image is exposed on the photosensitive material 106 by the exposure unit 176, the third step is performed in a state where water is applied to the emulsion surface (exposed surface). Receiving paper 1 with roller pair 166 of
08 is superimposed.

(Heat Roller) The heat roller 174 is
This is a thermal development transfer section of the apparatus, and is a cylindrical roller body 18.
0, and a heater 182 provided along an axis inside the roller main body 180.
By the operation of 2, the surface of the roller body 180 is heated, and has a role of applying heat to the members (the photosensitive material 106 and the image receiving paper 108) wound around the roller body 180. By this heating, a thermal development transfer process is performed, and the image recorded on the photosensitive material 106 is transferred to the image receiving paper 108.

A peeling roller 184 and a peeling claw 186 are provided near the lower left of the heat roller 174, and the image receiving paper 108 wound around the heat roller 174 by about 1/3 is peeled off from the photosensitive material 106, and a discharge tray 140 The image receiving paper 108 is guided in the direction.

On the other hand, the photosensitive material 106 is
The take-up reel 154 is wound by about 、, is turned by 180 °, and is guided to a position where the take-up reel 154 is loaded.

(Water application section) As shown in FIG. 3, the water application section 178 is provided with water as a solvent for forming an image.
6 or the image receiving paper 108, the superposed surfaces of both are brought into close contact with each other, and have a role of thermal development.
And a tank 190 for storing water.

The coating piece 188 is made of a highly absorbent material such as felt or sponge and has an appropriate hardness.
The photosensitive material 106 comes into contact with a predetermined pressure during transportation. The water in the tank 190 always transfers an appropriate amount to the coating piece 188 by utilizing the capillary phenomenon. When the photosensitive material 106 and the coating piece 188 come into contact with each other, the water is exposed by the coating piece 188. Water is applied to the surface (emulsion side) of the material 106.

Since the coated piece 188 is in contact with the photosensitive material 106 at an appropriate pressure, the water is uniformly applied.

The water in the tank 190 is replenished by removing the entire water application section 178. However, water may always be supplied from outside the apparatus by providing a pipe.

In the first embodiment, water is used as a solvent for image formation, but this water is not limited to pure water.
Contains water in a widely and commonly used sense. Further, a mixed solvent of water and a low boiling point solvent such as methanol, DMF, acetone, and diisobutyl ketone may be used. further,
A solution containing an image formation accelerator, an antifoggant, a development terminator, a hydrophilic heat solvent, and the like may be used.

(Exposure Unit) FIG. 4 shows an exposure unit 176 according to the first embodiment.

The light exposure unit 176 mainly includes a light source unit 200 provided above the conveyance path of the photosensitive material 106.
It is connected to the controller 202. Controller 2
02 stores image data (the CD-
The image data read from the ROM 102 or the FD 104) and the full-color image forming light source unit 204 in the light source unit 200 are turned on in accordance with the image data. Note that the configuration of a portion for turning on the full-color image forming light source unit 204 in the controller 202 particularly related to the present invention will be described later.

The light source unit 200 is movable in the width direction (main scanning direction) of the photosensitive material 106 by driving a main scanning unit 206 described later.
Main scanning is performed when the exposure unit 6 stops moving the exposure unit 176 stepwise.

The light source unit 200 of the exposure unit 176 is covered by a box-shaped exposure casing 214, and a full-color image forming light source unit 204 is disposed on the upper end surface of the exposure casing 214. The light emitting surface of the portion 204 faces the opening side of the exposure casing 214. Light source unit 204 for full-color image formation
An aperture 216 provided with a rectangular opening for each emission color is disposed on the emission surface side of the R-LED emitting red (R), green (G), and blue (B) colors. Chip 208R, G-LED chip 208G, B-LED
Chip 208B (11 for each color, see FIG. 5)
Limits the spread of light from

A lens 212 is disposed downstream of the aperture 216 and at the center of the exposure casing 214 to collect light from the full-color image forming light source unit 204 and form an image near the photosensitive material 106. Have. In addition,
The resolution of the light to be imaged is about 300 to 400 dpi. Although the lens 212 is shown as a single unit on the drawing, a single lens system may be configured by combining a plurality of lenses.

Here, the lens 212 is composed of a plurality of lenses and an aperture. If the lens 212 has a characteristic that the magnification does not change even if the height of the image plane changes to some extent, the main scanning unit During the main scanning movement by the
A minute error due to the mounting state of the ED chip 208 can be absorbed.

The focus is always adjusted by an auto focus mechanism (not shown).

The light source unit 200 includes the main scanning unit 2
06 are supported by a pair of parallel guide shafts 218 that constitute a part of the reference shaft 06. This guide shaft 218
Are disposed along the width direction of the photosensitive material 106 (the direction of the arrow W in FIG. 4), and the light source unit 20 for full-color image formation is provided.
4 is movable in the width direction of the photosensitive material 106 by being guided by the guide shaft 218.

An endless timing belt 220 is provided on an exposure casing 214 of the full-color image forming light source unit 204.
Some have been fixed. This timing belt 220
Are wound around sprockets 222 located near both ends of the guide shaft 218, respectively. The rotation shaft of one sprocket 222 is connected to the rotation shaft of a stepping motor 226 via a transmission 224, and the full-color image forming light source unit 204 moves along the guide shaft 218 by the reciprocating rotation of the stepping motor 226. It is reciprocated.

The driving of the stepping motor 226 is controlled by the controller 202, and is synchronized with the step movement of the photosensitive material 106. In other words, with the photosensitive material 106 moved one step and stopped, the stepping motor 226 starts rotating, and the light source unit 204 for full-color image formation moves on the photosensitive material 106 in the width direction of the photosensitive material 106. After confirming the predetermined pulse, the full-color image forming light source unit 204 returns to the original position by rotating the stepping motor 226 in the reverse direction.
The next movement of the photosensitive material 106 is started simultaneously with the return operation of the light source unit 204 for full-color image formation.

A photodiode 228 is provided on the light output side of the light source unit 200, on the surface facing the photosensitive material 106 and near the main scanning start position, and a signal corresponding to the light amount of the light source from the light source unit 204 for full-color image formation. Is output. The photodiode 228 is connected to the light amount correction unit 230, and the signal is input to the light amount correction unit 230.

The light quantity correction unit 230 compares the detected light quantities from the LED chips 208 of the respective colors to determine the light quantity,
It has a role of performing color balance adjustment and outputting a correction value to the controller 202. Based on the correction value, the image data sent to the full-color image forming light source unit 204 is corrected, and each LED chip 208 is turned on with an appropriate light amount.

As shown in FIG. 5, the full-color image forming light source unit 204 includes a B-LED chip 208B, a GL
The ED chip 208G and the R-LED chip 208R are collectively configured and mounted on the substrate 210 along the width direction (main scanning direction) of the photosensitive material 106 according to the same arrangement rule. That is, 11 B-LED chips 208B are arranged in two rows and in a staggered manner at the right end in plan view of the substrate 210, and at the left end,
The eleven R-LED chips 208R are arranged in two rows and in a staggered manner, and the eleven G-LED chips 2
08G are arranged in two rows and in a zigzag pattern, for a total of 6
Rows of LED chips are arranged.

A predetermined wiring is formed on the substrate 210 by an etching process or the like. The wiring is covered with a metal so as not to short-circuit between the wirings, and has a heat radiation function. For this reason, heat generation due to lighting of the LED chip 208 can be suppressed, and fluctuation of the light emission amount can be suppressed. Note that the outer dimensions (x × y) of the LED chip 208 are about 36
It is 0 × 360 μm.

By the way, as shown in FIG.
The pitch P between rows of the same color (the pitch in the main scanning direction) P of the same color of the LED chip 208 to be mounted at 0 is 600 μm, the row pitch L of each column (the pitch in the sub-scanning direction) L is 520 μm, It is preferable that the dimension D is 260 μm, and the gap dimension G between the colors is the same between R and G and between G and B. Note that the hatched portion of the LED chip 208 shown in FIG. 5 is a region that actually emits light, and the boundaries of the light emitting regions between adjacent rows in the staggered LEDs of the same light emitting color are matched.

Light source 2 for full-color image formation having the above structure
According to 04, 11 main scanning lines can be recorded on the photosensitive material 106 by one main scanning for each color.
Note that the interval between the main scanning line pitches is an even number of 10.

Here, in the first embodiment, as shown in FIG. 6, the step movement of the photosensitive material 106 is
6, the sub-scanning drive and the stop are repeated at a pitch (5.5 line pitch) at which the first main scanning line of the present time recorded on the line 6 comes to an intermediate position of the main scanning line between the previous sixth and seventh times. Is controlled. In FIG. 6, the thin solid lines are the eleven main scanning lines formed by the previous main scanning, the chain lines are the eleven main scanning lines formed by the current main scanning, and the thick solid line is the next main scanning line. 11 main scanning lines formed by main scanning.

As described above, by using an odd number of LED chips 208, the number of main scanning lines is set to an even number (that is, 10 intervals), and half of the main scanning lines are further formed. The resolution is doubled. As described above, the LED chips 208 are odd for each emission color, the LED chips 208 are spaced at even intervals, and the scanning lines are formed in half of the main scanning lines. it can.
In addition, the first to fifth main scanning lines at the time of the first main scanning drive are not written for control.

Next, with reference to FIG. 7, the structure of a portion for turning on the full-color image forming light source unit 204 in the controller 202, which is particularly related to the present invention, will be described in detail.

The controller 202 has an image memory 10 for temporarily storing input image data.
An output terminal of the image memory 10 receives an input of a look-up table (hereinafter, referred to as an LUT) 12 as a conversion means constituted by a memory in which a conversion table for converting input image data according to a predetermined rule is stored in advance for each channel. The output terminal of the LUT 12 is connected to an input terminal of a DA converter 32 that converts a digital signal for one channel into an analog signal.

The conversion table stored for each channel in the LUT 12 includes, for example, two-digit hexadecimal input data ('00' to 'FF') as shown in FIG.
Is output data of 3 digits of hexadecimal number ('000' to 'FF
F ′). The conversion at this time is performed by changing the input / output characteristics of the DA converter 32 so that the output voltage from the DA converter 32 is proportional to the input data of the DA converter 32, that is, the output data of the LUT 12, as shown in FIG. Accordingly, for example, as shown in FIG. 9A, LUTs near the minimum value and near the maximum value of the input data of the LUT 12
The twelve output data ranges X1 are set to be larger than the output data range X2 around the center value of the input data. In the following description, it is assumed that the conversion table shown in FIG. 9A is stored in advance as a conversion table corresponding to each channel in the LUT 12.

The output terminal of the DA converter 32
Is added to the output of the DA converter 32.
The addition point from the offset addition circuit 14 as an arithmetic circuit is
Via the LED chip 208 in the first embodiment.
33), each of which is an analog switch.
Switch 34_n(N is 1 to N, N = 3 in the first embodiment.
3, the same applies hereinafter) to one end of the switch unit,
Each analog switch 34 _nThe other end of the switch
Densa 36_nOne end of the buffer amplifier 38_nNon-anti
Connected to the input terminal. The capacitor 36_nof
The other end is grounded.

[0078] On the other hand, the inverting input terminal of the output terminal of the buffer amplifier 38 _n The buffer amplifier 38 _n, and is connected to one end of the switch portion of the analog switches 40 _n, the other end of the switch portion of the analog switch 40 _n capacitors 42
_n one end of, and is connected to the non-inverting input terminal of the buffer amplifier 44 _n. The other end of the capacitor 42 _n is grounded.

[0079] On the other hand, the output terminal of the buffer amplifier 44 _n is connected to the inverting input terminal of the buffer amplifier 44 _n, to form an output terminal of the full-color image forming light source unit 204 of the controller 202 (1ch~Nch) And
Each output terminal is a full-color image forming light source unit 20 shown in FIG.
4 are connected to the 33 LED chips 208 respectively. (A connection line from each output terminal to each LED chip 208 is not shown.) Further, each switch switching input terminal of the analog switch 34 _n is connected to an output terminal of a sampling signal 46 A corresponding to each channel of the timing generation circuit 46. Each of the switches is connected, and each switch switching input terminal of the analog switch 40 _n is connected to the same output terminal of the sampling signal 46B of the timing generation circuit 46.

As described above, the first-stage sample-and-hold circuit is constituted by the analog switch 34 _n , the capacitor 36 _n , and the buffer amplifier 38 _n by the analog switch 4 _n .
0 _n , the capacitor 42 _n , and the buffer amplifier 44 _{n form a} second-stage sample-hold circuit. Therefore, due to the effects of the buffer amplifiers 38 _n , 44 _n provided in the sample-hold circuits of each stage, the output terminals of the second-stage sample-hold circuits of the respective channels,
That is, the output terminal (1) to the light source unit 204 for full-color image formation
(ch to Nch), different offset voltages are generated. In order to set the offset voltage to 0 V (cancel), in the first embodiment, the offset adding circuit 14 adds a predetermined voltage to the output of the DA converter 32 and rewrites the conversion table for each channel of the LUT 12. However, the details will be described later. The LUT 12, the offset addition circuit 14, the DA converter 32, the two-stage sample-and-hold circuit corresponding to the number of channels, and the timing generation circuit 46 correspond to the multi-channel digital / analog converter of the present invention.

The controller 202 is connected to the light amount correction unit 230 and the image memory 10 and corrects the image data stored in the image memory 10 based on the correction value input from the light amount correction unit 230.
Is provided.

The CPU 16 is further connected to the stepping motor 226, the timing generation circuit 46, and the LUT 12, and controls the stepping movement of the light source unit 204 for full-color image formation, and controls the timing generation circuit 46 by one pixel in the main scanning direction. The output of the pixel clock signal 16A (see FIG. 8) indicating one cycle when the image is recorded, the rewriting of the conversion table of each channel of the LUT 12, and the like are performed.

The timing generation circuit 46 is further connected to the image memory 10, and outputs the image data stored in the image memory 10 to the DA converter 32 via the LUT 12 based on the pixel clock signal 16 A input from the CPU 16. Enter Therefore, the timing generation circuit 46 corresponds to the input means of the present invention.

The analog switches 34 _n , 40
_{As n} , an FET switch, a reed relay, or the like can be applied.

(Reservoir Section) The reservoir section 170 is disposed between the exposure section 176 and the water application section 178 as described above, and has two pairs of nipping rollers 192 and 194 and one dancer roller 196. It is composed of Photosensitive material 1
Reference numeral 06 is stretched over two pairs of nipping rollers 192 and 194, and a substantially U-shaped slack is provided in the photosensitive material 106 between them. In response to this slack, dancer roller 196
Of the photosensitive material 10 at the slack portion.
6 is held.

In the exposure unit 176, the photosensitive material 106 moves stepwise, but in the water application unit 178, it is necessary to convey the photosensitive material 106 at a constant speed for uniform application of water. For this reason,
The photosensitive material 106 is disposed between the exposure unit 176 and the water application unit 178.
The difference in the conveying speeds is caused. To absorb this speed difference,
The dancer roller 196 is moved up and down to adjust the amount of slack in the photosensitive material 106 so that the photosensitive material 106 can be moved stepwise and at a constant speed.

The operation of the first embodiment will be described below.
In the first embodiment, in order to cancel the offset voltage of the two-stage sample and hold circuit of each channel, the DA converter 3 by the offset addition circuit 14 is used.
2 and a predetermined voltage is added to the output of LU2.
The conversion table corresponding to each channel of T12 is rewritten in advance for each device, and the details will be described later. First, the overall flow for image recording will be described.

The tray 144 is loaded in the tray loading port 146, and the supply reel 152 with the photosensitive material 106 wound thereon and the empty take-up reel 154 are loaded at predetermined positions, respectively, and the loading is completed. When the print start key of the operation display unit 112 is operated, the controller 202 causes the CD-ROM 102 or the FD 10
4 is read out and stored in the image memory 10.

When the controller 202 stores the image data, the supply reel 152 is driven, and the conveyance of the photosensitive material 106 is started.

When the photosensitive material 106 reaches a predetermined position of the exposure unit 176, the photosensitive material 106 stops temporarily, and image data is output from the controller 202 to the full-color image forming light source unit 204. This image data is output every 11 lines, and the full-color image forming light source unit 204 is guided by the guide shaft 218 by the driving of the stepping motor 226 and moves along the width direction of the photosensitive material 106 (main scanning).

Before the output of the image data is started, the light amount of each color from the light source unit 204 for full-color image formation is detected by the photodiode 228, and the light amount correction unit 230 adjusts the light amount and color balance. The correction value is supplied to the CPU 16 of the controller 202,
The image data has been corrected. This correction is performed for each image.

As shown in FIG. 6, when one main scan is completed, the photosensitive material 106 moves one step (5.5 line pitch) and stops, and the second main scan is performed. By repeating this, an image for one frame is recorded on the photosensitive material 106. That is, the LED chip 20
The main scanning lines are formed at a half pitch of the arrangement pitch of 8, and the resolution is improved. In this case, up to five lines from the top in the first main scanning driving on one screen and five lines from the bottom in the last main scanning driving are unexposed (LED chip 20).
8 is turned off).

The photosensitive material 106 on which recording has been completed is
By driving only the pair of holding rollers 192 on the upstream side of the reservoir 170 (the pair of holding rollers 194 on the downstream side is stopped),
It is held in a slack state in the reservoir section 170 so as to be wound around the dancer roller 196, and does not reach the water application section 178.

When the length of the photosensitive material 106 corresponding to one image is accumulated in the reservoir 170, the pair of nipping rollers 194 on the downstream side of the reservoir 170 starts driving. As a result, the photosensitive material (image recorded) 106 is transported to the water application unit 178. In the water application section 178, the photosensitive material 106 is conveyed at a constant speed, and water is uniformly applied by the application piece 188.

The coating piece 188 is constantly supplied with water from the tank 190, and is supplied with the photosensitive material 10 at a predetermined pressure.
6 is pressed, an appropriate amount of water is applied to the photosensitive material 106.

The photosensitive material 106 to which water has been applied is guided by a guide plate 172 and conveyed to a third roller pair 166.

On the other hand, the image receiving paper 108 is a half moon roller 156.
Makes one rotation, the peripheral surface of the half-moon roller 156 and the leading end of the image receiving paper 108 come into contact with each other, and the uppermost layer of the image receiving paper 108
Is pulled out and nipped by the first roller pair 160. The driving of the first roller pair 160 causes the image receiving paper 108
Is pulled out of the tray 144 and the second roller pair 162
Wait for the photosensitive material 106 to arrive.

The driving of the first roller pair 160 and the second roller pair 162 is started in synchronization with the passage of the photosensitive material 106 through the guide plate 172, and the image receiving paper 108 is guided by the guide plate 164. It is conveyed to the third roller pair 166.

In the third roller pair 166, the photosensitive material 10
6 and the image receiving paper 108 are pinched in a superposed state, and sent out to the heat roller 174. At this time, the photosensitive material 10
Both are brought into close contact with each other by the water applied to 6.

The superposed photosensitive material 106 and the image receiving paper 108 are wound around a heat roller 174, receive heat from a heater 182, and undergo a thermal development transfer process. That is, the image recorded on the photosensitive material 106 is transferred to the image receiving paper 108 and visualized.

The heat development transfer is completed when the heat roller 174 is wound about 1/3, and the image receiving paper 108 is
The photosensitive material 1 is separated by the peeling roller 184 and the peeling claw 186.
, And is discharged onto a discharge tray 140 so as to be wound around a peeling roller 184.

On the other hand, the photosensitive material 106 is a heat roller 1
After being wrapped about 1/2 by 74, it moves tangentially and is taken up by the take-up reel 154.

Next, the operation of the controller 202 when the full-color image forming light source unit 204 is turned on will be described with reference to the circuit diagram of FIG. 7 and the time chart of FIG.

First, the DA by the offset adding circuit 14
The operation of adding a predetermined voltage to the output of converter 32 is started.

Next, the timing generation circuit 46
When the pixel clock signal 16A input from the H. 16 becomes high level (see FIG. 8), the pixel clock signal 16A
In each section obtained by dividing one cycle of N by time division (division into the number of channels), a sampling signal 46A in which the analog switch 34 _n corresponding to each channel is turned on in the order of channels is generated, and each analog signal of the sampling signal 46A is generated. The application to the switch 34 _n is started. At the same time, the timing generation circuit 46 starts applying the timing signal 46B generated so as to turn off the analog switch 40 _n for one cycle of the pixel clock signal 16A to the analog switch 40 _n . The analog switches 34 _n and 40 _n used in the first embodiment are:
It is turned on when the signal applied to the switch switching input terminal is at a low level.

[0106] When applied to the switch switching input end of the analog switches 40 _n of the applied and the sampling signal 46B to the switch switching input end of the analog switches 34 _n of the sampling signal 46A is started, the timing generation circuit 46, DA from the image memory 10 via the LUT 12
Input of image data for N channels to the converter 32, that is, image data for causing the N LED chips 208 provided in the full-color image forming light source unit 204 to emit light is started. At this time, the input of the image data of each channel falls within a period in which the sampling signal 46A corresponding to each channel is at a low level, that is, a period in which the analog switch 34 _n is turned on, as shown in FIG. it is divided into each channel to enter over a period that can sample and hold the image data of each channel to the capacitor 36 _n corresponding to the channel. At this time, the image data of each of the N channels input to the DA converter 32 is converted by the conversion table stored for each channel in the LUT 12.

[0107] or more is applied to the switch switching input end of the analog switches 34 _n of the sampling signal 46A, and the input to the DA converter 32 of the image data, a capacitor 36 _n that are connected to the analog switches 34 _n
In FIG. 8, the voltage corresponding to the image data of each channel is sampled, and the output voltage of each buffer amplifier 38 _n connected to each capacitor 36 _n , that is, the output voltage of the first stage sample and hold circuit is shown in FIG. As shown, the rising starts almost simultaneously with the input of the image data of each channel to the DA converter 32, and when the application of the low level of the sampling signal 46A corresponding to the Nth channel is completed, the image data of all the channels is The corresponding output voltage is held.

[0108] Then, the timing generating circuit 46, the sampling signal 46B state for turning on the analog switches 40 _n, i.e. a low level.

[0109] sampling signal 46B is the analog switches 4 to be turned on in this way the analog switch 40 _n
When the signals are simultaneously applied to all the switch switching input terminals 0 _n , the outputs at the output terminals of the buffer amplifiers 44 _n , that is, the output terminals of the sample-hold circuits of the second stage are simultaneously started. Accordingly, each LED chip 208 connected to the output end of each of the buffer amplifier 44 _n, the signal is applied corresponding to the image data at the same time.

[0110] Then, the timing generating circuit 46, by turning off the analog switches 40 _n sampling signals 46B to the high level, after completion of the sample-hold operation of the sample-and-hold circuit of the second stage, the next image data The sample-hold operation for the first-stage sample-hold circuit is started.

Next, the offset addition circuit 14 adds a predetermined voltage to the output of the DA converter 32 and cancels the offset voltage of the two-stage sample-hold circuit of each channel. The rewriting of the conversion table to be performed will be described in detail. First, D by the offset adding circuit 14
The addition of the predetermined voltage to the output of the A converter 32 will be described.

In the first embodiment, the predetermined voltage to be added to the output of the DA converter 32 by the offset adding circuit 14 is added to obtain a predetermined voltage among the offset voltages of the two-stage sample and hold circuits of each channel. The maximum offset voltage (hereinafter, referred to as the maximum offset voltage) is a voltage that can be set to 0 V (canceled). Therefore, the addition of the predetermined voltage by the offset addition circuit 14 is performed by, for example, applying a predetermined voltage not less than the maximum offset voltage to the output of the DA converter 32 in reverse polarity and in series. As a method of determining the predetermined voltage at this time, for example, a maximum voltage which can be generated as an offset voltage of a two-stage sample-and-hold circuit in the controller 202 obtained empirically is applied.
Alternatively, there is a method of actually detecting the offset voltage of each of the two-stage sample and hold circuits corresponding to each channel in the controller 202, and applying the maximum value of the detected offset voltage.

As a method of determining the predetermined voltage, each offset voltage of each of the two-stage sample-hold circuits corresponding to each channel is actually detected, and the maximum value of the detected offset voltage is applied to each channel. As a method of detecting the offset voltage, for example, all the analog switches 34 _n and 40 _n are turned on and the DA converter 32 does not add a predetermined voltage to the output of the DA converter 32 by the offset adding circuit 14. 3
Input '0' for 2 and 2 of each channel at that time
There is a method of detecting the output voltage of the sample-hold circuit at the stage and using the detected output voltage as an offset voltage of each channel.

Next, rewriting of the conversion table corresponding to each channel in the LUT 12 will be described.

First, the offset voltage of each of the two-stage sample and hold circuits corresponding to each channel is detected.

Next, DA is added by the offset adding circuit 14.
A predetermined voltage is added to the output of the DA converter 32 by the offset adding circuit 14 based on the predetermined voltage applied to the output of the converter 32 and the detected offset voltage of the two-stage sample and hold circuit of each channel. Thus, the contents of the conversion table of each channel stored in the LUT 12 are rewritten such that the offset voltages of the two-stage sample-hold circuits of each channel are canceled.

For example, the offset adding circuit 14
The predetermined voltage applied to the output of the A converter 32 is −50.
mV, and the offset voltage of each sample and hold circuit of each channel is 50 m, as shown in FIG.
V, 30 mV,..., The output of the DA converter 32 from the offset adding circuit 14 is always -5.
0 mV is applied, thereby canceling the offset voltage (50 mV) of the first channel.
There is no need to change the contents of the conversion table corresponding to the first channel of T12. Therefore, the conversion table corresponding to the first channel is not rewritten in the state shown in FIG.

As a result, the output voltage of the second-stage sample-hold circuit of the first channel is proportional to the size of the input data to the DA converter 32 as shown in FIG. In this case, the output voltage is 0 V, and the input data is the maximum value (in the first embodiment, hexadecimal 'FF
F ') the maximum voltage V _max becomes output voltage in the case of, becomes the offset voltage is not generated. In this case, L
As shown in FIG. 9C, the drive current of the ED chip 208 increases in proportion to the output voltage of the second-stage sample and hold circuit of the first channel, that is, the input voltage of the LED chip 208, when the input voltage is the maximum voltage V _max, the drive current of the LED chip 208 is made to be maximum drive current I _max is the maximum allowable current of the LED chip 208.

On the other hand, the offset voltage of the second channel is 30 mV, and the addition of −50 mV to the output of the DA converter 32 by the offset adding circuit 14 causes −20 mV to be applied to the output of the second stage sample and hold circuit.
Since an offset voltage of V is generated, in order to cancel the offset voltage, as shown in FIG. 11A, the conversion table corresponding to the second channel in the LUT 12 is converted to the output voltage of the DA converter 32. Rewrite so that the minimum value is 20 mV.

As a result of this rewriting, the output voltage of the second-stage sample-hold circuit of the second channel changes to the level shown in FIG.
As shown in FIG. 9B, the input data of the DA converter 32 is reduced by 20 mV as compared with the case where the conversion table shown in FIG.
If the embodiment is a hexadecimal number 'FFF'), 20mV lower than the maximum voltage V _max. Thus, the maximum voltage applied to the LED chip 208, 20 mV lower than the maximum voltage V _max, as shown in FIG. 11 (C), the maximum drive current of the LED chip 208 is the maximum drive current when not rewrite the conversion table I _Although slightly smaller than _max , as shown in FIG.
When a current I _Dmin smaller than the maximum drive current I _max is input, the density of an image recorded on the photosensitive material 106 is the minimum density D _min (in the case of a positive photosensitive material, in the case of a negative photosensitive material, with output power W _{Dm in} which is the maximum concentration) reference (FIG. 12 (B)), LED
Even if the maximum drive current of the chip 208 slightly decreases, the image quality does not deteriorate.

As described above, the rewritten LUT 12
Of the image data by the conversion table corresponding to the second channel of and -50 m by the offset adding circuit 14
As a result of the addition of V, the offset voltage 30 mV of the sample and hold circuit of the second channel is canceled.

Similarly, the conversion tables corresponding to channels 3 to N in the LUT 12 are rewritten so that the offset voltage of the sample and hold circuit of each channel can be canceled as a result.

As described above in detail, the multi-channel D / A converter according to the first embodiment uses the D / A converter 3 by the offset addition circuit 14 based on the offset voltage of each channel's sample and hold circuit.
2 and the image data for each channel to be input to the DA converter 32 such that the offset voltage of each sample and hold circuit of each channel is canceled by the application of the predetermined voltage. Since the conversion is performed by the LUT 12, generation of an offset voltage of the output of each channel can be prevented.

In the first embodiment, the addition of the predetermined voltage by the offset adding circuit 14 is performed by the DA converter 32.
Has been described, but the present invention is not limited to this, and may be a form in which addition is performed for each output of the sample and hold circuit of each channel.

In the first embodiment, the case where the predetermined voltage applied by the offset adding circuit 14 is a voltage that can cancel the maximum offset voltage of each offset voltage of the sample and hold circuit of each channel will be described. However, the present invention is not limited to this, and the maximum offset voltage may be a voltage that cannot be completely canceled. In this case, the input to the DA converter 32 based on the conversion table of the channel of the LUT 12 is performed. The offset voltage is canceled by the conversion of the image data.

Furthermore, in the first embodiment, a case has been described where the predetermined voltage to be added by the offset adding circuit 14 is set in advance for each device and the conversion table of each channel in the LUT 12 is rewritten. However, the present invention is not limited to this. For example, it may be performed every time image recording is performed.

[Second Embodiment] Next, a second embodiment of the present invention will be described. In the second embodiment, the invention described in claim 4 will be described.

The structure of the controller 202 of the image recording apparatus according to the second embodiment other than the portion for turning on the light source unit 204 for full-color image formation, and the entire flow for image recording are the same as those of the first embodiment. Therefore, the description is omitted here, and the controller 202 according to the second embodiment is omitted.
The configuration of the portion that turns on the full-color image forming light source unit 204 in the inside will be described with reference to FIG. In FIG. 13, the same components as those in the first embodiment shown in FIG. 7 are denoted by the same reference numerals, and description thereof will be omitted.

The configuration of the part for turning on the full-color image forming light source unit 204 in the controller 202 of the second embodiment is such that the LUT 12 stores digital data to be input to the DA converter 33 in a storage area other than the conversion table. LUT 12A as a means, no offset adding circuit 14, and DA converter 33 as a second digital / analog converter for generating a voltage for canceling the offset voltage of each channel is added. , And that the timing generation circuit 46 is also connected to the LUT 12A. The DA converter 3
3 is connected to the output terminal of the LUT 12, and D
The output terminal of the A converter 33 is connected to an addition point for the output of the DA converter 32.

The LUT 12A according to the second embodiment has the configuration shown in FIG.
In addition to the conversion table shown in (A), digital data (D) that causes the D / A converter 33 to generate a voltage that is applied to the output of the D / A converter 32 to cancel the offset voltage of each sample / hold circuit of each channel. (Hereinafter referred to as cancel data) is stored in advance for each channel, and the cancel data corresponding to the channel is transmitted from the LUT 12A to the DA converter 33 in synchronization with the timing at which the image data corresponding to each channel is input to the DA converter 32. , A voltage is generated by the DA converter 33 and applied to the output from the DA converter 32, thereby canceling each offset voltage of the sample and hold circuit of each channel. Therefore, in the second embodiment, the conversion table in the LUT 12 does not need to be prepared for each channel, and does not consider the offset voltage of the sample-and-hold circuit. For example, one basic table as shown in FIG. I just need to get it.

The cancel data may be, for example, digital data capable of causing the DA converter 33 to generate a voltage substantially equal to the offset voltage of each of the two-stage sample and hold circuits of each channel. May be applied to the output of the DA converter 32 in reverse polarity and in series. Also,
In the second embodiment, the input of the image data corresponding to each channel to the DA converter 32 and the input of the cancel data corresponding to the channel synchronized with the timing of the input from the LUT 12A to the DA converter 33 are performed at the timing. This is performed by the generation circuit 46. Therefore, the timing generation circuit 46 corresponds to the first and second input means of the present invention.

As described in detail above, the multi-channel D / A converter according to the second embodiment has a voltage applied to the output of the D / A converter 32 to cancel each offset voltage of the sample and hold circuit of each channel. Is generated and added to the output of the DA converter 32, so that it is possible to prevent the generation of an offset voltage of the output of each channel, which is the same effect as in the first embodiment, and to store a conversion table for each channel. Since there is no LU, compared to the first embodiment, LU
This has the effect that the storage capacity of T12 can be reduced.

In the second embodiment, the case where the addition of the predetermined voltage by the DA converter 33 is performed on the output of the DA converter 32 has been described. However, the present invention is not limited to this. May be added to each output of the sample and hold circuit.

In the second embodiment, the case where the cancel data is stored in the empty area of the LUT 12A has been described. However, the present invention is not limited to this, and a storage unit other than the LUT 12A is newly provided. Then, the information may be stored in the storage means.

[0135]

According to the first aspect of the present invention, the multi-channel digital /
According to the analog converter, since a voltage for canceling the offset voltage of each of the plurality of sample and hold circuits is added, the effect of preventing the generation of the output offset voltage can be obtained.

According to the multi-channel digital / analog converter according to the second and third aspects, the predetermined voltage is applied to the output of the digital / analog converter, and the plurality of sample-and-hold circuits are applied by applying the predetermined voltage. Since the digital signal for each channel input to the digital / analog converter is converted so that each of the offset voltages is canceled, generation of an output offset voltage can be prevented.

Further, according to the multi-channel digital / analog converter of the fourth aspect, the first digital / analog converter
In synchronization with the input of the digital signal for each channel to the analog converter, the voltage at which the offset voltage of each of the plurality of sample and hold circuits corresponding to each channel is canceled by the second digital / analog converter is changed to the first digital / analog signal. Since it is added to the output of the analog converter, the effect of preventing the generation of an offset voltage of the output can be obtained.

[Brief description of the drawings]

FIG. 1 is a perspective view of an image recording apparatus according to an embodiment.

FIG. 2 is a front view of the image recording apparatus according to the present embodiment.

FIG. 3 is a side sectional view showing an internal configuration of the image recording apparatus according to the embodiment.

FIG. 4 is a front view illustrating a schematic configuration of an exposure unit.

FIG. 5 is a plan view showing an arrangement state of LED chips in a light source unit.

FIG. 6 is a plan view of a photosensitive material showing a state of a main scanning line and a sub-scanning pitch.

FIG. 7 is a circuit diagram showing a circuit configuration of a portion for turning on a light source unit in the controller according to the first embodiment.

FIG. 8 is a time chart for explaining the operation of the controller 202;

9A is a graph showing an example of a relationship between input data and output data in a conversion table of a lookup table, and FIG. 9B is a graph showing a relationship between input data of a DA converter and output voltages of respective channels; FIG.
(C) is a graph showing the relationship between the voltage input to the LED chip and the LED drive current.

FIG. 10 is a graph showing an example of an offset voltage of a sample and hold circuit of each channel.

FIG. 11A is a graph showing a relationship between input data and output data in a rewritten conversion table;
(B) is a graph showing the relationship between the input data of the DA converter and the output voltage of each channel at that time, and (C).
Is a graph showing the relationship between the voltage input to the LED chip and the LED drive current at that time.

12A is a graph showing a relationship between LED drive current and LED output power, and FIG. 12B is a graph showing a relationship between LED output power and density of an image recorded on a photosensitive material.

FIG. 13 is a circuit diagram showing a circuit configuration of a portion for turning on a light source unit in a controller according to the second embodiment.

FIG. 14 is a circuit diagram showing a circuit configuration of a conventional multi-channel DA converter.

[Explanation of symbols]

Reference Signs List 12 lookup table (conversion means) 12A lookup table (storage means) 14 offset addition circuit (addition circuit) 32 DA converter (first digital / analog converter) 33 DA converter (second digital / analog converter) 46 timing Generation circuit (input means, first and second input means)

Claims (4)

[Claims] A digital / analog converter for converting a digital signal of one channel into an analog signal; input means for dividing and inputting digital signals of a plurality of channels into the digital / analog converter for each channel; A plurality of sample-and-hold circuits respectively connected in parallel to an output terminal of the converter, each of which samples and holds an analog signal for each channel output from the digital / analog converter; and an offset voltage of each of the plurality of sample-and-hold circuits And a multi-channel digital / analog converter comprising: 2. A digital / analog converter for converting a digital signal of one channel into an analog signal; input means for dividing a digital signal of a plurality of channels into the digital / analog converter for each channel and inputting the digital / analog; A plurality of sample-and-hold circuits respectively connected in parallel to the output terminals of the converters, each of which samples and holds an analog signal for each channel output from the digital / analog converter, and a predetermined voltage to the output of the digital / analog converter An adding circuit to be added; and a converter for converting a digital signal for each channel input to the digital / analog converter so that the offset voltage of each of the plurality of sample and hold circuits is canceled by applying the predetermined voltage. Multi-channel digital / analog converter with the means. 3. The multi-channel digital / analog converter according to claim 2, wherein the predetermined voltage is a voltage for canceling a maximum offset voltage among offset voltages of the plurality of sample and hold circuits. 4. A first digital / analog converter for converting a digital signal of one channel into an analog signal, and a first digital signal for dividing a plurality of channels into the first digital / analog converter for each channel. And a plurality of samples respectively connected in parallel to the output terminals of the first digital / analog converter, and each of which samples and holds an analog signal for each channel output from the first digital / analog converter. Hold circuit and convert 1 channel digital signal to analog signal,
A second digital / analog converter for adding the analog signal to an output of the first digital / analog converter; and a second digital / analog converter for applying the analog signal to an output of the first digital / analog converter to thereby provide a signal to each of the plurality of sample and hold circuits. Storage means for storing, for each channel, digital data for causing the second digital / analog converter to generate a voltage at which the offset voltage is canceled; and synchronizing with input of a digital signal for each channel to the first digital / analog converter. And a second input unit for inputting the digital data for each channel stored in the storage unit to the second digital / analog converter.