JPH10321879A - Silicon carbide diode - Google Patents

Abstract

(57) [Problem] To provide a diode with improved reverse characteristics and reduced loss during forward conduction, capable of high-speed response and low loss. A on the high impurity concentration n ⁺ semiconductor substrate 3 comprises an n-type layer 2 of a low impurity concentration, and the surface of the n-type layer 2, a predetermined depth L _P at a predetermined width W _P a plurality of high impurity concentration p ⁺ -type region 1A having a predetermined interval W _S, further, the anode electrode 4 is provided on the entire surface of the n-type layer 2 and the p ⁺ -type region 1A, thereby, the n-type layer 2 A Schottky junction is formed at the junction of the anode electrode 4, and an electrical connection between the Schottky junction and the p ⁺ -type region 1 A is obtained by the anode electrode 4. Concentration p ⁺ type region 1A
Is made into a horizontally long oval cross section, and the interval W _S between them is
Is located at a predetermined distance L _S from the substrate surface to the inside. [Effect] The resistance at the time of forward conduction can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device using silicon carbide, and more particularly to a silicon carbide diode suitable for use in combination with a power diode or transistor for switching a large current at high speed. About.

[0002]

2. Description of the Related Art In a power conversion device such as a voltage type inverter, a power diode for rectification, commutation, or formation of a return path is used together with a switching element. FIG. 4 shows an example of a main circuit of a voltage-type inverter. Six power transistors 101 (Tr1) to 106 (Tr6) serving as switching elements are respectively connected to return diodes 111 (D1) to 116 (116). D6) are provided in anti-parallel to convert the DC power supplied between the input terminals 221 and 222 into three-phase AC power and supply it to the induction motor 120 (IM) serving as a load. is there.

If the transistor 102 is turned on while a return current is flowing through the diode 111 from the induction motor 120, a reverse recovery mode occurs in the diode 111. _D , voltage V _D , and current I of transistor 102
_T and the voltage V _T is as shown in FIG. 5, respectively.

That is, the current I of the diode 111
_D is the turn-on of transistor 102 at time t _0, the change rate dI / d of the current I _T of the transistor 102
It decreased from the current value I _F at the same inclination in t opposite direction to reverse recovery. At this time, since the reverse recovery current Irr of the diode 111 is superimposed on the transistor 102, the turn-on loss is larger than in the case of the operation of the transistor alone.

At the time of reverse recovery, the voltage induced by the parasitic inductance L existing in the inverter circuit is superimposed on the reverse bias voltage of the diode 111 due to the current change rate dI / dt of the diode 111. ,
The voltage at this time is the diode 111 or the transistor 10
If the blocking voltage exceeds 1, the devices will be destroyed. In order to solve these difficulties, it is necessary to suppress the reverse recovery current Irr of the diode to a small value and to reduce the rate of change dIr / dt of the reverse recovery current.

In general, a diode having a pn ⁻ n ⁺ structure as shown in FIG. 6A is generally used as such a power diode, but as described above, the reverse recovery characteristic is improved. If desired, the diode
Conventionally, a Schottky diode shown in FIG. Here, n ⁻ represents an n-type layer having a low impurity concentration, and n ⁺ represents an n-type layer having a high impurity concentration. FIG. 6 (a),
In the diode shown in FIG. 1B, a low impurity concentration n-type layer 2 is deposited on a low resistance (high impurity concentration) n ⁺ semiconductor substrate 3 by epitaxial growth in consideration of a breakdown voltage, and then a high impurity concentration p ⁺ Type region 1 or high impurity concentration p ⁺
Forming a guard ring region 8 made of a mold layer;
And an anode electrode 4 are provided. Reference numeral 5 denotes a cathode electrode.

[0007] Figure 7 shows the reverse recovery current characteristics of the two diodes, a current characteristic of the diode I D _(a) is shown in FIG. _{6 (a), I D (} b) in FIG. FIG. 6B shows the current characteristics of the Schottky diode shown in FIG. 6B. As is clear from FIG. 7, the Schottky diode shown in FIG.
It can be seen that the reverse recovery current Irr is smaller than that of the diode having the pn ⁻ n ⁺ structure shown in FIG. 6A, and that the switching performance is improved. However, as described below, the forward characteristic is lower. It will be sacrificed.

The diode having the pn ⁻ n ⁺ structure shown in FIG.
When forward biased, high impurity concentration p ⁺ -type region 1
Then, holes, which are minority carriers, are injected into the low impurity concentration n-type layer 2. The injected holes cause conductivity modulation in the low-impurity-concentration n-type layer 2, which is a high-resistance layer, improving conductivity during forward conduction and lowering forward resistance.

On the other hand, the Schottky diode shown in FIG. 6B obtains diode characteristics by contact between a metal and a semiconductor, so that majority carriers dominate the rectification characteristics.
As a result, there is no carrier accumulation effect due to minority carriers. As a result, high-speed response characteristics can be obtained. However, since there is no minority carrier injection, conductivity modulation does not occur and the forward resistance decreases. Cannot be obtained.

For example, while the forward voltage of a pn ^- n ⁺ structure diode with a withstand voltage of 5 kV is 3 V, the Schottky diode also has a forward voltage of about 300 V. In this case, a pn ^- n ⁺ structure diode has That is, the resistance is reduced by about two digits due to the conductivity modulation.

By the way, as long as silicon is used as a semiconductor material, it is impossible to reduce the resistance of the Schottky diode when conducting in the forward direction. For this reason, silicon carbide has recently been used as a semiconductor material other than silicon. Attracting attention. Silicon carbide (silicon carbide) has a maximum electric field strength that is at least one order of magnitude greater than that of silicon, and the resistance during forward conduction can be reduced by about two orders of magnitude.

For example, a silicon carbide Schottky diode having a withstand voltage of 5 kV has a forward voltage of about 2 V and a p-type voltage of silicon.
It becomes lower than 3V of the diode of the n ^- n ⁺ structure. Therefore,
By forming the Schottky diode with silicon carbide, both the reverse recovery characteristic and the forward characteristic can be improved. However, the Schottky diode has the disadvantage that the reverse current is large and the temperature characteristics are poor.

Here, generally, in order to reduce the reverse current of the Schottky diode and improve the temperature characteristics, a barrier metal having a high barrier height may be used. However, when a barrier metal having a high barrier height is used, the forward rise voltage increases, and the forward loss increases. As described above, since there is a trade-off relationship between the forward characteristic and the backward characteristic of the Schottky diode, there is a limit in improving the characteristics by controlling the barrier height.

Further, the Schottky diode has a Schottky effect in which the Schottky barrier height is reduced when the electric field strength at the interface between the semiconductor and the metal is increased. There is an essential problem that the current increases,
Therefore, in order to improve the characteristics of the Schottky diode, use a barrier metal with a small barrier height,
It was necessary to relax the electric field strength at the Schottky junction interface so that the reverse leakage current did not increase.

Therefore, in recent years, as a method for remedying the above-mentioned disadvantages of the prior art, a pn junction is arranged around a Schottky diode, and when a reverse bias is applied to the diode, the pn junction is formed at the Schottky junction interface. Some methods have been proposed to extend the depletion layer from the substrate, relax the electric field strength at the Schottky junction interface, and reduce the reverse current.

Therefore, as one example, Japanese Patent Laid-Open No.
The Schottky diode proposed in Japanese Patent No. 6015 will be described with reference to FIG. Schottky diode shown in FIG. 2, first as in the conventional example of FIG. 6, the low resistance n ⁺ semiconductor substrate 3 having a cathode electrode 5
An n-type layer 2 having a low impurity concentration is formed thereon by epitaxial growth in consideration of withstand voltage.

Next, the surface of the n-type layer 2, a plurality of high impurity concentration p ⁺ -type region 1A having a predetermined depth L _P at a predetermined width W _P at a predetermined interval W _S, In addition, these n-type layer 2
The anode electrode 4 is provided on the entire surface including the surface of the P ⁺ -type region 1A and the exposed surface of the p ⁺ -type region 1A, whereby a Schottky junction is formed at the junction between the low impurity concentration n-type layer 2 and the anode electrode 4. The electrical connection between the key junction and the p ⁺ type region 1A is obtained by the anode electrode 4.

Here, the interval W _S provided between the plurality of p ⁺ -type regions 1A is such that when a reverse bias is applied to the Schottky junction, the high impurity concentration p ⁺ -type region 1A changes to the low impurity concentration n-type The dimensions are set such that the depletion layer formed by spreading in the layer 2 is sufficiently pinched off, so that when a reverse bias is applied, the high impurity concentration p ⁺ -type region 1
A depletion layer appears in the low impurity concentration n-type layer 2 from the pn junction formed by A and the low impurity concentration n-type layer 2, and this serves to eliminate the carrier immediately below the Schottky junction.

Therefore, according to the Schottky diode shown in FIG. 2, since the carrier immediately below the Schottky junction is eliminated, the function of alleviating the electric field strength at the interface of the Schottky junction can be obtained. By limiting the forward current, the current flowing through the pn junction is reduced, the effect of accumulating minority carriers is suppressed, and high-speed operation can be achieved.

At this time, the p ⁺ -type region 1A having a high impurity concentration also functions as a guard ring, and an effect due to the function can be obtained. Furthermore, according to this Schottky diode 2, the p ⁺ -type region 1A apart W _S narrowing of or by the increasing depth L _P, can be expected more electric field relaxation effect.

[0021]

The Schottky diode according to the prior art described above has a problem that the loss is increased because no consideration is given to an increase in the forward voltage. That is, in the diode according to the prior art, as described with reference to FIG. 2, since the plurality of p ⁺ -type regions 1A are provided on the surface of the n-type layer 2, the junction between the n-type layer 2 and the anode electrode 4 is correspondingly increased. The area of the Schottky junction formed in the portion is reduced, that is, the forward current path is narrowed, and as a result, the forward resistance increases and the forward voltage increases.

Further, in this prior art Schottky diode, p ⁺
Narrowing the interval W _S type region 1A, it is necessary to increase the depth L _P, As a result, further a reduction in the effective Schottky area, the extension of the current path narrower brought,
This causes a further increase in series resistance, and consequently increases the resistance during forward conduction.

Here, in order to reduce the resistance during forward conduction, a method of increasing the impurity concentration of the low impurity concentration n-type layer 2 can be considered. In this case, the same effect of reducing the electric field can be obtained. the, so there arises a need to further reduce the distance W _S of the p ⁺ -type region 1A, inevitably also increase the forward voltage.

It is an object of the present invention to provide a diode with improved reverse characteristics and reduced loss during forward conduction, capable of high-speed response and low loss.

[0025]

SUMMARY OF THE INVENTION It is an object of the present invention to selectively form at least two low-resistance regions of the second conductivity type on the surface of a high-resistance layer of the first conductivity type made of silicon carbide at predetermined intervals. In a diode having a metal layer formed on the surface of the first conductivity type high resistance layer and the surface of the second conductivity type low resistance region and serving as an anode electrode, This is achieved by forming the shape such that the distance between the second-conductivity-type low-resistance regions becomes a minimum value at a position inside a predetermined distance from the surface of the first-conduction-type high-resistance layer.

According to this structure, the surface area of the first-conductivity-type high-resistance layer sandwiched between the second-conductivity-type low-resistance regions increases, so that the conduction area increases, and the resistance during conduction decreases. Directional characteristics are improved. On the other hand, with respect to the reverse characteristics, both the breakdown voltage and the reverse current are maintained at the same level as the conventional structure.

The reason is as follows. Now, assuming that the second conductivity type low resistance region in the vicinity of the semiconductor substrate surface is a high impurity concentration p-type region and the first conductivity type high resistance layer is a low impurity concentration n-type layer, a pn junction formed therebetween is formed. Since the low impurity concentration n-type region and the high impurity concentration p-type layer 1 have the same potential, the depletion layer extending to the low impurity concentration n-type region is determined by the diffusion potential, and hardly expands beyond that.

Therefore, the interval W between the high impurity concentration p-type regions 1
_In the case of the prior art shown in FIG. 2 where the position where _S becomes the narrowest is also on the surface, when a reverse bias is applied, the impurity concentration n
The depletion layer extending to the mold region 2 contacts inside the semiconductor substrate surface.

Since the barrier height becomes highest at the point where the depletion layer comes into contact first, the high impurity concentration p-type region 1 on the surface side from this point has little influence on the reverse characteristics. Therefore, with respect to the reverse characteristics, both the breakdown voltage and the reverse current are maintained at the same level as in the conventional technique.

Heretofore, the above-mentioned problems have not been apparent in the field of silicon power devices. The reason is that a high breakdown voltage Schottky diode exceeding 100 V is not realistic because silicon has a large resistance during forward conduction.

Also, among silicon high-voltage diodes, a number of diodes having a Schottky junction and a pn junction alternately arranged as high-speed, low-loss diodes have been proposed. However, the operating principle is significantly different between silicon and silicon carbide.

First, in the case of silicon, holes are injected from the high impurity concentration p-type region 1, so that the presence of the high impurity concentration p-type region 1 does not become a dead space. However, in the case of silicon carbide, since no current flows across the pn junction, the existence of the high impurity concentration p-type region 1 becomes a dead space for the flow of forward current.

The reason is as follows. First, the rise voltage of the pn junction of silicon carbide is about 3 V, which is considerably higher than that of silicon, about 0.5 V. Therefore, no current flows unless a forward bias of 3 V or more is applied to the pn junction of silicon carbide.

As a result, for example, when a diode having a breakdown voltage of more than 50 V as shown in FIG. 2 was fabricated using silicon, when the current density was 100 A / cm ² or more, p
A forward bias of 0.5 V or more is applied to the n-junction, and holes are injected from the high impurity concentration p-type region 1 to the low impurity concentration n-type region 2. However, with silicon carbide diodes,
This is because, even with a breakdown voltage of 5000 V class, the forward bias of the pn junction does not become 3 V or more, so that holes are not injected across the pn junction.

[0035]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a silicon carbide diode according to the present invention will be described in detail with reference to an embodiment shown in the drawings. Here, first, the principle of operation of the present invention will be described with reference to FIG. An embodiment will be described.

First, also in the basic structure of the present invention shown in FIG. 1, a low impurity concentration n-type layer 2 is epitaxially grown on a low resistance high impurity concentration n ⁺ semiconductor substrate 3 having a cathode electrode 5. A plurality of high impurity concentration p ⁺ -type regions 1A having a predetermined width W _P and a predetermined depth L _P are provided at a predetermined interval W _S on the surface of the n-type layer 2. An anode electrode 4 is provided on the entire surface of the mold layer 2 and the p ⁺ -type region 1A.
2 in that a Schottky junction is formed at the junction of the Schottky junction and that the electrical connection between the Schottky junction and the p ⁺ -type region 1A is obtained by the anode electrode 4. Same as the diode according to the prior art.

The Schottky diode having the basic structure of the present invention shown in FIG. 1 is clearly different from the prior art shown in FIG. 2 in the following point. That is,
The first difference is that the semiconductor portion is made of a semiconductor material containing silicon carbide as a main component.

[0038] When detailed explanation, the n-type layer 2 and the n ⁺ semiconductor substrate 3, the silicon carbide, a material acts such as N (nitrogen) as an n-type semiconductor by adding as an impurity, and the p ⁺ type region 1A Is, for example, Al (aluminum), B
A material that functions as a p-type semiconductor by containing an impurity such as (boron), and is formed of each.

The second difference is that the p ⁺ type region 1
A is that the cross-sectional shape of A is formed as an oval extending in the lateral direction as shown in the figure. Detail when explaining a result of the cross-sectional shape of the p ⁺ -type region 1A oblong oblong, located to minimize their spacing W _S is moved a predetermined distance L _S from the surface of the n-type layer 2 on the inside, this Thus, the surface area of the p ⁺ -type region 1A is changed from the value determined by the maximum width W _P to the value determined by the width W _P ′ of the side of the oval.

[0040] As a result, the area of the Schottky junction formed at the junction of the n-type layer 2 and the anode electrode 4, the distance W _S
From the value determined by, the value is determined by the interval W _S ′. At this time, from the relationship (W _P > W _P ′), the relationship becomes (W _S ′> W _S ), and the area of the Schottky junction is reduced. The feature is that it is widened, and in these points, it is clearly different from the prior art of FIG.

The silicon carbide diode according to the present invention having the above-described characteristics is characterized in that the depletion that expands into the n-type region 2 when a reverse bias is applied from the pn junction formed between the p ⁺ -type region 1A and the n-type layer 2. The present inventor paid attention to the point that the layer becomes wider on the inner side than the surface of the semiconductor substrate.

That is, first, from the viewpoint of reducing the forward resistance, the smaller the surface area of the p ⁺ type region 1A, that is, the area in contact with the anode electrode 4 is better. Thus, when the surface area of the p ⁺ -type region 1A is reduced, the electric field strength at the Schottky junction interface increases when a reverse bias is applied, and the reverse characteristics deteriorate.

[0043] In the present invention, p ⁺ -type regions 1A cross-sectional shape made oval extending laterally, thereby, a position to minimize their spacing W _S is, from the surface of the n-type layer 2 It is shifted inward by a predetermined distance L _S ,
As a result, the area of p ⁺ -type region 1A is reduced near the surface of the semiconductor substrate which does not easily affect the reverse characteristics, and as a result, the forward characteristics can be improved without impairing the reverse characteristics. It is like that.

Next, the present invention will be described in detail with reference to specific embodiments. FIG. 3 shows an embodiment of the present invention, which is a cross-sectional structural view of a specific example of the basic configuration shown in FIG. 1. The semiconductor substrate of this embodiment has a specific resistance of 3.9 × 10 ^{−. 3} Ω · cm, impurity concentration 2 × 1
A specific resistance of 3.9 Ω · cm and an impurity concentration of 2 × 10 ¹⁵ cm are formed on an n ⁺ type semiconductor substrate 3 of 0 ¹⁸ cm ^-3 and a thickness of 300 μm.
N-type layer 2 composed of an epitaxial layer of ^-3 mm in thickness of 50 μm
It has grown to.

Then, ions are implanted into the surface of the n-type layer 2 composed of an epitaxial layer of the semiconductor substrate by a selective ion implantation method so that the impurity concentration becomes 1 × 10 ¹⁹ cm ⁻³ , Resistance is 7.8 × 10 ^-4 Ω
cm p ⁺ -type region 1A is formed. In this case, the width W _P of about 4μm the p ⁺ -type region 1A, the junction depth L _P of about 2μ
m, and the width of the interval W _S to form a Schottky junction was set to approximately 4 [mu] m.

Thereafter, a Ti (titanium) film is formed on the entire upper surface of the p ⁺ -type region 1A and the n-type layer 2 by electron beam evaporation for about 20 μm.
0 nm was deposited to form an anode electrode 4, and finally an Al film was deposited to a thickness of about 1 μm to form a protective metal layer 7 for protecting a barrier metal. On the other hand, Ni ⁺
(Ni) was vapor-deposited to a thickness of about 1 μm and sintered to form a cathode electrode 5, thereby obtaining a diode as shown in FIG.

The results of evaluating the electrical characteristics of the diode formed as described above are as follows. That is, a diode having a withstand voltage of 5000 V and a reverse voltage of 100 V
The reverse current when applying 0 V was 1 × 10 ⁻⁶ A / cm ² , and the forward voltage was 2.5 V when the forward current density was 50 A / cm ² .

Next, the present invention is also characterized in that the p ⁺ -type region 1A is formed by ion implantation. That is, in one embodiment of the present invention, as shown in FIG. 1, the cross-sectional shape of the p ⁺ type region 1A is made oblong and oblong, which is obtained by ion implantation of silicon carbide. This is possible for the first time due to the application, and this point will be described in detail below.

FIG. 8 shows the concentrations of the implanted ions as isoconcentration lines 81 to 83 when the silicon carbide immediately after the ion implantation is viewed from the lateral direction. In FIG. 8, reference numeral 71 denotes a mask, which shows a state after ions are implanted into the n-type layer 2 from the opening 71A as shown by an arrow. The concentration line 81 indicates the position of the highest concentration, followed by the isoconcentration line 82 and the isoconcentration line 83 in the order of low ion concentration.

FIG. 8 shows that these isoconcentration lines 81 to 83
It can be seen that each of them has a horizontally long oval shape, which is because the implanted ions wrap around to the back side of the mask 71. In this way, the wraparound appears in the implanted ions. This is because the implanted ions collide with the atoms of the substrate, which causes the ions to be scattered in the lateral direction.

By the way, even in a silicon substrate, immediately after ion implantation, the ion concentration distribution has such a shape that the central portion swells in the lateral direction. However, in the case of a silicon substrate, the implanted ions undergo redistribution due to annealing for defect recovery and activation of impurity ions, and thus such a distribution shape cannot be maintained. This is because silicon carbide has an impurity diffusion coefficient 1/100 of that of silicon.
Since it is extremely small, ie, 00, redistribution due to annealing does not occur, and the shape immediately after implantation shown in FIG. 8 is maintained.

Next, conventionally, in the field of silicon semiconductors, the high impurity concentration p ⁺ -type region 1 in the diode of FIG. 2 must be formed deep from the viewpoint of improving the reverse characteristics. As the method, a thermal diffusion method has been used for the following reason.

First, in a diode having a withstand voltage of 5 kV class, the depth of the high impurity concentration p ⁺ type region 1 is about 20 μm.
Although the above is necessary, in the ion implantation method, even if implantation is performed at a high energy of 10 MeV, the implantation depth is 10 μm, and therefore, it is difficult to implant up to a depth of about 20 μm.

However, when silicon carbide is used, since the thickness of the low impurity concentration n-type region 2 can be reduced to about 1/10 of silicon, the depth of the high impurity concentration p ⁺ type region 1A is 2 μm. A degree is sufficient. At this depth, an ion implantation method can be used even at an energy of about 2 MeV. In the case of silicon carbide, the ion implantation method can be applied to the formation of the high impurity concentration p ⁺ type region 1A.

On the other hand, since the impurity diffusion coefficient of silicon carbide is extremely small, it is not practical to apply the thermal diffusion method to a silicon carbide semiconductor. Therefore, in the present invention, it can be said that the ion implantation method is the best means for forming the high impurity concentration p ⁺ type region 1A.

Next, the mask 71 will be described. First, resist, metal, silicide, SiO _{2, and the} like are known as materials for the mask, but here, a mask that satisfies the following requirements is required. First, in FIG. 1, ions must be implanted with high energy to form a deep high impurity concentration p ⁺ -type region 1A as shown in the figure, but a thick mask is required to shield high energy ions. Required.

[0057] Further, oblong high impurity concentration p ⁺ -type region 1A shown in FIG. 1, i.e., the position where the distance W _S is minimized to form a shape on the inside from the surface of the semiconductor substrate, the mask Scattering of implanted ions on the side wall of the opening must be avoided as much as possible. To this end, it is necessary to make the mask thinner and make the opening end face of the mask as perpendicular to the semiconductor substrate surface as possible.

Therefore, when a resist is used for forming a mask, it is desirable to apply a multilayer resist method. According to the multilayer resist method, a thick mask can be easily formed,
This is because the side wall of the opening of the mask can be easily processed perpendicularly to the surface of the semiconductor substrate.

Hereinafter, a case where the method of processing a mask by the multilayer resist method is applied to an embodiment of the present invention will be described with reference to FIG. First, as shown in FIG. 9A, a laminated structure of an organic film 72, an inorganic intermediate layer 73, and a resist 74 is formed on the surface of a semiconductor substrate (low impurity concentration n-type layer 2). Here, the inorganic intermediate layer 73 is used to prevent the organic film 72 and the resist 74 from being mixed.

Next, as shown in FIG. 3B, the resist 74 is processed by exposure treatment, and then, as shown in FIG. 3C, etching is performed using the resist 74 as a mask to form the inorganic intermediate layer 73. Process. Finally, as shown in FIG.
Using the resist 74 and the inorganic intermediate layer 73 as a mask, O2-
The dry etching by RIE is performed to form a pattern on the organic film 72, and finally, the mask 71 is obtained. Here, as the organic film 72, for example, polyimide
(PIQ, manufactured by Hitachi Chemical) may be used.

Next, a mask using silicide will be described. Since silicide has a large shielding effect on ions, the mask can be made thinner. As a result, scattering of implanted ions on the side wall of the mask opening can be sufficiently suppressed. In addition, it has been reported that in silicon carbide, defects can be reduced at the time of implantation by implanting ions at a high temperature. Therefore, if the mask material has heat resistance,
High temperature ion implantation becomes possible.

Therefore, a case where a mask which uses silicide, has high heat resistance, has a large ion shielding effect even when thin, and is easily removed after ion implantation is applied to one embodiment of the present invention, and FIG. This will be described with reference to FIG. FIG.
Here, the mask has a structure in which a high melting point metal silicide 76 is stacked on a silicon nitride 75.
Here, first, sufficient heat resistance and a shielding effect can be obtained by the refractory metal silicide 76. Next, a silicon nitride 75 is provided at a portion where the high melting point metal silicide 76 contacts the semiconductor substrate (low impurity concentration n-type layer 2) so that the mask after ion implantation can be easily removed. I have. The high melting point metal silicide here includes tungsten silicide, molybdenum silicide and the like.

Next, another embodiment of the present invention will be described. First, FIG. 11 shows that, in order to reduce the contact resistance between the anode electrode 4 and the high impurity concentration p ⁺ -type region 1A, a portion in contact with the anode electrode 4 on the surface of the p ⁺ -type region 1A is p ^{++ with a} higher impurity concentration FIG. 2 is a cross-sectional structural diagram of an example of an embodiment in which a mold region 9 is used.

As described with reference to the isoconcentration lines 82 and 83 in FIG. 8, the surface concentration is reduced by one-stage ion implantation. Therefore, thereafter, the same mask is used, and p-type impurities are ion-implanted again with lower energy than that at the time of the ion implantation in the first stage, so that the p ⁺ -type region 1A has p-type impurities.
^{The ++} type region 9 can be formed.

Here, this ion implantation is for the purpose of reducing the contact resistance to the anode electrode 4, so that a shallow junction is sufficient.

The type of ions to be implanted at this time is as follows.
It may be the same as in the first stage, or may be different.
Next, FIG. 12 is a sectional structural view showing an embodiment of a Schottky diode in which the forward characteristic can be further improved. The embodiment of FIG. 12 is characterized by a high impurity concentration p ⁺ sectional shape of the mold region 1A is rather than oval, Yes in the substantially trapezoidal have spread to the lower, Thus, the interval W _S which is provided between the p ⁺ -type region 1A is the smallest position, FIG. It is located inside the substrate more than in the case of the first embodiment.

The depletion layer extending from the pn junction formed between the high impurity concentration p ⁺ type region 1A and the low impurity concentration n-type layer 2 to the low impurity concentration n-type region 2 becomes wider from the substrate surface toward the inside. Become. Therefore, as shown in FIG. 12, by making the cross-sectional shape of p ⁺ type region 1A substantially trapezoidal, the depletion layer comes into contact at the widest position. Therefore, according to the example embodiment of FIG. 12, the interval of the p ⁺ -type region 1A W _S
Can be further widened, and as a result, the series resistance at the time of forward conduction can be reduced, and the forward characteristics can be improved.

FIG. 13 shows an embodiment of a method for forming the substantially trapezoidal high impurity concentration p ⁺ type region 1A in the embodiment of FIG. First, as shown in FIG.
Using the mask 71, as a first step, ion implantation regions 11 are formed on the surface of the low impurity concentration n-type layer 2 by ion implantation of p-type impurities. At this time, if the opening side wall of the mask 71 at the time of ion implantation is close to a right angle to the substrate surface, the shape of the ion implantation region 11 in the first stage reflects the effect of lateral scattering, and The most swollen position is inside the substrate.

Next, as shown in FIG. 3B, ions are implanted at a higher energy than in the first stage, to form an ion implanted region 12 in the second stage. At this time,
The lateral scattering intensity is determined by the energy loss due to the collision between the implanted ions and the atoms of the substrate, and as the implantation energy increases, the energy loss due to the collision between the atoms increases monotonically. The distance increases.

Therefore, by implanting the same ions or different ions in multiple steps with different implantation energies, it is possible to form a substantially trapezoidal ion implantation region 13 as shown in FIG. it can. At this time, the energy loss due to the collision between atoms becomes larger as the element has a larger mass, so that the heavier the element is, the lower the shape becomes. Therefore, by selecting the type of ions, the ion implantation region 1 having a substantially trapezoidal shape has considerable flexibility.
3 can be formed.

Next, the characteristics of the diode according to the present invention will be described.
For a clearer description, the results of simulation of the characteristics of the diode according to the prior art and the diode of the present invention will be described. FIG. 14 is a characteristic diagram showing the simulation with the withstand voltage on the horizontal axis and the forward voltage when the current density is 50 A / cm ^{2 on} the vertical axis. As is clear from FIG. When compared at 5 kV, the diode of the prior art has a forward voltage of 3.5 V, while the diode of the present invention has a forward voltage of 2.5 V, and therefore, according to the diode of the present invention,
A forward voltage reduction of 1.0 V will be obtained.

Here, the breakdown of the forward voltage 3.5 V in the diode of the prior art is 2.3 V from the surface of the semiconductor substrate to the depth of the high impurity concentration p ⁺ type region 1 and the inside of the low impurity concentration n type region 2 is 2.3 V. 1.2V. On the other hand, the breakdown of the forward voltage 2.5 V in the diode of the present invention is 1.3 from the surface of the semiconductor substrate to the depth of the high impurity concentration p ⁺ type region 1A.
V, the inside of the low impurity concentration n-type region 2 is 1.2 V.

Therefore, according to the present invention, the high impurity concentration p
^The voltage drop due to the series resistance due to the depletion layer extending from the pn junction between the ⁺ type region 1A1 and the low impurity concentration n-type layer 2 to the low impurity concentration n-type layer 2 can be reduced from 2.3V to 1.3V.

Next, still another embodiment of the present invention will be described. When the diode of the present invention is connected in reverse parallel to a unipolar switching device such as a MOSFET, the switching device and the diode are both unipolar, so that high-speed operation is possible. However, if the MOSFET chip and the diode chip are incorporated in the same module and the leads are connected to connect the chips, the module size becomes large. Also, in this case, a large number of connection conductors are laid in the module, which causes a problem in reliability, such as disconnection.

However, this problem can be solved by integrating the diode in the MOSFET chip, and FIG.
5 is an embodiment of the present invention in such a case,
Reverse conducting MOSFET using diode according to the present invention
FIG. 15 (a) is a longitudinal sectional view of FIG.
(b) is a plan view thereof.

15A and 15B, 32 is a p-type base region, 31 is an n-type source region, 33 is an insulated gate electrode, 34 is a source electrode, 35 is a drain electrode, and 36 is a gate electrode insulating layer. , 37 represents a MOSFET region, and 38 represents a diode region. The low-impurity-concentration n-type layer 2 and the high-impurity-concentration n ⁺ semiconductor substrate 3 are the same as those in the embodiment of FIG. 1, but the low-impurity-concentration n-type layer 2 forms an n-type drift layer. ing.

On the surface of low impurity concentration n-type layer 2, p-type base regions 32 are formed at predetermined intervals, and n-type source region 31 is formed in the center of these p-type base regions 32. . An insulated gate electrode 33 is provided so as to bridge the p-type base region 32 of one element and another base region 32 adjacent thereto, and the periphery of the insulated gate electrode 33 is electrically connected to an adjacent member by a gate electrode insulating layer 36. Insulated.

A source electrode 34 is formed outside the insulated gate electrode 33. Both ends of the source electrode 34 are in conductive contact with the p-type base region 32 and the n-type source region 31, respectively. A region 37 is formed.

Therefore, by applying a positive voltage to the insulated gate electrode 33, the p-type base region 32 immediately below the insulated gate electrode 33 is inverted to n-type, a channel is formed, and the p-type base region 31 Electrons are injected into n-type drift layer 2 via the inversion layer in region 32.

Next, on the surface of the n-type drift layer 2, between one p-type base region 32 in a portion not bridged by the insulated gate electrode 33 and another p-type base region 32 adjacent thereto. A plurality of high-impurity-concentration p ⁺ -type regions 1A are alternately arranged at predetermined intervals to form a diode region 38 of the present invention.

In FIG. 15A, the cross-sectional shape of the high impurity concentration p ⁺ type region 1A is drawn in a semicircular shape.
In practice, a horizontally long oval as shown in FIG.
It is made substantially trapezoidal as shown in FIG.

When the above shape is viewed in a plan view, FIG.
As shown in the figure, the p-type base region 32 is formed in an elongated rectangular shape with four rounded corners, and it can be seen that a similar n-type source region 31 is provided in the p-type base region 32. . It can be seen that a plurality of striped high impurity concentration p ⁺ -type regions 1A are formed between one p-type base region 32 and the adjacent p-type base region 32.

Here, the portion composed of the MOSFET region 37 and the diode region 38 constitutes a unit cell composed of a one-element MOSFET and a diode. These unit cells are arranged in the n-type drift layer 2 in a stripe shape. It is formed integrally in order.

Therefore, according to the embodiment of FIG. 15, the p-type base region 32 of each unit cell is
Since it functions as the p-type base region 32 forming the region 37 and also functions as a guard ring in the diode region 38, the area of the entire device can be reduced as compared with the case where the MOSFET and the diode are formed independently. As a result, the element current density can be improved.

Next, FIG. 16 shows an embodiment in which the diode according to the present invention is combined with a reverse conduction type electrostatic induction transistor. FIG. 16 (a) is a longitudinal sectional view of the embodiment, and FIG. ) Is a plan view thereof. 16, reference numeral 41 denotes a p-type gate region, 42 denotes an n-type high impurity concentration source region, 43 denotes a gate electrode, 46 denotes a gate electrode insulating layer, 44 denotes a source electrode, 45 denotes a drain electrode, and 47 denotes a static electrode. The inductive transistor region and 48 represent the diode region, respectively. The low impurity concentration n-type layer 2 and the high impurity concentration n
^{+ The} semiconductor substrate 3 is the same as the embodiment of FIG.

First, on the surface of the low impurity concentration n-type layer (n-type drift layer) 2, a p-type gate
1 are formed, and an n-type source region 42 is formed between the p-type gate regions 41. Also, the p-type gate region 41
Has a gate electrode 43 in conductive contact therewith,
A gate electrode insulating layer 46 is provided around the gate electrode 43, and is electrically insulated from an adjacent member.

Further, a source electrode 44 is formed outside the gate electrode 43. The source electrode 44 is in conductive contact with the n-type source region 42, thereby forming an electrostatic induction transistor. Therefore, the gate electrode 43
By applying a reverse bias to the p-type gate region 4
The n-type drift layer 2 immediately below the n-type source region 42 is depleted by the depletion layer extending from the pn junction formed between the N-type drift layer 2 and the n-type drift layer 2 to the n-type drift layer 2, and the source-drain voltage And operates as an electrostatic induction transistor.

Next, on the surface of the low impurity concentration n-type layer (n-type drift layer) 2, one p-type gate region 41 having no n-type source region 42 and another p-type gate region A plurality of high-impurity-concentration p ⁺ -type regions 1A are alternately arranged at predetermined intervals between the region 41 and the region 41, thereby forming a diode region 48 of the present invention.

In FIG. 16A, the cross-sectional shape of the high impurity concentration p ⁺ type region 1A is drawn as a semicircle.
In practice, a horizontally long oval as shown in FIG.
It is made substantially trapezoidal as shown in FIG.

When the above shape is viewed in plan, FIG.
As shown in FIG. 6B, it is found that the p-type gate region 41 is formed in a rectangle with four rounded corners, and the n-type source region 42 is formed.
Exists between one p-type gate region 41 where no p-type is present and an adjacent p-type gate region 41 in the form of a stripe with a high impurity concentration p ⁺
It can be seen that the mold region 1A is formed.

Therefore, according to this embodiment, a unit cell composed of an electrostatic induction transistor and a diode is constituted by a portion composed of the static induction transistor region 47 and the diode region 48, and these unit cells are formed in a stripe shape. , In the n-type drift layer 2.

At this time, the p-type gate region 41 of each unit cell functions as the p-type gate region 41 forming the electrostatic induction transistor region 47 and also functions as a guard ring of the diode region 48, so that the electrostatic induction As compared with the case where the transistor and the diode are formed independently of each other, the area of the entire device can be reduced, and the device current density can be improved.

FIG. 17 shows an example of a main circuit of a power inverter device using a reverse conducting MOSFET according to an embodiment of the present invention.
A reverse conduction type MOSFET shown in FIG. 15 is applied to an anti-parallel circuit portion of an OSFET and a diode.

The main circuit of the inverter device shown in FIG.
A pair of DC terminals 221 and 222 and three AC terminals 231 to 233 having the same number of AC phases are provided.
DC power supply is connected to
The DC power is converted into AC power by switching 206, and a three-phase AC voltage is output to AC terminals 231 to 233.

Each MOSFET 201-206 is paired with two MOSFETs, and each pair of MOSFETs,
SFETs 201 and 202, 203 and 204, 205 and 2
Reference numeral 06 is connected in series between the DC terminals 221 and 222, and AC terminals 231 to 233 are respectively taken out from a series connection point of two MOSFETs in each MOSFET pair.

In FIG. 17, the anti-parallel circuit portion of the MOSFET and the diode surrounded by a broken line
It is composed of the reverse conducting MOSFET chip shown in FIG. According to the circuit of FIG. 17, since the MOSFET and the diode are integrated, the inductance of the wiring is reduced, and as a result, the rated voltage of the MOSFET and the diode can be reduced.

Also, since the wiring inductance is reduced, the module loss can be reduced, the efficiency of the inverter device is improved, and the module is less likely to malfunction, so that the reliability of the inverter is also improved. As a result, the breakdown strength is improved, so that the protection circuit can be omitted or simplified, and therefore, the inverter device can be downsized.

The present invention is not limited to the above-described embodiment. For example, a semiconductor device in which the conductivity type of a semiconductor layer of a diode is reversed, that is, a semiconductor device in which p is changed to n and n is changed to p Needless to say, it can be applied to

[0099]

According to the present invention, pn is applied to the surface of a semiconductor substrate.
In a diode in which junctions and Schottky junctions are alternately arranged, a semiconductor material is made of silicon carbide, and then a cross section of a semiconductor region of one conductivity type formed on the surface of a semiconductor substrate to form a pn junction extends in a lateral direction. Oval shape or a substantially trapezoidal shape that spreads downward, and a structure with the narrowest space between them is deeper than the substrate surface. Directional resistance can be sufficiently reduced.

As a result, a diode having a high withstand voltage and a small loss can be easily provided.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an embodiment of a silicon carbide diode according to the present invention.

FIG. 2 is a sectional view of a conventional diode.

FIG. 3 is a sectional view showing a further specific embodiment of the silicon carbide diode according to the present invention.

FIG. 4 is a circuit diagram showing an example of a main circuit diagram of a voltage type inverter.

FIG. 5 is a waveform diagram of a current / voltage in a reverse circuit mode of a diode and a current / voltage when a transistor shifts from off to on.

FIG. 6 is a cross-sectional view showing a diode having a pn ⁻ n ⁺ structure and a Schottky diode according to the related art.

FIG. 7 is a waveform chart showing current characteristics of a diode in a reverse recovery mode.

FIG. 8 is an explanatory diagram of ion concentration when ions are implanted using a mask in the diode of the present invention.

FIG. 9 is an explanatory diagram showing a mask processing method using a multilayer resist.

FIG. 10 is a cross-sectional view of a mask using a stacked film of silicon nitride and a refractory metal silicide as a mask.

FIG. 11 is a sectional view showing another embodiment of the silicon carbide diode according to the present invention.

FIG. 12 is a sectional view showing still another embodiment of the silicon carbide diode according to the present invention.

FIG. 13 is an explanatory view showing a method of forming an ion implantation region in still another embodiment of the silicon carbide diode according to the present invention.

FIG. 14 is a characteristic diagram of a diode according to the present invention and a diode according to the related art.

FIG. 15 is a cross-sectional view and a plan view showing an embodiment of a silicon carbide diode according to the present invention in combination with a reverse conducting MOSFET.

FIG. 16 is a sectional view and a plan view showing an embodiment of a silicon carbide diode according to the present invention in combination with a reverse conducting electrostatic induction transistor.

FIG. 17 is a circuit diagram showing an example of a main circuit of a power inverter device to which the silicon carbide diode according to the present invention is applied.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 1A High impurity concentration p ⁺ type region 2 Low impurity concentration n ⁺ type layer 3 High impurity concentration n ⁺ type region 4 Anode electrode 5 Cathode electrode 6 Insulator 7 Protective metal 8 High impurity concentration p ⁺ type guard ring region 9 High impurity Concentration p ⁺⁺ region 11 First stage ion implantation region 12 Second stage ion implantation region 13 Final ion implantation region 31 N-type source region 32 P-type base region 33 Insulated gate electrode 34 Source electrode 35 Drain electrode 36 Gate electrode Insulating layer 37 MOSFET region 38 Diode region 41 P-type gate region 42 N-type source region 43 Gate electrode 44 Source electrode 45 Drain electrode 46 Gate electrode insulating layer 47 Static induction transistor region 48 Diode region 71 Ion implantation mask 72 Organic film 73 Inorganic intermediate layer 74 Resist 75 Silicon nitride film 7 Equal concentration lines of refractory metal silicide 81 to 83 ion concentration

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Tsutomu Yao 7-1-1, Omikacho, Hitachi City, Ibaraki Prefecture Inside Hitachi Research Laboratory, Hitachi, Ltd. (72) Inventor Yoshitaka Sugawara 7-1, Omikamachi, Hitachi City, Ibaraki Prefecture No. 1 Hitachi, Ltd. Hitachi Research Laboratory (72) Inventor Katsunori Asano 3-2-2 Nakanoshima, Kita-ku, Osaka-shi, Osaka

Claims (10)

[Claims] A first conductive type high-resistance layer made of silicon carbide, wherein at least two second conductive type low-resistance regions are selectively provided at predetermined intervals on the surface; In a diode in which a metal layer is formed on the surface of the high resistance layer and the surface of the second conductivity type low resistance region to serve as an anode electrode, the cross section of the second conductivity type low resistance region is A silicon carbide diode characterized in that the distance between them has a minimum value at a position inside a predetermined distance from the surface of the first conductivity type high resistance layer. 2. The invention according to claim 1, wherein an impurity concentration of a portion of the second conductivity type low resistance region exposed on the surface of the first conductivity type high resistance layer is within the second conductivity type low resistance region. A silicon carbide diode configured to have a concentration higher than a minimum impurity concentration among the impurity concentrations. 3. The silicon carbide diode according to claim 1, wherein the second conductivity type low resistance region is formed by an ion implantation method. 4. The silicon carbide diode according to claim 2, wherein the second conductivity type low resistance region is formed by a multi-stage ion implantation method with different implantation energies. 5. The silicon carbide diode according to claim 2, wherein said second conductivity type low resistance region is formed by a multi-stage ion implantation method using ion species having different masses. . 6. The invention according to claim 3, wherein the shielding mask used in the ion implantation method is made of at least one material of a resist, a metal, an oxide film, a nitride film, and a silicide. And silicon carbide diode. 7. The method according to claim 3, wherein the shielding mask used in the ion implantation method is a multilayer film in which an organic film, an intermediate inorganic layer, and a resist are sequentially laminated on the surface of the first conductivity type high resistance layer. A silicon carbide diode characterized by being constituted. 8. The silicon carbide diode according to claim 7, wherein said organic film is polyimide. 9. The silicon carbide diode according to claim 3, wherein the shielding mask used in the ion implantation method is composed of a laminated film of silicon nitride and a refractory metal silicide. 10. The silicon carbide diode according to claim 9, wherein the refractory metal silicide is at least one of tungsten silicide and molybdenum silicide.