JPH10320917A - Method for processing digital signal and digital signal regenerating apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To conduct highly accurate binary identification by reducing errors due to influences of noises. SOLUTION: A reproduction signal Sa is supplied to an equalizer 10, thereby obtaining a Nyquist equalization signal Seq. The signal Seq is converted to a digital signal Sf and supplied to an identification circuit 60. At the same time, the signal Sf is equalized to a PR (1, -1) characteristic by a (1-D) filter 45, thereby obtaining a signal Sf(1-D) which is then supplied to the identification circuit 60. A binarization signal Sb is obtained from the signal Seq at a comparator 11. A synchronization signal Ss synchronized to a predetermined phase or delayed by one clock is generated at a synchronization circuit 12. Signals UT, DT indicating a rise and a fall of the signal Ss are generated at a differentiation circuit 50 and supplied to the identification circuit 60. A signal based on the signal Sf(1-D) and the signal Sf are added with a predetermined ratio at the identification circuit 60. By varying the ratio, a frequency characteristic of noises of a signal obtained by the addition can be varied. Phases of the signals UT, DT are controlled on the basis of the obtained signal, so that a correct binary identification signal Sg is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a digital signal processing method and a digital signal reproducing device. More specifically, a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded is equalized to a plurality of equalization standards having different frequency characteristics, and the obtained signal is added at a predetermined ratio, thereby obtaining the added signal. Frequency characteristics relating to noise can be set to desired characteristics, and by performing binary identification of the reproduction signal based on the added signal, the occurrence of errors can be reduced and the signal recorded on the recording medium can be correctly reproduced. Things.

[0002]

2. Description of the Related Art Conventionally, in a magnetic recording / reproducing apparatus and an optical disk apparatus, various methods have been proposed for binary identification of a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded.

For example, in a method called integral detection, FIG.
As shown in (1), the reproduction signal Sa is supplied to an integral equalizer 10 composed of a cosine equalizer or the like. In the integral equalizer 10, the reproduced signal Sa is processed so as to satisfy a condition called the Nyquist condition and to have a characteristic as shown in FIG. 8, thereby suppressing intersymbol interference. The Nyquist equalized signal Seq obtained by performing the equalizing process by the integral equalizer 10 is supplied to the comparator 11. FIG. 9 shows an eye pattern of the Nyquist equalization signal Seq. When the recording signal WS is as shown in FIG. 10A, the Nyquist equalization signal Seq is as shown in FIG. 10B.

The comparator 11 determines whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and generates a binary signal Sb as shown in FIG. 10C. This binarized signal Sb is transmitted to the synchronization circuit 12 and the PLL (Phas
e Locked Loop) circuit, and is supplied to a phase comparator 21 of a clock generation unit 20 configured using a circuit.

A clock signal C from a voltage controlled oscillator (VCO) 22 is supplied to a phase comparator 21 of the clock generator 20.
LK is supplied, the phase of the binary signal Sb is compared with the phase of the clock signal CLK, and an error signal PD indicating a phase difference is supplied to the voltage controlled oscillator 22 via the integrator 23.
For this reason, in the voltage controlled oscillator 22, the frequency of the clock signal CLK is controlled based on the error signal PD, and the phase of the clock signal CLK is equal to the edge of the binary signal Sb, for example, as shown in FIG. 10D. Is done. The clock signal CLK having the same phase as the binary signal Sb generated by the PLL circuit 20 in this manner is supplied to the synchronization circuit 12.

In the synchronization circuit 12, the clock signal C
The binarized signal Sb is latched based on LK, and FIG.
As shown in E, a binary identification signal Sc synchronized with the rising edge of the clock signal CLK is generated.

If amplitude equalization is performed for binary identification by this integration detection method, a low-frequency noise component is considered to have an emphasized low-frequency component, and an error may occur due to the low-frequency noise. Therefore, low-frequency components are not required.
A method called amplitude detection is also used as a value identification method.

In the amplitude detecting method, a reproduced signal Sa is supplied to an integral equalizer 10 as shown in FIG. The integration equalizer 10 and a comparator and a clock generation unit, which will be described later, are the same as those of the integration detection method, and the description is omitted.

The Nyquist equalized signal Seq obtained by the integral equalizer 10 is compared with the comparator 12 and the PR (1, -1) equalizer 30.
Supplied to The PR (1, -1) equalizer 30 is a filter having the characteristic of "1-D (subtract the signal one clock before from the current signal)". The intersymbol interference of the signal eq is suppressed by the device 30. The signal S (1-D), which is a signal in which intersymbol interference is suppressed, has a characteristic in which a high frequency band is emphasized as shown in FIG. PR
The signal S (1-D) obtained by the (1, -1) equalizer 30 is supplied to the non-inverting input terminal of the comparator 31 and the inverting input terminal of the comparator 32. This signal S (1-D) is a ternary signal, and the eye pattern is shown in FIG. When the recording signal WS is as shown in FIG. 14A, the signal S (1-
D) is as shown in FIG. 14B.

The inverting input terminal of the comparator 31 is connected to the connection point between the resistor 33 and the resistor 34, and is obtained by dividing the positive power supply voltage + V and the negative power supply voltage -V by the resistors 33, 34 and 35. The supplied threshold voltage Vthu is supplied. Similarly, the non-inverting input terminal of the comparator 32 is connected to a resistor 34
And the connection point of the resistor 35 and the positive power supply voltage +
A threshold voltage Vthl obtained by dividing V and the negative power supply voltage -V by the resistors 33, 34, 35 is supplied.

For this reason, the comparator 31 outputs the signal S (1
-D) is compared with the threshold voltage Vthu to generate a signal CU indicating that the signal S (1-D) is higher than the threshold voltage Vthu as shown in FIG. 14C. This signal CU is supplied to the J input terminal of the JK flip-flop 36. Similarly,
In the comparator 32, the signal S (1-D) and the threshold voltage Vthl
Are compared to generate a signal CL indicating that the signal S (1-D) is smaller than the threshold voltage Vthl as shown in FIG. 14D. This signal CL is equal to the K of the JK flip-flop 36.
It is supplied to the input terminal.

A clock signal CLK shown in FIG. 14E is supplied from the clock generator 20 to the JK flip-flop 36. The signal level of the J input terminal and the K input terminal of the JK flip-flop 36 at the timing of the clock signal CLK. Is generated and output as the binary identification signal Sd shown in FIG. 14F.

[0013]

By the way, in such an integral detection method, a large amount of low-frequency components is required. Therefore, in a magnetic recording / reproducing system in which a DC component cannot be reproduced, the low-frequency components are excessively emphasized. As a result, an error is generated by low-frequency noise.

Further, in the amplitude detection method, since the high frequency band is emphasized, the influence of the high frequency noise increases, which is disadvantageous for high density (short wavelength) recording.

Accordingly, the present invention provides a digital signal processing method and a digital signal reproducing apparatus which can reduce the occurrence of errors due to the influence of noise.

[0016]

A digital signal processing method according to the present invention equalizes a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded to a plurality of equalization standards having different frequency characteristics. The added signals are obtained by adding the respective signals obtained by the equalization at a predetermined ratio, and the binary identification of the reproduced signal is performed based on the added signals.

Further, the digital signal reproducing apparatus comprises a plurality of equalizing means for equalizing to equalization standards having different frequency characteristics, and a signal for adding a signal obtained by the equalizing means at a predetermined ratio to generate an addition signal. It has an addition processing means and an identification means for performing binary identification based on the addition signal.
A reproduction signal obtained by reproducing a recording medium on which a digital signal is recorded is equalized, and a binary identification signal of the reproduction signal is obtained from the identification means.

According to the present invention, a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded is converted into a signal having different frequency characteristics, for example, a signal equalized to an equalization reference of an integration system and an equalization of a differentiation system. A signal equalized to the reference is obtained,
The predetermined ratio is varied so that the frequency characteristic of the added signal obtained by adding this signal at a predetermined ratio has a desired characteristic.

[0019]

Next, a digital signal processing method and a digital signal reproducing apparatus according to the present invention will be described in detail with reference to the drawings.

FIG. 1 shows a configuration of a main part of a digital signal reproducing apparatus. A reproduction signal Sa obtained by reproducing the recording medium is supplied to an integral equalizer 10 composed of a cosine equalizer or the like, and processed so as to have a characteristic satisfying the Nyquist condition. Interference is suppressed. The Nyquist equalized signal Seq obtained by performing the equalizing process by the integral equalizer 10 is supplied to the comparator 11 and the A / D converter 40.

The comparator 11 determines whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and generates a binary signal Sb. The binarized signal Sb is supplied to a clock generator 20 configured using a synchronization circuit 12 and a PLL circuit.

As described above, the clock generating section 20 is constituted by using the phase comparing section 21, the voltage controlled oscillator 22, and the integrator 23. When the binary signal Sb is supplied to the phase comparing section 21, An error signal PD indicating a phase difference from the clock signal CLK supplied from the oscillator 22 is generated, and the error signal PD is supplied to the voltage controlled oscillator 22 via the integrator 23 and generated by the voltage controlled oscillator 22. The frequency of the clock signal CLK is controlled such that the phases of the clock signal CLK and the binarized signal Sb become equal. The clock signal CLK thus generated by the clock generator 20 is supplied to the synchronizing circuit 12, an A / D converter 40, a (1-D) filter 45, a differentiating circuit 50, and an identifying circuit 60, which will be described later.

In the synchronization circuit 12, the clock signal CLK
, The binarized signal Sb is latched, and the synchronization signal Ss
Is output to the differentiating circuit 50.

In the A / D converter 40, the clock signal CL
The Nyquist equalized signal Seq is converted into a digital signal Sf based on K and supplied to the (1-D) filter 45 and the identification circuit 60.

The (1-D) filter 45 has the characteristic of (1-D), that is, the characteristic obtained by subtracting the signal one clock before from the current signal, and the digital signal Sf is (1-D).
D) By the filter 45, PR (1,-
The characteristic is equalized to the characteristic of 1) to obtain an equalized signal Sf (1-D). Sf (1-D) (n) = Sf (n) -Sf (n-1) (1) The equalized signal Sf (1-D) thus obtained is supplied to the identification circuit 60. Is done.

The differentiating circuit 50 has the configuration shown in FIG. 2. The synchronizing signal Ss is supplied to a delay unit 51 and an AND gate 52.
The signal is supplied to the ND gate 55. The delay unit 51 delays the synchronization signal Ss by one clock. The synchronization signal Ss delayed by one clock is supplied to the AND gate 55 as the delay signal Scd, and is also logically inverted by the inverter 54 and supplied to the AND gate 52. Therefore, AN
From the D gate 52, a signal UT whose signal level is set to the high level "H" for one clock from the rise of the synchronization signal Ss is output. From the AND gate 55, a signal DT whose signal level is set to the high level "H" for one clock after the falling of the synchronization signal Ss is output. The signals UT and DT indicate the result of differentiation of the reproduction signal Sa. The signals UT and DT are supplied to the identification circuit 60.

In the identification circuit 60, binary identification is performed based on the operation result M shown in the equation (2). M = P × Sf (n) + Sf (1-D) (n−1) −Sf (1-D) (n) (2) Here, the signal Sf (n) contains much low-frequency noise. And the equalized signal "Sf (1-D) (n-1) -Sf (1-D)
(N) "is a signal containing a large amount of high-frequency noise. Therefore, by changing the coefficient" P ", the frequency characteristics of the noise are varied, and the frequency characteristics of the noise can be flattened.

The identification circuit 60 has the configuration shown in FIG. 3, and the signal Sf supplied from the A / D converter 40 is
The signal is supplied to the multiplier 61. In the multiplier 61, the signal Sf is multiplied by the coefficient “P”, and a signal PSf indicating the result of the multiplication is supplied to the delay unit 62.

The delay unit 62 adjusts the timing between the signal PSf and an equalized signal Sf (1-D), which will be described later. Supplied.

The equalized signal Sf (1-D) is supplied to a delay unit 63 and a subtractor 64. In the delay unit 63, the equalized signal Sf (1-D) is delayed by one clock and supplied to the subtractor 64. Therefore, the subtractor 64 performs the operation of Expression (3), and a signal Ms indicating the operation result is supplied to the subtractor 65. Ms = Sf (1-D) (n) -Sf (1-D) (n-1) (3)

In the subtracter 64, the signal Ms is subtracted from the signal PSf, and the addition signal MD indicating the operation result M of the equation (2) is obtained.
Is calculated. This addition signal MD is supplied to the delay unit 66. The OR signal 68 from an OR gate 68, which will be described later, is supplied to the delay unit 66, and the sign of the addition signal MD indicating the operation result is latched at a timing based on the signal GT, and the sign determination circuit 67 outputs the sign signal MF. Supplied to The signal DT obtained by the differentiating circuit 50 is supplied to the sign determination circuit 67, and the sign of the sign signal MF is inverted based on the signal DT. The code signal MF processed by the code determination circuit 67 is supplied to the selection circuit 71 as an output selection signal OTC.

The signals UT and DT obtained by the differentiating circuit 50
Is supplied to the OR gate 68. The OR signal GT obtained by the OR gate 68 is supplied to the above-described delay device 66 and also to the selection circuit 71 via the delay device 69 as a signal GTA. Further, the OR signal GT is supplied to the delay unit 6
The signal GTB is supplied to the selection circuit 71 via the signals 9 and 70.

For this reason, the selection circuit 71 selects either the signal GTA or GTB based on the output selection signal OTC and outputs it as a binary signal Sg.

Next, the operation of the digital signal processing device will be described with reference to FIGS. When the recording signal WS is as shown in FIG. 4A, the Nyquist equalized signal Seq shown in FIG. 4B is output from the integrating equalizer 10. The comparator 11 determines whether the signal level of the Nyquist equalization signal Seq is on the positive side or the negative side, and generates a binary signal Sb as shown in FIG. 4C. Based on the binarized signal Sb, the clock signal generator 20 generates, as shown in FIG.
The clock signal CL is adjusted so that the edge of the binarized signal Sb and the rising edge of the clock signal CLK have the same phase.
The frequency of K is controlled.

In the synchronization circuit 12, this clock signal C
The binarized signal Sb is latched on the basis of LK,
As shown in (1), a synchronization signal Ss synchronized with the rising edge of the clock signal CLK is generated.

For this reason, in the synchronization signal Ss, even if the reproduction signal Sa includes noise or the like, the phase of the synchronization signal Ss is set to either the solid line or the broken line, and the phase variation is kept within one clock. . Therefore, the signals UT and DT output from the differentiating circuit 50 are also as shown in FIGS.
It is assumed that the phase change is within one clock.

FIGS. 5 and 6 show the operation of the identification circuit 60. The signal Sf supplied from the A / D converter 40 shown in FIG. 5A is multiplied by a coefficient "P" in a coefficient multiplier 61. At the same time, the signal is delayed by one clock in the delay unit 62 and supplied to the subtractor 65 as a signal PSfd shown in FIG. 5B.

For example, during the period from time t1 to time t2, the signal Sf
Is changed from "-1" to "1" and the level is changed from "1" to "-1" during the period from time t4 to t5, the signal P
Sfd is a period from time t2 to time t3 after a lapse of one clock, the level of the signal PSfd is changed from “−1” to “1”, and
The level is changed from "1" to "-1" in the period from 5 to t6.
FIG. 5C shows the level obtained by sampling the signal PSfd at each time. Also, the coefficient multiplier 6 at this time
The coefficient P of 1 is, for example, “P = 1”.

From the (1-D) filter 45, the signal Sf (1-D) shown in FIG. 5D is supplied. This signal Sf (1-D)
The level is changed from "0" to "2" during the period from time t1 to t2, and the level is changed from "2" to "0" during the period from time t2 to t3. Further, the level is changed from “0” to “−2” during the period from time t4 to t5, and the level is changed from “−2” to “0” during the period from time t5 to t6. FIG. 5E shows the level obtained by sampling the signal PSfd at each time point.

In the identification circuit 60, the delay unit 63 and the subtractor 6
4, the operation result Ms is obtained from the signal Sf (1-D), and the operation result Ms is subtracted from the signal PSfd by the subtractor 65, so that the operation result M shown in FIG. The sum signal MD shown is obtained.

Here, the signals UT and DT shown in FIGS.
Is delayed to correspond to the signal PSfd, and the signal UT
The signal level is set to the high level "H" for one clock period from the time point ta to tb. The signal DT is at time td.
The signal level is set to the high level “H” only for one clock period from to te. Therefore, the signal level of the OR signal GT shown in FIG. 5J is set to the high level “H” only during the period from the time point ta to tb and from the time point td to te.

In the delay unit 66, the sign of the addition signal MD shown in FIG. 5F is latched based on the logical sum signal GT, so that the sign signal MF output from the delay unit 66 is
As shown by K, during the period from the time point ta to td, it is at the low level "L" and from the time point td it is at the high level "H".

Further, in the sign determination circuit 67, the sign signal M
When F is latched at the next clock and the signal DT is set to the high level “H”, the sign of the sign signal MF is inverted. For this reason, as shown in FIG. 5L, the output selection signal OTC is set to the low level “L” from the time point tb to the time point te, and the signal DT is set to the high level “H” during the time period from the time point td to te. , The logic level of the sign signal MF is inverted, and is kept at the low level “L” from the time point te.

In the selection circuit 71, when the signal level of the output selection signal OTC is at the high level "H", it is determined that the phase is delayed, and the phase is delayed by 1 from the signal GTB shown in FIG. 5N.
The signal GTA shown in FIG. 5M having the earlier clock phase is selected as the binary identification signal Sg. This binarized identification signal Sg is shown in FIG. 5P.

When the signal level of the output selection signal OTC is low level "L", it is determined that the phase is correct, and the signal GTB is selected as the binary identification signal Sg. Here, since the output selection signal OTC is at the low level "L", the signal GTB is selected, and the binarized identification signal Sg is set to the high level "H" during the period between the time points tc to td and tf to tg. .

FIG. 6 shows the case where the phases are delayed, that is, the case where the signals UT and DT are generated at the timing shown by the broken line in FIG. 4, and the signals in FIGS.
These correspond to the signals F to P. 6B to 6C.
6G and H show the case where the phase shown in FIG. 5 is correct.

When the phase is delayed, the signals in FIGS. 6B to 6C and 6G and H are set to the high level "H" with a delay of one clock as compared with the case where the phase is correct. For this reason,
The sign signal MF indicates the sign of the addition signal MD at the time point tb, and is at a high level "H", and at a time point te, at a low level "L". Therefore, the output selection signal OTC
Is at a high level "H" from time tc, and at time tf, the logic level of the code signal MF is inverted to a high level "H".

For this reason, the selection circuit 71 determines that the phase is delayed, and is one step behind the signal GTB shown in FIG. 6H.
The signal GTA shown in FIG. 6G having the earlier clock phase is selected as the binary identification signal Sg, and is equal to the case where the phase is correct, and is equal to the binary identification signal Sg during the period from time tc to td, tf to tg
Is set to a high level “H”.

The recording signal WS is a signal obtained by subjecting the recording information data signal to NRZI modulation. The recording signal WS can be obtained by subjecting the binarized identification signal Sg output from the identification circuit 60 to NRZI modulation.

As described above, according to the above embodiment,
The Nyquist equalized signal Seq, which is an error identification signal obtained by the integral equalizer 10 performing integral detection, and the Nyquist equalized signal Seq are A / D-converted and processed by the (1-D) filter 45, and The signal Ms generated based on the obtained signal of the PR (1, -1) characteristic is added at a predetermined ratio, and binary identification is performed based on the obtained addition signal MD. This Nyquist equalization signal Seq is a signal equalized to the equalization criterion of an integrating system containing much low-frequency noise, and the signal Ms is equalized to the equalization criterion of a differential system containing much high-frequency noise. Therefore, the frequency characteristics of the noise can be flattened only by changing the coefficient “P”, the identification accuracy can be improved, and the occurrence of errors can be reduced.

When the digital signal reproducing apparatus is applied to a video tape recorder or the like, the value of the coefficient "P" is switched between in a normal reproducing operation mode and in a variable speed reproduction operation mode having a lot of low-frequency crosstalk. If the ratio is changed by changing the ratio, it is possible to perform optimum binary identification according to each mode.

In the above-described embodiment, the case where Nyquist equalization and PR (1, -1) equalization are used as equalization methods has been described. Needless to say, value identification may be performed.

[0053]

According to the present invention, a reproduced signal obtained by reproducing a recording medium on which a digital signal is recorded is equalized to a plurality of equalization standards having different frequency characteristics, and each obtained signal is converted into a predetermined signal. In addition, the addition signal is generated in addition to the above ratio, and the predetermined ratio is varied, so that the frequency characteristic of the addition signal with respect to noise can be set to a desired characteristic. For this reason, by performing the binary identification of the reproduction signal based on the added signal, it is possible to perform the high-precision binary identification with a simple configuration. Signal can be reproduced correctly.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus according to the present invention.

FIG. 2 is a diagram showing a configuration of a differentiating circuit.

FIG. 3 is a diagram illustrating a configuration of an identification circuit.

FIG. 4 is a diagram for explaining the operation of the digital signal reproducing device.

FIG. 5 is a diagram for explaining the operation of the identification circuit.

FIG. 6 is a diagram for explaining the operation of the identification circuit.

FIG. 7 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus using an integration detection method.

FIG. 8 is a diagram illustrating frequency characteristics of a signal Sb.

FIG. 9 is a diagram showing an eye pattern of a Nyquist equalization signal Seq.

FIG. 10 is a diagram for explaining the operation of the digital signal reproducing device using the integration detection method.

FIG. 11 is a diagram showing a configuration of a main part of a digital signal reproducing apparatus using an amplitude detection method.

FIG. 12 is a diagram illustrating frequency characteristics of a signal S (1-D).

FIG. 13 is a diagram showing an eye pattern of an equalized signal S (1-D).

FIG. 14 is a diagram for explaining the operation of the digital signal reproducing apparatus using the amplitude detection method.

[Explanation of symbols]

10: integral equalizer, 11: comparator, 12
... Synchronization circuit, 20 ... Clock generation unit, 40
..A / D generator, 45 ... (1-D) filter, 5
0: differentiation circuit, 60: identification circuit, 61: coefficient multiplier, 67: sign determination circuit, 71: selection circuit

Claims (4)

[Claims] 1. A reproduction signal obtained by reproducing a recording medium on which a digital signal is recorded is equalized to a plurality of equalization standards having different frequency characteristics, and each signal obtained by the equalization is converted into a predetermined signal. A digital signal processing method, wherein an addition signal is obtained in addition to a ratio, and a binary identification of the reproduction signal is performed based on the addition signal. 2. The digital signal processing method according to claim 1, wherein said predetermined ratio is varied so that a frequency characteristic relating to noise of said addition signal has a desired characteristic. 3. A plurality of equalizing means for equalizing to equalization standards having different frequency characteristics, a signal adding processing means for adding a signal obtained by the equalizing means at a predetermined ratio to generate an added signal, Identification means for performing binary identification based on the addition signal; wherein the plurality of equalization means equalize a reproduction signal obtained by reproducing a recording medium on which a digital signal is recorded; A digital signal reproducing apparatus, wherein a binary identification signal of the reproduced signal is obtained from a means. 4. The equalizer according to claim 3, wherein the plurality of equalizers generate a signal equalized to an equalization criterion of an integral system and a signal equalized to an equalization criterion of a differential system. A digital signal reproducing apparatus according to claim 1.