JPH09106626A - Data-processing apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To generate clocks correctly synchronously with input data, by detecting a specific pattern in digital data, and generating clocks based on digital signals extracted in accordance with detection timing. SOLUTION: An amplitude detection circuit 19 detects amplitude level of a reproducing signal. A CPU 20 detects an abnormal case, e.g. when an error flag from an error correction circuit 9 indicates a total error although the reproducing signal is sufficiently large, and judges the state as abnormal in a PLL. At this time, the CPU 20 lowers high frequency gain of an equalizer 4 by several dB, and makes an automatic correction of equalization characteristic based on the error flag again or enlarges the variable range of the high frequency gain of the equalizer 4, etc., that is, controls the equalizer 4 so that a waveform after a PR process (1, 0, -1) changes smoothly at a specific point and monotonously in accordance with an actual waveform change corresponding to a change of data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device, and more particularly to a device for extracting a clock from transmitted digital data.

[0002]

2. Description of the Related Art Conventionally, in a device for transmitting (recording / reproducing) high-speed data such as a digital VTR, it is known to use a phase-locked loop (PLL) when extracting a clock from a received data string. ing.

A digital VT for high density magnetic recording
In R, the partial response 1,0, -1 method (hereinafter PR (1,0,-
1)) is used more often.

FIG. 9 is a block diagram showing a configuration example of a reproducing system of such a digital VTR.

In FIG. 9, the digital signal recorded on the magnetic tape 1 is reproduced by the magnetic head 2 and amplified by the amplifier 3 to a level sufficient for the subsequent processing. Here, the reproduction frequency characteristic of the magnetic head 2 is, in the case of the combination of the in-plane recording medium and the ring type magnetic head, as shown in FIG. 10A, due to the differential characteristic in the low range and various losses in the high range. It has a damping characteristic.

Therefore, the equalizer 4 having the frequency characteristic shown in FIG. 11B is used to equalize the frequency characteristic after equalization to the cosine roll-off characteristic shown in FIG. 10C. . The cosine roll-off characteristic is a characteristic such that the waveform interference is minimized at the data detection point, and the recorded data is restored by performing binary discrimination of the equalized signal.

Such equalization is called integral equalization, and the data detection method for determining the positive / negative of the integrated equalized signal by a comparator or the like is called integral detection.

Here, the eye pattern of the signal which has been integrated and equalized as described above is shown in FIG.

The eye pattern of the integrated and equalized signal is as shown in the figure, and in order to accurately detect the data, it is necessary to generate a clock for accurately sampling the maximum point of the eye opening. become. This clock is generated by a PLL including a phase detection circuit 13, a loop filter 14, and a voltage controlled oscillator (hereinafter referred to as VCO) 15.

The phase difference between the clock generated by the VCO 15 and the output signal of the equalizer 4 is detected by the phase detection circuit 13, and the phase difference signal is passed through the loop filter 14 to V
It is output to the CO 15 and the oscillation frequency of the VCO 15 is controlled to lock the phase so that the reproduced data and the clock are synchronized. At this time, the loop filter 14
The phase response characteristics of the PLL such as the frequency characteristic, the gain, and the sensitivity of the VCO 15 are set so as to sufficiently absorb the jitter generated by the head tape system of the VTR and make it difficult to respond to various noises.

As described above, the PLL for obtaining the clock of the A / D converter 5 is configured, and the eye opening is achieved by adjusting the lock phase of the PLL by, for example, adjusting the operating point of the phase detection circuit 13. The maximum point can be sampled.

The integrated and equalized signal is sampled by the A / D converter 5 controlled by the clock generated by the above-mentioned PLL and converted from data having an analog waveform into digital data. The reproduced signal converted into digital data is delayed by 2 clocks by the delay circuit 6, and the original signal is subtracted by the subtractor 7. By this operation, the integral equalized waveform is converted into a waveform having a PR (1,0, -1) characteristic, and its eye pattern has three values as shown in FIG. 11 (b).

Next, the PR (1,0, -1) signal is subjected to maximum likelihood decoding by the Viterbi decoding circuit 8.

The combination of the PR (1,0, -1) system and the Viterbi decoding is a digital V using high density magnetic recording.
It is often used in TR and the like, and it is possible to avoid poor low-frequency characteristics (S / N, waveform distortion, etc.) of the magnetic recording system and keep transmission errors to a minimum. The reproduction data decoded by the Viterbi decoding circuit 8 is corrected by the error correction circuit 9 for the error generated in the transmission path using the parity data added at the time of recording, and is output to the image decoding circuit 10. Image decoding circuit 10
Expands the information amount of the reproduction data compressed during recording, and D
Output to the / A converter 11. The D / A converter 11 converts the input digital data into analog data and outputs it to the output terminal 12
Output via.

[0015]

SUMMARY OF THE INVENTION In the above-mentioned device,
A clock is extracted from the analog signal output from the equalizer 4 by the PLL, and the output signal of the equalizer 4 is sampled by the A / D converter 5 using this clock.

However, in general, an analog-configured PLL circuit is difficult to maintain stability especially when the quality of a reproduced signal is low and high speed like a digital VTR, and it is necessary to adjust a sampling phase. There was a problem such as becoming.

An object of the present invention is to solve the above problems.

It is another object of the present invention to provide a device which stably extracts a clock from input data and has stable operation.

[0019]

SUMMARY OF THE INVENTION In order to solve the problems that have been conventionally encountered and to achieve the above-mentioned object, the present invention is an equalizing means for equalizing input data and sampling output data of the equalizing means. , Conversion means for converting to digital data,
Pattern detection means for detecting a specific pattern in the digital data, sampling means for sampling and holding the digital data according to the output of the pattern detection means, and phase synchronization with the input data according to the output of the sampling means Generating means for generating a clock,
Amplitude detecting means for detecting the amplitude of the input data, error detecting means for detecting an error in the digital data, and controlling the equalizing means according to the output of the amplitude detecting means and the output of the error detecting means. And a control means for performing the operation.

[0020]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 shows a digital V as an embodiment of the present invention.
FIG. 11 is a block diagram showing a configuration of a TR reproduction system, and those performing the same operation as in FIG.

First, the circuit for generating the operation clock of the A / D converter 5 in FIG. 1 will be described. In FIG.
16 is a digital phase detection circuit, which is a pattern detection circuit 17
And a latch circuit 18.

Reference numeral 19 is an amplitude detection circuit for detecting the amplitude level of the output signal of the amplifier 3, and this amplitude detection circuit 1
The output of 9 and the error flag output from the error correction circuit 9 are output to the CPU 20. The CPU 20 controls the equalization characteristic of the equalizer 4 based on the detection output of the amplitude detection circuit 19 and the error flag from the error correction circuit 9 as described later.

Reference numeral 21 is an arithmetic operation circuit, which performs an operation on the output signal of the equalizer 4 as described later, and a Viterbi decoding circuit 8, a pattern detection circuit 17 and a latch circuit 1.
8 is output.

In such a configuration, the pattern detection circuit 17 is supplied with the digital signals converted by the A / D converter 5, and detects a specific data pattern taken by these in time series. The latch circuit 18 latches the output of the arithmetic operation circuit 21 in accordance with the pattern detection output to obtain a signal corresponding to the phase difference between the reproduction signal and the A / D conversion clock.

FIG. 2 is a block diagram showing a specific configuration of the pattern detection circuit 16, the arithmetic operation circuit 21 and the latch circuit 18.

In the figure, reference numerals 211 to 214 denote N-1 for delaying the A / D-converted digital signal every clock.
Delay circuits connected to the stages, reference numeral 171 denotes delay circuits 211 to 2
14 is a decoder composed of a logical operation circuit for detecting a specific pattern from the output of 14.

Reference numeral 215 denotes a subtracter for subtracting the output of 213 from the output of the delay circuit 211 and converting it to data having the characteristic of PR (1,0, -1). The output of the subtractor 215 is a Viterbi decoding circuit. 8 and the switch 217, and also to the switch 217 via the inverting circuit 216. Here, the delay circuits 211 to 214, the subtractor 215,
The inverting circuit 216 and the switch 217 make up the arithmetic operation circuit 21.
Is composed.

The decoder 171 is supplied with the output data from the A / D converter 5 and the MSB of each output data from the delay circuits 211 to 214. In the present embodiment, the A / D converter 5 is quantized with a plurality of bits for one sample,
This MSB represents the data obtained by binarizing the data of each sample. The decoder 171 detects a specific pattern in the reproduction data based on these MSBs, controls the switch 217, and outputs a pattern detection pulse to the latch circuit 18.

Next, a specific pattern detecting operation will be described.

As shown in FIG. 3A, the recording signal is (...,
0, 1, 1, 1, 0, ...) Data pattern.

The signal equalized and integrated by the equalizer 4 (see FIG. 3).
(B)) is the arithmetic operation circuit 21 and + at three time points t0, t1, t2 as shown in FIG. 3 (c) (analog display).
It is converted into a PR (1,0, -1) waveform that changes as 1,0, -1.

Therefore, the data pattern taken by the data after A / D conversion on the time series is (0, 1, 1, 1,)
When the decoder 171 detects 0), a pattern detection pulse is generated. By latching the central point (t1) with this pattern detection pulse by the latch circuit 18, the phase difference between the reproduced data and the clock can be detected. The principle will be described below.

When the phase of the A / D conversion clock is ahead of the ideal case, as shown in FIG.
The value of 1 changes to + α. Further, when the phase of the A / D conversion clock is delayed, the value at the time point t1 changes to -α as shown in Fig. 5C. This means that the decoder 171 detects that the recorded data has a pattern of (0,1,1,1,0), and at that time, the time point t1 of the waveform of PR (1,0, -1) is By latching, it means that the phase difference between the reproduced data and the clock can be detected.

Here, as the specific data pattern,
The opposite (1,0,0,0,1) is also conceivable, in which case the PR (1,0, -1) waveform also has the phase detection characteristic inverted as shown in FIG. 6C.

Therefore, the decoder 171 outputs the data (1,
When it is detected that the pattern is 0,0,0,1),
By switching the switch 217 and supplying the output of the inverting circuit 216 to the latch circuit 18, operation is performed so that the phase detection characteristic is not inverted.

Hereinafter, after the output of the latch circuit 18 which is the phase detection data is filtered by the loop filter 14, it is converted into an analog signal by the D / A converter 22 and V
A PLL for controlling the phase of the clock is configured by outputting the output to the CO 15 and controlling the oscillation frequency.

The characteristics of the tape 1 often have quite different frequency characteristics depending on the manufacturer, grade and the like. On the other hand, it is considered that the characteristic of the equalizer 4 is automatically adjusted so as to minimize the error flag while monitoring the error flag obtained from the error correction circuit 9.

With the recent progress in tape technology, tapes such as metal evaporated tapes (ME tapes) having a significantly improved high-frequency output have begun to appear. If the characteristics of the equalizer 4 remain the optimum characteristics for the conventional tape having a low high-frequency output for such a high-output tape, the integrated waveform of the output signal of the equalizer 4 is as shown in FIG. The waveform has a fast rising edge. When a signal having such an integrated waveform is subjected to PR (1,0, −1) processing, the waveform becomes 0 not only at time point t1 but also before and after time point t1 as shown in FIG. Will be low.

If the tape has a higher high-frequency output, equalization by the equalizer 4 causes overcompensation.
Due to the ringing of the integrated waveform as shown in FIG.
As shown in FIG. 8C, it is possible that the PR (1,0, -1) waveform has a slope opposite to the actual slope near time t1.

If left as it is, the phase detection characteristic near the time point t1 becomes an inverse characteristic and the operation of the PLL does not converge, or a pseudo lock state in which the phase is locked to an abnormal phase is brought about. Therefore, if the high-frequency output of the tape increases, the number of errors originally decreases, but it is conceivable that the number of decoding errors will increase abnormally due to the malfunction of the PLL.

Therefore, in the present embodiment, the amplitude detection circuit 19 detects the amplitude level of the reproduction signal, and the CPU 20
A case where the error flag from the error correction circuit 9 is abnormally large, such as all errors, even if the amplitude level of the reproduced signal is sufficiently high, is detected, and the state is judged to be an abnormality of the PLL. When the CPU 20 determines that the PLL is abnormal, the high-frequency gain of the equalizer 4 is decreased by several dB for the reason described above, and the equalization characteristic is automatically adjusted again based on the error flag. For example, to expand the variable range of high frequency gain, PR (1,
0, -1) The processed waveform is smooth at time t1, and
The equalizer 4 is controlled so as to change monotonously in accordance with the actual waveform change corresponding to the data change.

By controlling the characteristics of the equalizer 4 in this manner, the PLL can be operated correctly even when data is reproduced from a tape having a large high frequency output, and a clock phase-synchronized with the reproduced data can be obtained. Obtainable. Therefore, high quality reproduction data can be obtained.

Further, since the noise can be suppressed to a low level by lowering the high frequency gain, the characteristics of the tape can be fully brought out and the decoding error can be reduced.

In the above embodiment, the specific data patterns (0, 1, 1, 1, 0) and (1, 0, 0,
0, 1) was used, but the present invention is not limited to this, and if the PR (1, 0, -1) waveform crosses 0 at time t1, among other patterns obtained with N bits, another data pattern is used. However, the same effect as that of the above-mentioned embodiment can be expected.

Further, in the above-mentioned embodiment, an example in which the binary detection data (MSB) obtained from the inputs of the delay circuits 211 to 214 and each stage is used as the pattern detection circuit has been described, but as another detection method, The PR (1, -1) method can also be used.

Further, in the above-described embodiment, the amplitude detection circuit 1
Although the amplitude level of the reproduction signal is detected by means of 9, the configuration may be such that a conventionally used dropout detection circuit detects data dropout. In this case, if there are many errors despite no dropout, it is determined that the PLL is abnormal.

Further, instead of the error flag, the abnormality of the PLL may be judged based on whether or not the sync data in the reproduced data is correctly detected.

In the above-described embodiment, an example in which the present invention is applied to a digital VTR has been described, but the present invention can be applied to the case of using other transmission lines such as sanitary communication and optical fiber communication, and the same applies. It has the effect of.

In the above embodiment, the amplitude level of the reproduction signal is detected based on the output of the amplifier 3, but the A / D
You may detect using the digital data after conversion.

[0051]

As is apparent from the above description, according to the present invention, the specific pattern in the digital data is detected and the clock is generated based on the digital signal extracted according to the detection timing. It is possible to generate a clock accurately synchronized with.

Further, since the equalizing means is controlled on the basis of the level of the input data and the error in the data, the clock generating operation can be kept normal even when the characteristic of the input data largely changes, and The characteristics of the equalizing means can also be optimally controlled.

Therefore, errors in the input data can be reduced, and extremely high quality data can be obtained.

Since the phase detection output is obtained directly from the digital signal, the clock can be stably extracted.

Therefore, the circuit can be made unadjusted and the error in the processing of the reproduced signal can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a digital VTR as an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a main part of the apparatus shown in FIG.

FIG. 3 is a diagram for explaining the operation of the circuit of FIG.

FIG. 4 is a diagram for explaining the operation of the circuit of FIG. 2;

5 is a diagram for explaining the operation of the circuit of FIG.

FIG. 6 is a diagram for explaining the operation of the circuit of FIG.

FIG. 7 is a diagram for explaining a control operation of characteristics of the equalization circuit of FIG.

FIG. 8 is a diagram for explaining a control operation of characteristics of the equalization circuit of FIG.

FIG. 9 is a diagram showing a configuration of a conventional digital VTR.

FIG. 10 is a diagram showing characteristics of a magnetic recording / reproducing system.

FIG. 11 is a diagram showing an eye pattern of reproduced data.

[Explanation of symbols]

 4 Equalizer 5 A / D Converter 17 Pattern Detection Circuit 18 Latch Circuit 19 Amplitude Detection Circuit 20 CPU 21 Arithmetic Operation Circuit

Continuation of the front page (51) Int.Cl. ⁶ Identification number Office reference number FI technical display location G11B 20/18 574 9558-5D G11B 20/18 574B

Claims (15)

[Claims] 1. An equalizing means for equalizing input data, a converting means for sampling output data of the equalizing means and converting it into digital data, and a pattern detecting means for detecting a specific pattern in the digital data. Sampling means for sampling and holding the digital data according to the output of the pattern detecting means, generating means for generating a clock phase-synchronized with the input data according to the output of the sampling means, and amplitude of the input data. Amplitude detecting means for detecting, error detecting means for detecting an error in the digital data, and control means for controlling the equalizing means according to the output of the amplitude detecting means and the output of the error detecting means. Data processing device. 2. The data processing device according to claim 1, wherein the detection unit detects a plurality of patterns different from each other as the specific pattern. 3. The generating means has an extracting means for extracting a part of the digital data according to the output of the pattern detecting means, and the sampling means samples the difference of the digital data extracted by the extracting means. The data processing device according to claim 1, wherein the data processing device holds the data. 4. The generating means includes a loop filter for filtering the output of the sampling means, and a transmitting means for generating a signal having a frequency according to the output of the loop filter, and the output of the transmitting means is the clock. The data processing apparatus according to claim 1, wherein the data processing apparatus outputs the data as. 5. The data processing apparatus according to claim 1, wherein the conversion means performs the conversion operation according to the clock. 6. The control means reduces the high frequency gain of the equalization means when the amplitude of the input data is larger than a predetermined level and the number of errors in the digital data is larger than a predetermined number. The signal processing device according to claim 1, wherein: 7. An input means for inputting data whose amplitude varies in an analog manner, an equalizing means for equalizing the input data, and a converting means for sampling output data of the equalizing means and converting it into digital data. A pattern detecting unit for detecting a specific pattern in the digital data by using continuous N samples (N ≧ 3) of the digital data converted by the converting unit; Generating means for generating a clock phase-synchronized with the input data, an amplitude detecting means for detecting the amplitude of the input data, a detecting means for detecting an error in the digital data, an output of the amplitude detecting means and the A data processing device comprising: a control unit that controls the equalization unit according to the output of the error detection unit. 8. A delay means for delaying digital data from said conversion means, and a subtraction means for subtracting output data of said delay means from input data of said delay means. Data processing equipment. 9. The pattern detecting means detects, as the specific pattern, a pattern in which a zero-cross point occurs between a plurality of samples of digital data continuously output from the subtracting means. The data processing device according to. 10. The data processing apparatus according to claim 7, wherein the detection unit detects a plurality of patterns different from each other as the specific pattern. 11. The generating means latches the digital data output from the converting means in response to the output of the pattern detecting means, a loop filter for filtering the output of the latching means, and the loop filter. 8. The data processing device according to claim 7, further comprising: a transmission unit that generates a signal having a frequency according to the output of the output unit, and outputs the output of the transmission unit as the clock. 12. The pattern detecting means has delay means connected to N−1 stages for delaying the digital data from the converting means by N clocks (N ≧ 2), and the digital data from the converting means and the delay means are connected to each other. 2 digital data of N + 1 samples obtained from each stage of the delay means
8. The data processing device according to claim 7, wherein the specific pattern is detected by performing a value determination and using N + 1 bit data obtained as a result of the determination. 13. The data processing apparatus according to claim 7, wherein the control unit changes a high frequency gain of the equalization unit. 14. The data processing apparatus according to claim 7, wherein the conversion means performs the conversion operation according to the clock. 15. An equalizer for equalizing input data, an amplitude detector for detecting an amplitude of the input data, an error detector for detecting an error in the input data, and an output of the amplitude detector. A data processing apparatus comprising: a control unit that controls the equalization unit according to the output of the error detection unit.