[go: up one dir, main page]

JPH10301851A - データ処理システム内のキャッシュ・メモリ・データを投機的に供給する方法及びシステム - Google Patents

データ処理システム内のキャッシュ・メモリ・データを投機的に供給する方法及びシステム

Info

Publication number
JPH10301851A
JPH10301851A JP10096007A JP9600798A JPH10301851A JP H10301851 A JPH10301851 A JP H10301851A JP 10096007 A JP10096007 A JP 10096007A JP 9600798 A JP9600798 A JP 9600798A JP H10301851 A JPH10301851 A JP H10301851A
Authority
JP
Japan
Prior art keywords
data
processing
cache
response
processing device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10096007A
Other languages
English (en)
Japanese (ja)
Inventor
Kumar Arimiri Ravi
ラヴィ・カマー・アライミリ
Stephen Doddson John
ジョン・スティーブン・ドッドソン
Don Lewis Jerry
ジェリー・ドン・リュイス
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of JPH10301851A publication Critical patent/JPH10301851A/ja
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
    • G06F12/0868—Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP10096007A 1997-04-14 1998-04-08 データ処理システム内のキャッシュ・メモリ・データを投機的に供給する方法及びシステム Pending JPH10301851A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US83411797A 1997-04-14 1997-04-14
US08/834117 1997-04-14

Publications (1)

Publication Number Publication Date
JPH10301851A true JPH10301851A (ja) 1998-11-13

Family

ID=25266163

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10096007A Pending JPH10301851A (ja) 1997-04-14 1998-04-08 データ処理システム内のキャッシュ・メモリ・データを投機的に供給する方法及びシステム

Country Status (6)

Country Link
JP (1) JPH10301851A (zh)
KR (1) KR100277446B1 (zh)
CN (1) CN1110755C (zh)
CA (1) CA2231361A1 (zh)
SG (1) SG68034A1 (zh)
TW (1) TW386192B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008197716A (ja) * 2007-02-08 2008-08-28 Nec Corp データ一貫性制御システム及びデータ一貫性制御方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW480404B (en) * 1999-08-31 2002-03-21 Ibm Memory card with signal processing element

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0349123B1 (en) * 1988-06-27 1995-09-20 Digital Equipment Corporation Multi-processor computer systems having shared memory and private cache memories
US5191649A (en) * 1990-12-21 1993-03-02 Intel Corporation Multiprocessor computer system with data bus and ordered and out-of-order split data transactions
US5572702A (en) * 1994-02-28 1996-11-05 Intel Corporation Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
US5613153A (en) * 1994-10-03 1997-03-18 International Business Machines Corporation Coherency and synchronization mechanisms for I/O channel controllers in a data processing system
US5581729A (en) * 1995-03-31 1996-12-03 Sun Microsystems, Inc. Parallelized coherent read and writeback transaction processing system for use in a packet switched cache coherent multiprocessor system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008197716A (ja) * 2007-02-08 2008-08-28 Nec Corp データ一貫性制御システム及びデータ一貫性制御方法

Also Published As

Publication number Publication date
CN1110755C (zh) 2003-06-04
KR100277446B1 (ko) 2001-01-15
CA2231361A1 (en) 1998-10-14
CN1197956A (zh) 1998-11-04
TW386192B (en) 2000-04-01
SG68034A1 (en) 1999-10-19
KR19980079625A (ko) 1998-11-25

Similar Documents

Publication Publication Date Title
US7120755B2 (en) Transfer of cache lines on-chip between processing cores in a multi-core system
US6785776B2 (en) DMA exclusive cache state providing a fully pipelined input/output DMA write mechanism
JP3280207B2 (ja) Ｉ／ｏチャネル・コントローラ、多重プロセッサ・システム、キャッシュ・コヒーレンシを維持する方法、ｉ／ｏ同期を提供する方法
EP1311956B1 (en) Method and apparatus for pipelining ordered input/output transactions in a cache coherent, multi-processor system
US5751995A (en) Apparatus and method of maintaining processor ordering in a multiprocessor system which includes one or more processors that execute instructions speculatively
EP0514024B1 (en) Method and apparatus for an improved memory architecture
EP0743601A2 (en) A system and method for improving cache performance in a multiprocessing system
US5895484A (en) Method and system for speculatively accessing cache memory data within a multiprocessor data-processing system using a cache controller
JPH09138779A (ja) スヌープ処理方法
US6553442B1 (en) Bus master for SMP execution of global operations utilizing a single token with implied release
JP2000227908A (ja) 共用介入サポ―トを有する不均等メモリ・アクセス（ｎｕｍａ）デ―タ処理システム
US20060064518A1 (en) Method and system for managing cache injection in a multiprocessor system
JP4409619B2 (ja) 情報処理装置、制御装置および制御方法
JPH1031625A (ja) マルチ・プロセッサ・システムにおける改良されたコピーバック性能のためのライトバック・バッファ
US5263144A (en) Method and apparatus for sharing data between processors in a computer system
US5611074A (en) Efficient polling technique using cache coherent protocol
US20040111563A1 (en) Method and apparatus for cache coherency between heterogeneous agents and limiting data transfers among symmetric processors
US5987544A (en) System interface protocol with optional module cache
US6507880B1 (en) Bus protocol, bus master and bus snooper for execution of global operations utilizing multiple tokens
US6973541B1 (en) System and method for initializing memory within a data processing system
US5924118A (en) Method and system for speculatively sourcing cache memory data prior to upstream cache invalidation within a multiprocessor data-processing system
US6480915B1 (en) Bus protocol and token manager for SMP execution of global operations utilizing a single token with implied release
JP3550092B2 (ja) キャッシュ装置及び制御方法
US6460101B1 (en) Token manager for execution of global operations utilizing multiple tokens
US6055608A (en) Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system

Legal Events

Date Code Title Description
A601 Written request for extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A601

Effective date: 20051011

A602 Written permission of extension of time

Free format text: JAPANESE INTERMEDIATE CODE: A602

Effective date: 20051014