JPH10284645A - Resin sealing structure of semiconductor chip and method of manufacturing the same - Google Patents
Resin sealing structure of semiconductor chip and method of manufacturing the sameInfo
- Publication number
- JPH10284645A JPH10284645A JP9082807A JP8280797A JPH10284645A JP H10284645 A JPH10284645 A JP H10284645A JP 9082807 A JP9082807 A JP 9082807A JP 8280797 A JP8280797 A JP 8280797A JP H10284645 A JPH10284645 A JP H10284645A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- semiconductor chip
- sealing
- bank
- shaped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
Landscapes
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
(57)【要約】
【課題】回路基板上に固着した半導体チップ及び金属細
線を覆う封止用の樹脂の流れを防止する樹脂封止構造及
びその製造方法を提供する。
【解決手段】回路基板１上には回路パターン２が形成さ
れ、半導体チップ３が固着され、回路パターン２と半導
体チップ３は金属細線５で接続されている。半導体チッ
プ３及び金属細線５を囲むように土手状のエポキシ系樹
脂６が形成され、土手状のエポキシ系樹脂６で囲まれた
領域内の半導体チップ３及び金属細線５を覆うように封
止用の樹脂７が形成される。土手状のエポキシ系樹脂６
の粘度は封止用の樹脂７のそれよりも高いものである。
また製造方法としては土手状及び封止用の樹脂６，７を
順次に吐出し形成後に、両者を同時に熱処理して硬化す
る。
(57) Abstract: Provided is a resin sealing structure for preventing a flow of a sealing resin covering a semiconductor chip and a fine metal wire fixed on a circuit board, and a method of manufacturing the same. A circuit pattern is formed on a circuit board, a semiconductor chip is fixed, and the circuit pattern and the semiconductor chip are connected by a thin metal wire. A bank-shaped epoxy resin 6 is formed so as to surround the semiconductor chip 3 and the thin metal wires 5, and is used for sealing so as to cover the semiconductor chip 3 and the thin metal wires 5 in a region surrounded by the bank-shaped epoxy resin 6. Is formed. Bank-like epoxy resin 6
Is higher than that of the sealing resin 7.
As a manufacturing method, after the bank-shaped and sealing resins 6 and 7 are sequentially discharged and formed, both are heat-treated and cured at the same time.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、回路基板上に固着
した半導体チップを封止する封止用の樹脂の流れを防止
する構造及びその製造方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for preventing the flow of a sealing resin for sealing a semiconductor chip fixed on a circuit board, and a method of manufacturing the same.
【０００２】[0002]
【従来の技術】図２（ａ）及び（ｂ）に、回路基板上に
固着した半導体チップを封止する封止用の樹脂の流れを
防止する従来の構造の例を示す。回路基板１１上には回
路パターン１２が形成されており、半導体チップ１３は
回路基板１１に接着用の樹脂１４で固着され、回路パタ
ーン１２と半導体チップ１３とは金線などの金属細線１
５により接続されている。回路基板１１上の半導体チッ
プ１３を囲むように土手状のシリコーン系樹脂１６を形
成する。この土手状のシリコーン系樹脂１６はディスペ
ンサー（図示していない）により吐出されて形成され
る。その後、例えばおおよそ１００〜１５０℃で１時間
程度の熱処理をして土手状のシリコーン系樹脂１６を硬
化させる。次いで、半導体チップ１３及び金属細線１５
を封止用のエポキシ系樹脂１７で封止する。この封止用
のエポキシ系樹脂１７もディスペンサー（図示していな
い）により吐出されて形成される。その後、例えば、１
００〜１２０℃で１時間程度の熱処理をして封止用のエ
ポキシ系樹脂１７を硬化させる。2. Description of the Related Art FIGS. 2A and 2B show an example of a conventional structure for preventing a flow of a sealing resin for sealing a semiconductor chip fixed on a circuit board. A circuit pattern 12 is formed on a circuit board 11, a semiconductor chip 13 is fixed to the circuit board 11 with an adhesive resin 14, and the circuit pattern 12 and the semiconductor chip 13 are formed of a thin metal wire 1 such as a gold wire.
5 are connected. A bank-shaped silicone resin 16 is formed so as to surround the semiconductor chip 13 on the circuit board 11. The bank-like silicone resin 16 is formed by being discharged by a dispenser (not shown). Thereafter, for example, heat treatment is performed at about 100 to 150 ° C. for about one hour to cure the bank-like silicone resin 16. Next, the semiconductor chip 13 and the fine metal wire 15
Is sealed with an epoxy resin 17 for sealing. The epoxy resin 17 for sealing is also discharged and formed by a dispenser (not shown). Then, for example, 1
The epoxy resin 17 for sealing is cured by performing a heat treatment at 00 to 120 ° C. for about 1 hour.
【０００３】[0003]
【発明が解決しようとする課題】従来の技術では、回路
基板１１上の半導体チップ１３及び金属細線１５を囲む
土手状の樹脂１６はシリコーン系樹脂を用い、半導体チ
ップ１３及び金属細線１５を封止する封止用の樹脂１７
はエポキシ系樹脂を用いていた。シリコーン系樹脂とエ
ポキシ系樹脂との異なる樹脂を用いており、これらの樹
脂の境界面では樹脂同士の融合はおこらずにただ接して
いるのみである。したがって、両者の樹脂間に僅かな隙
間２０が生じてしまうことがあり、この隙間２０が水分
等の侵入経路となる。水分等の侵入が生じると半導体チ
ップ１３及び回路パターン１２などが劣化したりショー
トしたりしてしまうことがある。According to the prior art, the bank-shaped resin 16 surrounding the semiconductor chip 13 and the fine metal wires 15 on the circuit board 11 uses a silicone resin to seal the semiconductor chip 13 and the fine metal wires 15. Sealing resin 17
Used an epoxy resin. A resin different from a silicone-based resin and an epoxy-based resin is used. At the interface between these resins, the resins are merely in contact with each other without fusion. Therefore, a slight gap 20 may be formed between the two resins, and this gap 20 serves as a path for water and the like to enter. If moisture or the like enters, the semiconductor chip 13 and the circuit pattern 12 may be deteriorated or short-circuited.
【０００４】また、シリコーン系樹脂を熱処理により硬
化した後でエポキシ系樹脂を熱処理により硬化するが、
両方の熱処理のための炉を共用にすると、エポキシ系樹
脂が硬化しない場合などがあるので、炉を共用にするこ
とはできなかった。このような問題に鑑み、本発明の目
的は、半導体チップを封止する封止用の樹脂の流れを防
止するとともに土手状の樹脂と封止用の樹脂との親和性
の向上を図ることのできる半導体チップの樹脂封止構造
及びその製造方法を提供するものである。[0004] Further, after the silicone resin is cured by heat treatment, the epoxy resin is cured by heat treatment.
If a furnace for both heat treatments is used in common, the epoxy resin may not be cured in some cases, so that the furnace cannot be used in common. In view of such problems, an object of the present invention is to prevent the flow of a sealing resin for sealing a semiconductor chip and to improve the affinity between a bank-like resin and the sealing resin. The present invention provides a resin sealing structure for a semiconductor chip and a method for manufacturing the same.
【０００５】[0005]
【課題を解決するための手段】上記の課題を解決する手
段としては、回路パターンを有する回路基板上に固着さ
れ、この回路パターンと金属細線によって接続された半
導体チップの樹脂封止構造において、前記半導体チップ
及び金属細線を囲むように形成された土手状の樹脂と、
該土手状の樹脂で囲まれた領域内で前記半導体チップ及
び金属細線を封止するように形成された封止用の樹脂と
からなり、前記土手状の樹脂と封止用の樹脂とは同系の
樹脂であるものとする。Means for solving the above-mentioned problems include a resin sealing structure of a semiconductor chip fixed on a circuit board having a circuit pattern and connected to the circuit pattern by a thin metal wire. A bank-shaped resin formed so as to surround the semiconductor chip and the fine metal wire,
A sealing resin formed so as to seal the semiconductor chip and the fine metal wires in a region surrounded by the bank-shaped resin, wherein the bank-shaped resin and the sealing resin are of the same type; Resin.
【０００６】このようにすると、半導体チップ及び金属
細線を封止する封止用の樹脂の流れを土手状の樹脂によ
って防止することができ、土手状の樹脂と封止用の樹脂
とを同系の樹脂とすることで、不要な化学反応を生じる
ことなく、良く融合した親和性の優れた樹脂封止構造に
できる。また、前記土手状の樹脂の粘度が封止用の樹脂
のそれよりも高いものとすると有効である。前記土手状
の樹脂の粘度及びチクソトロピック性が封止用の樹脂の
それよりも高いものとすると効果的である。そして、前
記土手状の樹脂及び封止用の樹脂は、エポキシ系樹脂、
アクリル系樹脂およびフエノール系樹脂のうちいずれか
一つであることで良い。With this configuration, the flow of the sealing resin for sealing the semiconductor chip and the fine metal wire can be prevented by the bank-like resin, and the bank-like resin and the sealing resin are of the same type. By using a resin, it is possible to form a well-fused resin sealing structure with excellent affinity without generating unnecessary chemical reactions. It is also effective that the bank-like resin has a higher viscosity than that of the sealing resin. It is effective if the viscosity and thixotropic properties of the bank-like resin are higher than those of the sealing resin. The bank-like resin and the sealing resin are epoxy resins,
Any one of an acrylic resin and a phenolic resin may be used.
【０００７】さらに、製造方法としては、同系の前記土
手状の樹脂及び封止用の樹脂をそれぞれ吐出して形成後
に、同時に熱処理して硬化させることが有効である。Further, as a manufacturing method, it is effective that the bank-like resin and the sealing resin of the same system are respectively formed by discharging and then heat-treated at the same time.
【０００８】[0008]
【発明の実施の形態】この発明の実施の形態を図１
（ａ）及び（ｂ）に基づいて説明する。図１（ａ）及び
（ｂ）は、回路基板上に固着した半導体チップを封止す
る封止用の樹脂の流れを防止する構造を示している。土
手状の樹脂と封止用の樹脂とを同系の樹脂として親和性
の向上を図っている。回路基板としては例えば金属絶縁
基板などがある。FIG. 1 shows an embodiment of the present invention.
A description will be given based on (a) and (b). FIGS. 1A and 1B show a structure for preventing the flow of a sealing resin for sealing a semiconductor chip fixed on a circuit board. The affinity of the bank-shaped resin and the sealing resin is improved by using the same resin. Examples of the circuit board include a metal insulating board.
【０００９】回路基板１上には絶縁層を介して銅箔など
からなる回路パターン２が形成されており、半導体チッ
プ３は回路基板１に接着用の樹脂４で固着され、回路パ
ターン２と半導体チップ３とは金線などの金属細線５に
より接続されている。回路基板１上の半導体チップ３及
び金属細線５を囲むように土手状のエポキシ系樹脂６が
硬化形成されている。その土手の高さは例えば２ｍｍ程
度である。土手状の樹脂６の硬化前の粘度はおよそ５０
００〜１００００Ｐａ・ｓである。そして土手状のエポ
キシ系樹脂６をチクソトロピック性（せん断力が加わっ
ているときだけ粘度が低下する特性のこと）の高い樹脂
とすると後述するように所望の形状に形成し易くなりさ
らによい。半導体チップ３及び金属細線５は封止用のエ
ポキシ系樹脂７で封止されており、この封止用のエポキ
シ系樹脂７は土手状のエポキシ系樹脂６でせき止められ
た状態で硬化形成されている。封止用のエポキシ系樹脂
７の硬化前の粘度はおよそ１０００Ｐａ・ｓである。A circuit pattern 2 made of copper foil or the like is formed on a circuit board 1 via an insulating layer. A semiconductor chip 3 is fixed to the circuit board 1 with an adhesive resin 4, and the circuit pattern 2 and the semiconductor The chip 3 is connected by a thin metal wire 5 such as a gold wire. A bank-like epoxy resin 6 is formed by curing so as to surround the semiconductor chip 3 and the fine metal wires 5 on the circuit board 1. The height of the bank is, for example, about 2 mm. The viscosity of the bank-like resin 6 before curing is about 50
00 to 10000 Pa · s. When the bank-like epoxy resin 6 is a resin having high thixotropic property (a property that the viscosity is reduced only when a shearing force is applied), it becomes easier to form a desired shape as described later, which is more preferable. The semiconductor chip 3 and the thin metal wires 5 are sealed with an epoxy resin 7 for sealing, and the epoxy resin 7 for sealing is hardened and formed with the epoxy resin 6 in a bank shape being blocked. I have. The viscosity of the epoxy resin 7 for sealing before curing is about 1000 Pa · s.
【００１０】次に、製造方法について述べる。回路パタ
ーン２が形成されている回路基板１上に半導体チップ３
を接着用の樹脂４により固着する。回路パターン２と半
導体チップ３とは金線などの金属細線５により接続す
る。回路基板１上の半導体チップ３及び金属細線５を囲
むように土手状のエポキシ系樹脂６を形成する。この土
手状のエポキシ系樹脂６はディスペンサー（図示してい
ない）により吐出して形成する。土手状のエポキシ系樹
脂６の粘度はおよそ５０００〜１００００Ｐａ・ｓであ
るので、半導体チップ３及び金属細線５を囲む土手状の
エポキシ系樹脂６を所望の形状に容易に形成することが
できる。さらに、土手状のエポキシ系樹脂６をチクソト
ロピック性の高い樹脂とすると、ディスペンサーにより
吐出されるときに、粘度が低下して所望の形状にし易
く、回路基板１上に達すると元の高い粘度に戻るのでそ
の形状が崩れにくく、半導体チップ３及び金属細線５を
囲む土手状の樹脂６を所望の形状により一層容易に形成
することができる。次いで、半導体チップ３及び金属細
線５を封止用のエポキシ系樹脂７により封止する。この
封止用のエポキシ系樹脂７は土手状のエポキシ系樹脂６
により囲まれた領域内で半導体チップ３及び金属細線５
を封止するようにディスペンサー（図示していない）に
より吐出し形成される。この封止用のエポキシ系樹脂７
の粘度はおよそ１０００Ｐａ・ｓであり、粘度の低い、
流れ性の良い樹脂であるので、短時間で吐出し形成する
ことができる。その後、例えば１００〜１２０℃で１時
間程度の熱処理をして土手状及び封止用のエポキシ系樹
脂６、７を同時に硬化させる。このように土手状及び封
止用のエポキシ系樹脂６、７を同時に硬化させると、両
者は同系の樹脂であるからよく融合して親和性が非常に
良く、また不要な化学的反応も起こらない。さらに、両
者は同系の樹脂なので熱処理用の炉を別々に管理する必
要はなく一つでよい。Next, a manufacturing method will be described. A semiconductor chip 3 is provided on a circuit board 1 on which a circuit pattern 2 is formed.
Is fixed with an adhesive resin 4. The circuit pattern 2 and the semiconductor chip 3 are connected by a thin metal wire 5 such as a gold wire. A bank-shaped epoxy resin 6 is formed so as to surround the semiconductor chip 3 and the fine metal wires 5 on the circuit board 1. The bank-shaped epoxy resin 6 is formed by discharging with a dispenser (not shown). Since the viscosity of the bank-like epoxy resin 6 is approximately 5000 to 10000 Pa · s, the bank-like epoxy resin 6 surrounding the semiconductor chip 3 and the thin metal wire 5 can be easily formed into a desired shape. Further, when the bank-shaped epoxy resin 6 is made of a resin having a high thixotropic property, the viscosity decreases when the resin is discharged by the dispenser, so that the resin easily becomes a desired shape. Since it returns, the shape is not easily collapsed, and the bank-shaped resin 6 surrounding the semiconductor chip 3 and the thin metal wire 5 can be more easily formed in a desired shape. Next, the semiconductor chip 3 and the thin metal wires 5 are sealed with an epoxy resin 7 for sealing. The epoxy resin 7 for sealing is a bank-like epoxy resin 6
Semiconductor chip 3 and metal thin wire 5 in a region surrounded by
Is formed by discharging with a dispenser (not shown) so as to seal. This sealing epoxy resin 7
Has a viscosity of about 1000 Pa · s, and has a low viscosity.
Since the resin has good flowability, it can be formed by discharging in a short time. Thereafter, heat treatment is performed, for example, at 100 to 120 ° C. for about 1 hour to simultaneously cure the bank-like and sealing epoxy resins 6 and 7. When the bank-like and sealing epoxy resins 6 and 7 are simultaneously cured as described above, the two resins are the same type of resin and are well fused to each other so that the affinity is very good and unnecessary chemical reaction does not occur. . Furthermore, since both are the same type of resin, it is not necessary to separately manage the furnaces for heat treatment, and one may be used.
【００１１】上記の実施の形態の場合、土手状及び封止
用のエポキシ系樹脂６，７を同時に熱処理して硬化する
製造方法を示したが、別の製造方法として、土手状のエ
ポキシ系樹脂６を吐出形成し熱処理して硬化した後に、
封止用のエポキシ系樹脂７を吐出形成し熱処理して硬化
することでもよい。ただし、両樹脂６，７の親和性とし
ては同時に熱処理して硬化する方が優れている。In the case of the above embodiment, the manufacturing method in which the bank-shaped and sealing epoxy resins 6 and 7 are simultaneously heat-treated and cured has been described. As another manufacturing method, a bank-shaped epoxy resin is used. After forming and heat-treating and hardening 6
The sealing epoxy resin 7 may be formed by ejection, heat-treated and cured. However, it is better for both resins 6 and 7 to be cured by heat treatment at the same time.
【００１２】また上記の実施の形態では、土手状及び封
止用の樹脂としてエポキシ系樹脂の例を示したが、この
ほかにアクリル系樹脂、フェノール系樹脂などを用いる
こともできる。フェノール系樹脂では高い耐湿性を必要
とする場合にその表面にワックスを形成することもあ
る。In the above embodiment, an epoxy resin is used as the bank-like and sealing resin. However, an acrylic resin, a phenol resin, or the like may be used. A phenolic resin may form a wax on its surface when high moisture resistance is required.
【００１３】[0013]
【発明の効果】本発明によれば、半導体チップ及び金属
細線を囲むように形成された土手状の樹脂と、この土手
状の樹脂で囲まれた領域内で半導体チップ及び金属細線
を封止するように形成された封止用の樹脂とからなり、
土手状の樹脂と封止用の樹脂とは同系の樹脂としたの
で、土手状の樹脂及び封止用の樹脂の境界面は良く融合
して境界面におけるピンホールや隙間のない樹脂封止構
造とすることができる。また土手状の樹脂の粘度を、あ
るいは粘度及びチクソトロピック性を封止用の樹脂のそ
れよりも高くしたので、土手状の樹脂を任意の形状に容
易に形成することができるとともに、封止用の樹脂の流
れ性を良くしたので短時間で容易に吐出形成することが
できる。さらに、製造方法においては、同系の樹脂であ
る土手状及び封止用の樹脂をそれぞれ吐出して形成後に
同時に熱処理をするので、熱処理工程の低減を図ること
ができるとともに熱処理用の炉を一つにできる。According to the present invention, a bank-shaped resin formed so as to surround a semiconductor chip and a thin metal wire, and the semiconductor chip and the thin metal wire are sealed in a region surrounded by the bank-shaped resin. Consisting of a sealing resin formed as
Since the bank-like resin and the sealing resin are of the same type, the boundary surface between the bank-like resin and the sealing resin is fused well, so that there is no pinhole or gap at the boundary surface. It can be. In addition, the viscosity of the bank-shaped resin, or the viscosity and thixotropic properties are higher than those of the sealing resin, so that the bank-shaped resin can be easily formed into an arbitrary shape and the sealing resin can be easily formed. Since the flowability of the resin is improved, the discharge can be easily formed in a short time. Furthermore, in the manufacturing method, the bank-like resin and the sealing resin, which are the same type of resin, are respectively discharged and heat-treated at the same time after the formation, so that the heat-treatment process can be reduced and one heat-treatment furnace can be used. Can be.
【図１】本発明の回路基板上に形成された半導体チップ
及び金属細線を囲む樹脂封止構造で、（ａ）は平面図、
（ｂ）は（ａ）の平面図のＡ−Ａ線における断面図FIG. 1 is a resin sealing structure surrounding a semiconductor chip and a thin metal wire formed on a circuit board of the present invention, wherein (a) is a plan view,
(B) is a cross-sectional view taken along line AA of the plan view of (a).
【図２】従来の技術の回路基板上に形成された半導体チ
ップ及び金属細線を囲む樹脂封止構造で、（ａ）は平面
図、（ｂ）は（ａ）の平面図のＢ−Ｂ線における断面図FIG. 2 is a resin sealing structure surrounding a semiconductor chip and a thin metal wire formed on a circuit board according to a conventional technique, wherein (a) is a plan view and (b) is a BB line of the plan view of (a). Cross section in
１、１１ 回路基板 ２、１２ 回路パターン ３、１３ 半導体チップ ４、１４ 接着用樹脂 ５、１５ 金属細線 ６ 土手状のシリコーン系樹脂 ７、１７ 封止用のエポキシ系樹脂 １６ 土手状のエポキシ系樹脂 ２０ 隙間 DESCRIPTION OF SYMBOLS 1, 11 Circuit board 2, 12 Circuit pattern 3, 13 Semiconductor chip 4, 14 Adhesive resin 5, 15 Thin metal wire 6 Bank-like silicone resin 7, 17 Epoxy resin for sealing 16 Bank-like epoxy resin 20 gaps
Claims (5)
れ、この回路パターンと金属細線によって接続された半
導体チップの樹脂封止構造において、前記半導体チップ
及び金属細線を囲むように形成された土手状の樹脂と、
該土手状の樹脂で囲まれた領域内で前記半導体チップ及
び金属細線を封止するように形成された封止用の樹脂と
からなり、前記土手状の樹脂と封止用の樹脂とは同系の
樹脂であることを特徴とする半導体チップの樹脂封止構
造。1. A resin sealing structure of a semiconductor chip fixed on a circuit board having a circuit pattern and connected to the circuit pattern by a thin metal wire, a bank-like shape formed so as to surround the semiconductor chip and the thin metal wire. Resin and
A sealing resin formed so as to seal the semiconductor chip and the fine metal wires in a region surrounded by the bank-shaped resin, wherein the bank-shaped resin and the sealing resin are of the same type; A resin sealing structure for a semiconductor chip, characterized in that the resin sealing resin is a resin.
脂のそれよりも高いことを特徴とする請求項１記載の半
導体チップの樹脂封止構造。2. The resin sealing structure for a semiconductor chip according to claim 1, wherein the viscosity of the bank-like resin is higher than that of the sealing resin.
ック性が封止用の樹脂のそれよりも高いことを特徴とす
る請求項１記載の半導体チップの樹脂封止構造。3. The resin sealing structure for a semiconductor chip according to claim 1, wherein the viscosity and thixotropic properties of the bank-like resin are higher than those of the sealing resin.
ポキシ系樹脂、アクリル系樹脂及びフエノール系樹脂の
うちいずれか一つであることを特徴とする請求項１，２
又は３に記載の半導体チップの樹脂封止構造。4. The resin according to claim 1, wherein the bank-like resin and the sealing resin are one of an epoxy resin, an acrylic resin and a phenol resin.
Or the resin sealing structure of the semiconductor chip of 3 described.
ぞれ吐出して形成後に、同時に熱処理をして硬化させる
ことを特徴とする請求項４記載の半導体チップの樹脂封
止構造の製造方法。5. The method of manufacturing a resin sealing structure for a semiconductor chip according to claim 4, wherein the bank-shaped resin and the sealing resin are respectively formed by discharging and then simultaneously heat-treated and cured. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9082807A JPH10284645A (en) | 1997-04-01 | 1997-04-01 | Resin sealing structure of semiconductor chip and method of manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9082807A JPH10284645A (en) | 1997-04-01 | 1997-04-01 | Resin sealing structure of semiconductor chip and method of manufacturing the same |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH10284645A true JPH10284645A (en) | 1998-10-23 |
Family
ID=13784691
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9082807A Pending JPH10284645A (en) | 1997-04-01 | 1997-04-01 | Resin sealing structure of semiconductor chip and method of manufacturing the same |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH10284645A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8520178B2 (en) | 2006-07-04 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device with electrode having frame shape |
-
1997
- 1997-04-01 JP JP9082807A patent/JPH10284645A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8520178B2 (en) | 2006-07-04 | 2013-08-27 | Semiconductor Energy Laboratory Co., Ltd. | Method for manufacturing display device with electrode having frame shape |
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