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JPH10284514A - Structure of area array package type semiconductor device - Google Patents

Structure of area array package type semiconductor device

Info

Publication number
JPH10284514A
JPH10284514A JP9093574A JP9357497A JPH10284514A JP H10284514 A JPH10284514 A JP H10284514A JP 9093574 A JP9093574 A JP 9093574A JP 9357497 A JP9357497 A JP 9357497A JP H10284514 A JPH10284514 A JP H10284514A
Authority
JP
Japan
Prior art keywords
chip
package
bonding
package body
type substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9093574A
Other languages
Japanese (ja)
Other versions
JP3707639B2 (en
Inventor
Tadahiro Morifuji
忠洋 森藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Rohm Co Ltd
Original Assignee
Rohm Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Rohm Co Ltd filed Critical Rohm Co Ltd
Priority to JP09357497A priority Critical patent/JP3707639B2/en
Publication of JPH10284514A publication Critical patent/JPH10284514A/en
Application granted granted Critical
Publication of JP3707639B2 publication Critical patent/JP3707639B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92247—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01047—Silver [Ag]
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    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To prevent generation of cracks in a package body or a bonding part with a board by providing a fine strip non-bonding part which lowers bonding property of a package body to an upper surface of a chip-type board so that one end thereof faces an outer circumferential part of an IC chip and the other end faces an outer circumferential part of a package body. SOLUTION: When each bonding pad 5 and a chip pad 8 of a chip-type board are formed, a non-bonding pattern 7 formed of a metallic foil such as copper is formed to a fine strip simultaneously, and one end thereof is connected integrally from the chip pad 8 and the other end is formed to face an outer circumferential surface of a chip-type board. Therefore, when a package body 11 is formed, adhesion of the synthetic resin package body 11 to the non-bonding pattern 7 formed of a metallic foil such as copper lowers, vapor of water and volatile element remaining inside the package 11 during soldering mounting escapes along the non-bonding pattern 7 and a pressure inside of the package body 11 does not rise, thus reducing generation of cracks of a bonding part.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、ＩＣチップを、下
面に多数個の外部接続用端子電極をマトリックス状に設
けたチップ型基板の上面に、当該ＩＣチップにおける多
数個の電極パッドが前記チップ型基板の下面における各
外部接続用端子電極の各々に電気的に接続するように搭
載し、且つ、前記チップ型基板に、ＩＣチップの部分を
密封する合成樹脂製のパッケージ体を成形して成るエリ
アアレイパッケージ型半導体装置の構造に関するもので
ある。BACKGROUND OF THE INVENTION The present invention relates to a chip type substrate in which an IC chip is provided with a plurality of external connection terminal electrodes in a matrix on a lower surface. A package made of a synthetic resin that is mounted so as to be electrically connected to each of the external connection terminal electrodes on the lower surface of the mold substrate and that seals an IC chip portion on the chip-type substrate. The present invention relates to a structure of an area array package type semiconductor device.

【０００２】[0002]

【従来の技術と発明が解決しようとする課題】従来、こ
の種のエリアアレイパッケージ（ＣＳＰ）型半導体装置
は、チップ型基板の上面にＩＣチップをペーストを使用
して固着している。この固着に際して使用した前記ペー
ストは、前記チップ型基板の上面に対してパッケージ体
を成形するまで間において加熱による乾燥工程が施され
ているものの、この加熱・乾燥によっては水分及び揮発
成分を完全に除去することができず、残った水分及び揮
発成分、更には、ＩＣチップ等に付着している水分が、
半導体装置をプリント基板等に対して半田付けにて実装
するときにおいて、半田付けのための熱で蒸発すること
になるから、パッケージ体の内部が高い圧力になり、こ
の圧力のために、前記パッケージ体に及び／又はこのパ
ッケージ体とチップ型基板との接着部に亀裂が発生する
と言う問題があった。2. Description of the Related Art Conventionally, in this type of area array package (CSP) type semiconductor device, an IC chip is fixed on the upper surface of a chip type substrate by using a paste. Although the paste used for the fixing is subjected to a drying step by heating until the package is formed on the upper surface of the chip-type substrate, moisture and volatile components are completely removed by the heating and drying. The remaining water and volatile components that cannot be removed, and furthermore, the water adhering to the IC chip, etc.
When a semiconductor device is mounted on a printed circuit board or the like by soldering, since the heat for soldering evaporates, the inside of the package body is at a high pressure, and due to this pressure, the package There is a problem that cracks occur in the body and / or in the bonding portion between the package body and the chip-type substrate.

【０００３】本発明は、この問題の発生を確実に抑制で
きる構造を提供することを技術的課題とするものであ
る。An object of the present invention is to provide a structure capable of reliably suppressing the occurrence of this problem.

【０００４】[0004]

【課題を解決するための手段】この技術的課題を達成す
るため本発明は、「ＩＣチップを、下面に多数個の外部
接続用端子電極をマトリックス状に設けたチップ型基板
の上面に搭載し、このＩＣチップにおける各電極パッド
と、前記パッケージ基板の上面に設けた各ボンディング
パッドとの間を金属線にワイヤボンディングし、且つ、
前記チップ型基板の上面に、ＩＣチップの部分を密封す
る合成樹脂製のパッケージ体を成形して成る半導体装置
において、前記チップ型基板の上面に、当該上面に対す
る前記パッケージ体の接着性を低下するか、又は当該上
面に対して前記パッケージ体が接着しないようにする細
幅帯状の非接着部を、その一端が前記ＩＣチップの外周
部に、他端が前記パッケージ体の外周面に各々のぞむよ
うに設ける。」と言う構成にした。In order to achieve this technical object, the present invention provides a method for mounting an IC chip on an upper surface of a chip type substrate having a plurality of external connection terminal electrodes provided in a matrix on the lower surface. Wire-bonding a metal wire between each electrode pad of the IC chip and each bonding pad provided on the upper surface of the package substrate; and
In a semiconductor device in which a package made of a synthetic resin for sealing an IC chip portion is formed on the upper surface of the chip-type substrate, the adhesiveness of the package to the upper surface of the chip-type substrate is reduced. Alternatively, a narrow band-shaped non-adhesive portion for preventing the package body from adhering to the upper surface, with one end facing the outer peripheral surface of the IC chip and the other end facing the outer peripheral surface of the package body, respectively. To be provided. ".

【０００５】[0005]

【発明の作用・効果】このように構成することにより、
ＩＣチップの部分を、パッケージ体にて確実に密封する
ことができる一方、ＩＣチップをチップ型基板に対して
固着するためのペーストに残存する水分及び揮発成分が
蒸発することにより、前記パッケージ体の内部の圧力が
高くなると、この蒸気は、細幅帯状の非接着パターンを
伝ってパッケージ体の内部から逐次外に逃げることにな
るから、前記パッケージ体の内部が高い圧力になること
を回避できるのである。Operation and effect of the present invention
While the IC chip portion can be securely sealed with the package, the moisture and volatile components remaining in the paste for fixing the IC chip to the chip-type substrate evaporate, so that the package is sealed. When the internal pressure is increased, the vapor will escape from the inside of the package sequentially along the narrow band-shaped non-adhesive pattern, so that the inside of the package can be prevented from becoming a high pressure. is there.

【０００６】従って、本発明によると、プリント基板等
に対して半田付けにて実装するときおいて、パッケージ
体、又はパッケージ体とチップ型基板との接着部に亀裂
が発生することを確実に低減できる効果を有する。特
に、「請求項２」に記載したように、前記非接着パター
ンを、前記チップ型基板の上面における金属箔層にて形
成することにより、前記チップ型基板の上面に各ボンデ
ィングパッドと各外部接続用端子電極の相互間の各々を
電気的に接続するための金属箔層による配線パターンを
形成するときにおいて、同時に形成することができるか
ら、この非接着パターンを設けることのためのコストア
ップを回避できる利点がある。Therefore, according to the present invention, when a package is mounted on a printed circuit board or the like by soldering, the occurrence of cracks in the package or the bonding portion between the package and the chip-type substrate is reliably reduced. Has an effect that can be. In particular, as described in claim 2, by forming the non-adhesive pattern with a metal foil layer on the upper surface of the chip-type substrate, each bonding pad and each external connection are formed on the upper surface of the chip-type substrate. When forming a wiring pattern using a metal foil layer for electrically connecting the respective terminal electrodes to each other, the wiring patterns can be formed at the same time, thereby avoiding an increase in cost for providing this non-adhesive pattern. There are advantages that can be done.

【０００７】[0007]

【発明の実施の形態】以下、本発明の実施の形態を、図
１〜図７の図面について説明する。この図において符号
１は、ＩＣチップを示し、このＩＣチップ１の上面に
は、その中央の部分に能動回路又は従動回路等のような
各種の回路素子が設けられ、また、その周囲の部分に前
記各種の回路素子に対する接続用電極パッド２の多数個
が、四つの各辺に沿って適宜ピッチの間隔で設けられて
いる。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to FIGS. In this figure, reference numeral 1 denotes an IC chip, and on the upper surface of the IC chip 1, various circuit elements such as an active circuit or a driven circuit are provided in a central portion thereof, and a peripheral portion thereof is provided in a peripheral portion thereof. A large number of connection electrode pads 2 for the various circuit elements are provided at appropriate intervals along the four sides.

【０００８】符号３は、前記ＩＣチップ１が搭載される
チップ型基板を示し、このチップ型基板３は、ガラスエ
ポシキ樹脂又はポリイミド樹脂等のような合成樹脂製で
あり、その下面には、本発明における外部接続用端子電
極としての半田又は金等のような金属製のバンプ４の多
数個が、縦方向及び横方向の両方について適宜ピッチ間
隔のマトリックス状に並べて設けられている。Reference numeral 3 denotes a chip-type substrate on which the IC chip 1 is mounted. The chip-type substrate 3 is made of a synthetic resin such as glass epoxy resin or polyimide resin. A large number of metal bumps 4 such as solder or gold as external connection terminal electrodes according to the present invention are arranged in a matrix at appropriate pitch intervals in both the vertical and horizontal directions.

【０００９】また、前記チップ型基板３における上面に
は、前記ＩＣチップ１における電極パッドと同数個のボ
ンディングパッド５が、前記ＩＣチップ１における四つ
の各辺に沿って適宜ピッチの間隔で設けられていると共
に、前記ＩＣチップ１を搭載するためのチップ用パッド
８が形成されている。更に、このチップ型基板３の下面
には、このチップ型基板３を貫通するスルーホール６ａ
を介して、前記各ボンディングパッド５の各々と、その
下面における各外部接続用端子電極としての各バンプ４
の各々との相互間を別々に電気的に接続するための配線
パターン６が設けられている。なお、この配線パターン
６は、絶縁被膜１２にて被覆されている。On the upper surface of the chip-type substrate 3, the same number of bonding pads 5 as the electrode pads of the IC chip 1 are provided along the four sides of the IC chip 1 at appropriate intervals. In addition, a chip pad 8 for mounting the IC chip 1 is formed. Further, a through hole 6a penetrating the chip type substrate 3 is provided on the lower surface of the chip type substrate 3.
Through each of the bonding pads 5 and the bumps 4 as external connection terminal electrodes on the lower surface thereof.
And a wiring pattern 6 for electrically connecting each of them separately. The wiring pattern 6 is covered with an insulating film 12.

【００１０】このチップ型基板３における各ボンディン
グパッド５及びチップ用パッド８は、チップ型基板３の
上面に形成した銅等の金属箔層にボンディングパッド５
及びチップ用パッド８のパターンを焼き付けたのち不要
な箇所をエッチングにて除去すると言うホォトリソ法又
はホォトエッチング法にて形成される。この各ボンディ
ングパッド５及びチップ用パッド８を、前記したよう
に、ホォトリソ法又はホォトエッチング法にて形成する
ときは、これと同時に、銅等の金属箔製の非接着パター
ン７を、細幅帯状にし、その一端が前記チップ用パッド
８から一体的に連接し、他端が前記チップ型基板３の外
周面にのぞむようにして形成する。The bonding pads 5 and the chip pads 8 on the chip type substrate 3 are formed on a metal foil layer of copper or the like formed on the upper surface of the chip type substrate 3.
After the pattern of the chip pad 8 is printed, an unnecessary portion is removed by etching, and is formed by a photolithography method or a photoetching method. As described above, when the bonding pads 5 and the chip pads 8 are formed by the photolithography method or the photo etching method, at the same time, the non-adhesion pattern 7 made of metal foil such as copper is One end thereof is integrally connected to the chip pad 8, and the other end is formed so as to be viewed on the outer peripheral surface of the chip type substrate 3.

【００１１】なお、前記各ボンディングパッド５の表面
には、これに対して後述する金属線の接合性を高めるこ
とのために、ニッケルメッキ層を下地として金又は銀の
メッキ層が形成されており、このニッケルメッキ層を下
地として金又は銀のメッキ層は、前記チップ用パッド８
及び非接着パターン７の表面にも、同時に形成されてい
る。A gold or silver plating layer is formed on the surface of each of the bonding pads 5 with a nickel plating layer as a base, in order to enhance the bonding property of a metal wire to be described later. With the nickel plating layer as a base, the gold or silver plating layer is
And also on the surface of the non-bonding pattern 7.

【００１２】そして、前記ＩＣチップ１を、前記チップ
型基板３の上面に、その間にペースト９を塗布して搭載
したのち、このペースト９を乾燥・硬化することによ
り、前記ＩＣチップ１をチップ型基板３に対して固着す
る。次いで、このＩＣチップ１の上面における各電極パ
ッド２と、チップ型基板３の上面における各ボンディン
グパッド５との相互間の各々を、細い金属線１０による
ワイヤボンディングにて電気的に接続したのち、前記チ
ップ型基板３の上面に、エポシキ樹脂等の熱硬化性合成
樹脂製のパッケージ体１１を、前記ＩＣチップ１及び各
金属線１０の部分の全体を密封するように成形すること
により、半導体装置１３の完成品にするのである。Then, after the IC chip 1 is mounted on the upper surface of the chip type substrate 3 by applying a paste 9 therebetween, the paste 9 is dried and cured, so that the IC chip 1 is formed into a chip type. It is fixed to the substrate 3. Next, the respective electrode pads 2 on the upper surface of the IC chip 1 and the respective bonding pads 5 on the upper surface of the chip type substrate 3 are electrically connected to each other by wire bonding with a thin metal wire 10. A semiconductor device is formed on the upper surface of the chip-type substrate 3 by molding a package 11 made of a thermosetting synthetic resin such as epoxy resin so as to seal the entirety of the IC chip 1 and each of the metal wires 10. 13 finished products.

【００１３】前記パッケージ体１１の成形に際して、こ
の合成樹脂製のパッケージ体１１は、同じく合成樹脂製
のチップ型基板３に対しては充分に接着するが、銅等の
金属箔製の非接着パターン７に対する接着力は、前記チ
ップ型基板３に対する接着力より低くなる。従って、前
記半導体装置１３を、プリント基板等に対して半田付け
にて実装するときにおいて、パッケージ体１１内部のペ
ースト９に残存する水分及び揮発成分、更には、ＩＣチ
ップ１等に付着する水分が蒸発することにより、前記パ
ッケージ体１１の内部の圧力が高くなった場合、この蒸
気は、細幅帯状の非接着パターン７を伝ってパッケージ
体１１の内部から逐次外に逃げることになり、前記パッ
ケージ体１１の内部が高い圧力になることを回避できる
から、パッケージ体１１、又はパッケージ体１１とチッ
プ型基板３との接着部に亀裂が発生することを確実に低
減できるのである。At the time of molding the package 11, the package 11 made of synthetic resin is sufficiently adhered to the chip-type substrate 3 also made of synthetic resin. 7 is lower than the adhesive strength to the chip-type substrate 3. Therefore, when the semiconductor device 13 is mounted on a printed circuit board or the like by soldering, moisture and volatile components remaining in the paste 9 inside the package body 11 and further, moisture adhering to the IC chip 1 and the like are reduced. When the pressure inside the package body 11 increases due to evaporation, the vapor escapes from the inside of the package body 11 successively through the narrow band-shaped non-adhesive pattern 7 to the outside. Since it is possible to avoid a high pressure inside the body 11, it is possible to surely reduce the occurrence of cracks in the package body 11 or the bonding portion between the package body 11 and the chip type substrate 3.

【００１４】なお、前記金属箔層による非接着パターン
７の表面には、前記各ボンディングパッド５の表面と同
様に、ニッケルメッキ層を下地として金又は銀のメッキ
層を形成することにより、当該非接着パターン７に対す
るパッケージ体１１の接着力を更に低下するか、この非
接着パターン７に対してパッケージ体１１を接着しない
ようにすることができる。The surface of the non-adhesive pattern 7 made of the metal foil layer is formed with a gold or silver plating layer with a nickel plating layer as a base, similarly to the surface of each of the bonding pads 5, so that the non-bonding pattern 7 is formed. The adhesive strength of the package 11 to the adhesive pattern 7 can be further reduced, or the package 11 can not be bonded to the non-adhesive pattern 7.

【００１５】また、前記非接着パターン７は、これを金
属箔層にて形成することに代えて、前記パッケージ体１
１の合成樹脂に対する接着力が低いか、パッケージ体１
１の合成樹脂に対して接着しない性質を有する合成樹脂
又はワックス等を、チップ型基板３の上面に細幅帯状に
形成することによって構成しても良いのである。Further, the non-adhesive pattern 7 may be formed of a metal foil layer instead of the package body 1.
1 has a low adhesive strength to the synthetic resin or the package 1
Alternatively, a synthetic resin or wax having a property of not adhering to the first synthetic resin may be formed in a narrow band shape on the upper surface of the chip type substrate 3.

【図面の簡単な説明】[Brief description of the drawings]

【図１】本発明の実施の形態を示す分解斜視図である。FIG. 1 is an exploded perspective view showing an embodiment of the present invention.

【図２】図１の拡大縦断正面図である。FIG. 2 is an enlarged vertical sectional front view of FIG.

【図３】図２のIII −III 視平面図である。FIG. 3 is a plan view taken along line III-III of FIG. 2;

【図４】ＩＣチップをチップ型基板に搭載した状態を示
す拡大縦断正面図である。FIG. 4 is an enlarged vertical sectional front view showing a state where an IC chip is mounted on a chip-type substrate.

【図５】本発明の実施の形態を示す拡大縦断正面図であ
る。FIG. 5 is an enlarged vertical sectional front view showing the embodiment of the present invention.

【図６】図５のVI−VI視断面図である。6 is a sectional view taken along line VI-VI of FIG.

【図７】図５のVII −VII 視断面図である。FIG. 7 is a sectional view taken along the line VII-VII of FIG. 5;

【符号の説明】[Explanation of symbols]

１ ＩＣチップ ２ 電極パッド ３ チップ型基板 ４ 外部接続用端子電極としてのバ
ンプ ５ ボンディングパッド ６ 配線パターン ７ 非接着パターン ８ 絶縁被膜 ９ ペースト １０ 金属線 １１ パッケージ体 １２ 半導体装置DESCRIPTION OF SYMBOLS 1 IC chip 2 Electrode pad 3 Chip-type board 4 Bump as a terminal electrode for external connection 5 Bonding pad 6 Wiring pattern 7 Non-adhesive pattern 8 Insulating coating 9 Paste 10 Metal wire 11 Package body 12 Semiconductor device

Claims (2)

【特許請求の範囲】[Claims] 【請求項１】ＩＣチップを、下面に多数個の外部接続用
端子電極をマトリックス状に設けたチップ型基板の上面
に搭載し、このＩＣチップにおける各電極パッドと、前
記パッケージ基板の上面に設けた各ボンディングパッド
との間を金属線にワイヤボンディングし、且つ、前記チ
ップ型基板の上面に、ＩＣチップの部分を密封する合成
樹脂製のパッケージ体を成形して成る半導体装置におい
て、 前記チップ型基板の上面に、当該上面に対する前記パッ
ケージ体の接着性を低下するか、又は当該上面に対して
前記パッケージ体が接着しないようにした細幅帯状の非
接着パターンを、その一端が前記ＩＣチップの外周部
に、他端が前記パッケージ体の外周面に各々のぞむよう
に設けたことを特徴とするエリアアレイパッケージ型半
導体装置の構造。An IC chip is mounted on an upper surface of a chip type substrate having a plurality of external connection terminal electrodes provided in a matrix on a lower surface, and each electrode pad of the IC chip is provided on an upper surface of the package substrate. A semiconductor device formed by wire bonding between each of the bonding pads and a metal wire, and forming a synthetic resin package for sealing an IC chip portion on an upper surface of the chip-type substrate. On the upper surface of the substrate, a narrow band-shaped non-adhesion pattern that lowers the adhesiveness of the package to the upper surface or prevents the package from adhering to the upper surface, one end of which is the IC chip. The structure of an area array package type semiconductor device, characterized in that the other end is provided on the outer peripheral portion so as to look at the outer peripheral surface of the package body. . 【請求項２】前記「請求項１」において、前記細幅帯状
の非接着パターンを、前記チップ型基板の上面における
金属箔層にて形成したことをことを特徴とするエリアア
レイパッケージ型半導体装置の構造。2. The area array package type semiconductor device according to claim 1, wherein said narrow band-shaped non-adhesive pattern is formed by a metal foil layer on an upper surface of said chip type substrate. Structure.
JP09357497A 1997-04-11 1997-04-11 Structure of area array package type semiconductor device Expired - Lifetime JP3707639B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP09357497A JP3707639B2 (en) 1997-04-11 1997-04-11 Structure of area array package type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP09357497A JP3707639B2 (en) 1997-04-11 1997-04-11 Structure of area array package type semiconductor device

Publications (2)

Publication Number Publication Date
JPH10284514A true JPH10284514A (en) 1998-10-23
JP3707639B2 JP3707639B2 (en) 2005-10-19

Family

ID=14086042

Family Applications (1)

Application Number Title Priority Date Filing Date
JP09357497A Expired - Lifetime JP3707639B2 (en) 1997-04-11 1997-04-11 Structure of area array package type semiconductor device

Country Status (1)

Country Link
JP (1) JP3707639B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046034A (en) * 2001-07-31 2003-02-14 Nec Kagobutsu Device Kk Resin-sealed semiconductor device
JP2010067850A (en) * 2008-09-11 2010-03-25 Sanyo Electric Co Ltd Circuit device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003046034A (en) * 2001-07-31 2003-02-14 Nec Kagobutsu Device Kk Resin-sealed semiconductor device
JP2010067850A (en) * 2008-09-11 2010-03-25 Sanyo Electric Co Ltd Circuit device

Also Published As

Publication number Publication date
JP3707639B2 (en) 2005-10-19

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