JPH10261296A - Non-volatile semiconductor memory and data read-out method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To increase a read-out speed of a NAND type flash memory. SOLUTION: A bit line BLai is made floating after it is precharged to a ground potential or an intermediate potential. Also, an output of a latch circuit LATCH is made 'H'. 0V is applied to a selected word line, a power source potential VCC is applied to the other word lines. As the bit line BLai to which a selected memory cell having a threshold value being less than 0V is connected is connected to ground, it is made 0V. In a bit line BLai to which a selected memory cell having a threshold value exceeding 0V is connected, a potential of the bit line BLai is raised toward a power source potential VCC by capacity coupling of a word line and a bit line. When a potential of a bit line exceeds a threshold value of a transistor M3, an output of the latch circuit LATCH is reversed to 'L'.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called NAND
The present invention relates to a nonvolatile semiconductor memory device such as a flash memory.

[0002]

2. Description of the Related Art FIG. 5 shows an example of a block configuration of a conventional nonvolatile semiconductor memory device. FIG. 6 shows a circuit configuration of a main part of the nonvolatile semiconductor memory device of FIG. The memory cell array has a plurality of blocks, and each block has a plurality of pages. One page is composed of, for example, 512 bytes (4096 bits), and one block is composed of, for example, 4 kilobytes. In this example, eight Ns connected in series
Since an AND cell is used, one block is composed of eight pages.

[0003] Erasing is performed in block units or all bits collectively, and writing and reading are performed in page units. Table 1 shows an example of the potentials of the control gates CG1 to CG8, the select gates SG1 and SG2, the bit line BLa and the source line VS in each operation mode.

[0004]

[Table 1]

In Table 1, it is assumed that the block BLK1 is selected and the control gate CG4 in the block BLK1 is selected in writing or reading.

FIG. 7 shows a threshold distribution of a memory cell in a write state and an erase state. Erasing is to set the threshold value of the memory cell to a value less than 0 V (the state of data "1"). Writing means that the threshold value of the memory cell exceeds 0 V and the power supply potential VCC (for example, 5
V) (a state of data "0").

Writing is performed on a page basis after erasing data on a block basis or on all bits at once. The reason why the threshold value of the memory cell in the written state is set to be lower than the power supply potential VCC is that the power supply potential VCC is applied to the unselected control gates CG1 to CG3 and CG5 to CG8 in the selected block BLK1 at the time of reading. This is for keeping the selected memory cell conductive.

[0008]

The read operation of the semiconductor memory device as described above will be examined. At the time of reading, as shown in Table 1, 0 V is applied to the selected control gate CG4 in the selected block BLK1, and the unselected control gates CG1 to CG5 in the selected block BLK1 are applied. The power supply potential VCC is applied to .about.8.

The bit line BLai (i is 0 to 40)
95) is a floating state after being precharged to the power supply potential VCC by the precharge circuit (N-channel MOS transistor) M2. When the power supply voltage VCC is applied to the select gates SG1 and SG2 in the selected block BLK1, the bit line BLa is set according to the threshold value of the selected memory cell sharing the control gate CG4.
The potential of i is determined.

For example, if the data of the selected memory cell 0 is "0", no cell current flows through the selected memory cell 0, and the potential of the bit line BLa0 becomes the precharge potential VC.
C holds. If the data of the selected memory cell 1 is "1", a cell current flows through the selected memory cell 1, and
The potential of the bit line BLa1 decreases toward a source potential (for example, a ground potential) VS.

The data of the selected memory cell is stored in the bit line BL.
a0 to BLa4095 are simultaneously read and then latched by the latch circuit LATCH, and the L level is quickly set in the page mode.
Read out of SI.

FIG. 8 shows the relationship between the precharge signal φp, the potentials of the select gates SG1 and SG2 of the selected block, and the potential of the bit line BLai. If the data of the selected memory cell is "0", no cell current flows through the selected memory cell as described above, so that the potential of the bit line BLai is set to the precharge potential VCC as shown in FIG. Will be retained.

If the data of the selected memory cell is "1", the cell current flows through the selected memory cell as described above, so that the potential of the bit line BLai becomes the source potential as shown in FIG. (For example, the ground potential) decreases toward VS.

However, for example, the selected memory cell 0 shown in FIG.
Is "0", the potential of the bit line BLa0 must maintain the precharge potential VCC, but if the data of the selected memory cell 1 in FIG. 6 is "1". , The potential of bit line BLa1 becomes VS (ground potential), and the potential of bit line BLa0 becomes lower than precharge potential VCC as shown by c due to capacitive coupling between two bit lines BLa0 and BLa1. is there.

In such a state, the sense amplifier 1
2 is set to the intermediate potential Vth1 between the precharge potential VCC and the source potential (ground potential) VS, a sufficient margin between the precharge potential and the threshold is not secured, and erroneous data is obtained. May be read out.

Therefore, the threshold value of the sense amplifier 12 is set to an intermediate potential Vth2 between the high potential VCC-α and the source potential (ground potential) VS in consideration of capacitive coupling between bit lines.

However, in this case, since the threshold value of the sense amplifier is low, when the data of the selected memory cell is "1", the bit line BLai is discharged and the bit line BLai is discharged.
The time required for the potential of ai to fall below the threshold value of the sense amplifier 12 increases. Therefore, there is a drawback that the read time becomes longer. In recent years, the space between bit lines has been reduced due to a demand for a larger memory capacity, and the capacitive coupling between the bit lines has been increasing. . Therefore, an early solution of the above-mentioned problem is desired.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks. An object of the present invention is to increase the memory capacity and to increase the potential (particularly, high potential) of a bit line by capacitive coupling between the bit lines.
Is to be able to read data in a short time without erroneous reading even when the data fluctuates.

[0019]

In order to achieve the above object, a nonvolatile semiconductor memory device of the present invention has a plurality of memory cells connected in series, and one end of the plurality of memory cells connected in series is provided. , The other end of the plurality of memory cells connected in series is connected to a terminal for supplying a low potential via a select gate transistor, and the plurality of memory cells are connected to a bit line via a select gate transistor. On the premise that the threshold value is less than the first potential or exceeds the first potential and is less than the power supply potential, the latch circuit and the output of the latch circuit are set to a high potential before reading, and the bit line Means for setting the potential of the selected word line to the low potential or an intermediate potential exceeding the low potential, and setting the potential of the selected word line to the first potential and setting the potential of the non-selected word line at the time of reading. A second means for setting a potential to the power supply potential; and a threshold value exceeding the low potential and the intermediate potential and less than the power supply potential, and when the potential of the bit line exceeds the threshold value, Third means for inverting the output to the low potential.

A nonvolatile semiconductor memory device of the present invention has a control gate, a memory cell for storing information, a bit line electrically connected to the memory cell, and a control gate. A word line electrically connected to the memory cell and data read from the memory cell via the bit line or data written to the memory cell via the bit line. First means for setting the output of the latch circuit to a high potential at the time of precharge, and setting the potential of the bit line to a low potential or an intermediate potential exceeding the low potential, and reading. A second means for setting the potential of the selected word line to the read potential and setting the potential of the non-selected word line to the power supply potential, and sensing a change in the potential of the bit line at the time of reading; The output of the latch circuit is Third to invert serial to the low potential
Means.

The memory cell array of the nonvolatile semiconductor memory device is composed of a plurality of blocks,
The select gate transistor of the selected block including the selected word line is set to the on state, and the select gate transistor of the unselected block not including the selected word line is set to the off state.

The first potential and the low potential are ground potentials, and the high potential is equal to the power supply potential. The first means includes a MOS transistor having a drain connected to an input terminal of the latch circuit and turned on before the reading.

The third means is connected between the bit line and an input terminal of the latch circuit, and has a MOS transistor which is turned on before the read operation and is turned off during the read operation, and a drain connected to the output terminal of the latch circuit. And a MOS transistor connected to the end and having a gate connected to the bit line.

According to a data reading method for a nonvolatile semiconductor memory device of the present invention, a memory cell having a threshold value lower than a first potential;
It is premised that there is a memory cell whose threshold value is higher than the first potential and lower than the power supply potential. Before reading, the potential of the bit line is set to a low potential or an intermediate potential exceeding the low potential, Applying the first potential to a word line; applying the power supply potential to a non-selected word line;
When the selected memory cell connected to the
When the potential of the bit line is set to the low potential and a selected memory cell connected to the word line is in an off state, the bit line is capacitively coupled to the unselected word line and the bit line. Is raised toward the power supply potential.

The select gate transistor of the selected block including the selected word line is set to the ON state, and the select gate transistor of the unselected block not including the selected word line is set to the OFF state. ing. The potential of the bit line is recognized by means having a threshold value that exceeds the low potential and the intermediate potential and is less than the power supply potential.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a nonvolatile semiconductor memory device according to the present invention will be described in detail with reference to the drawings.
FIG. 1 shows a configuration of a main part of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

The memory cell array has a plurality of blocks, and each block has a plurality of pages. As in the conventional case, for example, one page is composed of 512 bytes (4096 bits), and one block is composed of 4 kilobytes. In this embodiment, since eight NAND cells connected in series are used, one block is composed of eight pages.

Erasure is performed in block units or all bits at a time, and writing and reading are performed in page units. Control gate CG in each operation mode
1 to 8, select gates SG1 and SG2, bit line BL
a and the potential of the source line VS are as shown in Table 1 above.

Each bit line BLai (i = 0 to 409)
5) includes a readout circuit 11 constituting a main part of the present invention.
Is connected. The read circuit 11 has an N-channel MOS transistor M1 having one of its source and drain connected to the bit line BLai, and a signal φa applied to its gate.
And a latch circuit LATCH connected to the other of the source and drain of the MOS transistor M1.

The latch circuit LATCH has two invertors.
The output of one inverter is the input of the other inverter. This latch circuit LATC
H is used for both reading and writing.

Further, the read circuit 11 has an N-channel MOS transistor M2 connected to the input terminal a of the latch circuit LATCH, and an N-channel MOS transistor M3 connected to the output terminal b of the latch circuit LATCH. .

The MOS transistor M2 has a latch circuit L
A low potential (eg, ground potential) V is applied to the input terminal a of the ATCH.
S is supplied, the input of the latch circuit is set to “L”, and the output is set to “H”.
Set to. The MOS transistor M3 is connected to the latch circuit L
A low potential (for example, ground potential) V is applied to the output terminal b of the ATCH.
S is supplied, the input of the latch circuit is set to “H”, and the output
Set to.

The signal φd is applied to the gate of the MOS transistor M2, and the gate of the MOS transistor M3 is connected to the bit line BLai. The MOS transistor M2 is for setting the bit line BLai to the low potential VS in advance at the time of reading.

Therefore, for example, the control gates CG1 to CG8 of all the blocks and the select gate CG
1, a power supply potential VCC is applied to CG2 to turn on all memory cells and select gate transistors, and to set the bit line BLai to a low potential VS, a MOS transistor is used.
The transistor M2 can be omitted.

Next, the read operation of the above-described nonvolatile semiconductor memory device will be described in detail. First, all the bit lines BLai (i = 0 to 4095) are set to a low potential (for example, ground potential) VS by using one of the following two methods, and the input terminal of the latch circuit LATCH is set. a is set to “L” and the output terminal b is set to “H”.

I. The signal φa is set to “H” (power supply potential VC).
C) ”to turn on the MOS transistor M1, and set the signal φd to“ H ”to turn on the MOS transistor M2. At this time, the low potential VS becomes M
Via the OS transistors M1 and M2, the bit line BL
ai, all the bit lines BLai are set to the low potential VS.

Ii. Control of all blocks
The power supply potential VCC is applied to the gates CG1 to CG8 and the select gates CG1 and CG2 to turn on all the memory cells and the select gate transistors. At this time, since the low potential VS is applied to the bit line BLai via the memory cell and the select gate transistor, all the bit lines BLai are set to the low potential VS. Further, since signal φa is set to “H”, MOS transistor M1 is on.

The above ii. When using the method of
The OS transistor M2 can be omitted. Thereafter, signal φa is set to “L (ground potential)”, and MOS transistor M1 is turned off. As a result, all the bit lines BLai enter the floating state.

For the unselected block BLK0, the unselected word lines (control gates), that is, all word lines are raised from 0V to the power supply potential VCC, and the select gate CG1 is selected. , CG2 are set to 0V.

For the selected block BLK1, unselected word lines, that is, control gates CG1 to CG3 and CG
5-8 and the select gates CG1 and CG2 are raised from 0V to the power supply potential VCC, and the select word line, that is, the control gate CG4 is set to 0V.

When the data of the selected memory cell connected to the selected word line is "1", that is, when the threshold value of the selected memory cell is less than 0 V, the selected memory cell is turned on. Therefore, the potential of the bit line BLai to which the selected memory cell is connected remains at 0V.

On the other hand, when the data of the selected memory cell connected to the selected word line is "0", that is, when the threshold value of the selected memory cell exceeds 0 V, the selected memory cell is turned off. Therefore, the potential of the bit line BLai to which the selected memory cell is connected rises toward the power supply potential VCC due to the capacitive coupling between the word line and the bit line.

For example, as shown in FIGS. 1 and 2, when the data of the selected memory cell 0 is "1", that is, when the threshold value of the selected memory cell 0 is less than 0 V, the selected memory cell 0 Is turned on, the potential of the bit line BLa0 remains at 0V.

On the other hand, the data of the selected memory cell 1 is "0".
In other words, when the threshold value of the selected memory cell 1 exceeds 0 V, the selected memory cell 1 is turned off.
The potential of the bit line BLa1 rises toward the power supply potential VCC due to the capacitive coupling between the word line (excluding the selected word line) and the bit line BLa1.

When the potential of the bit line BLai remains at 0 V, the output of the latch circuit LATCH remains at "H", but the potential of the bit line BLai remains at MO.
When the threshold value of the S transistor M3 is exceeded, the latch circuit LA
The output of TCH is inverted to "L".

As described above, according to the state of the memory cell,
Since the output of the latch circuit LATCH is set to a binary value of "L" or "H", data of the memory cell can be read.

According to the nonvolatile semiconductor memory device having the above structure, the bit line BLai is not precharged to the power supply potential VCC, but is row precharged to the low potential (ground potential) VS, and the state of the selected memory cell is changed. Accordingly, bit line B
Lai is kept at 0 V or the power supply potential VC
C.

The rise in the potential of the bit line BLai is
All word lines except the selected word line and the bit line BLai
This is done by capacitive coupling with In this case, the threshold is 0V
Since the bit lines to which less than the selected memory cells are connected are always connected to the ground, for example, even if the bit line adjacent thereto rises to the power supply potential VCC, the capacitance between the bit lines is reduced. The coupling does not greatly change (increase) the potential of the bit line.

In a bit line to which a selected memory cell having a threshold value exceeding 0 V is connected, the number of word lines (in unselected blocks) to which the power supply potential VCC is applied is controlled so that the potential of the bit line is reduced. The climb speed can be adjusted.

The number of word lines (in unselected blocks) to which the power supply potential VCC is applied is such that the potential of the bit line connected to the ground greatly increases due to the capacitive coupling between the word line and the bit line. It is also necessary to set it to such an extent that it will not end up.

Further, in the nonvolatile semiconductor memory device having the above configuration, the influence of the capacitive coupling between the bit lines at the time of reading can be eliminated without providing a current source for the bit line BLai.

Therefore, in the present invention, it is not necessary to consider the problem of floating of the source potential VS which occurs in the conventional method of continuously flowing the current to the bit lines and eliminating the influence of the capacitive coupling between the bit lines at the time of reading. Good. That is, in the present invention, since the source potential VS does not float, a sufficient read margin can be secured.

Further, according to the nonvolatile semiconductor memory device having the above configuration, the control signal for determining the read timing and the MOS transistor are not required. That is, in the conventional case, for example, as shown in FIG.
Is required, but in the present invention, there is no transistor corresponding to the MOS transistor M4 in FIG.

That is, 1 for one read circuit 11
Since the number of MOS transistors can be omitted, in this embodiment, a total of 4096 MOS transistors can be omitted, so that the readout circuit can be reduced and the chip area can be reduced. This effect is due to MOS
The larger the size of the transistor M4, the more noticeable.

In the present invention, the power supply potential VCC is also applied to the word lines in the non-selected blocks. In this case, however, the increase in power consumption does not pose a significant problem. In this case, the power consumption is slightly increased in the word line driving circuit, but the word line itself is connected only to the power supply line and a large current does not flow through the word line.

FIG. 3 shows a configuration of a main part of a nonvolatile semiconductor memory device according to a second embodiment of the present invention. In this embodiment, by setting the initial value of the potential of the bit line BLai to a predetermined intermediate potential VI (VS <VI <VCC) instead of the low potential (ground potential) VS, the data This achieves a further increase in the reading speed.

The memory cell array has a plurality of blocks, and each block has a plurality of pages. As in the conventional case, for example, one page is composed of 512 bytes (4096 bits), and one block is composed of 4 kilobytes. In this embodiment, since eight NAND cells connected in series are used, one block is composed of eight pages.

Erasure is performed in block units or all bits at a time, and writing and reading are performed in page units. Control gate CG in each operation mode
1 to 8, select gates SG1 and SG2, bit line BL
a and the potential of the source line VS are as shown in Table 1 above.

Each bit line BLai (i = 0 to 409)
5) includes a readout circuit 11 constituting a main part of the present invention.
Is connected. The read circuit 11 has an N-channel MOS transistor M1 having one of its source and drain connected to the bit line BLai, and a signal φa applied to its gate.
And a latch circuit LATCH connected to the other of the source and drain of the MOS transistor M1.

The latch circuit LATCH has two invertors.
The output of one inverter is the input of the other inverter. This latch circuit LATC
H is used for both reading and writing.

Further, the read circuit 11 has an N-channel MOS transistor M2 connected to the input terminal a of the latch circuit LATCH, and an N-channel MOS transistor M3 connected to the output terminal b of the latch circuit LATCH. .

The MOS transistor M2 includes a latch circuit L
An intermediate potential VI (VS <VI <V) is applied to the input terminal a of the ATCH.
CC). The intermediate potential VI is generated by, for example, an intermediate potential generating circuit as shown in FIG. In FIG. 4, 21 is a constant current source, and 22 is an N-channel MOS transistor.

The intermediate potential VI is, for example, a potential lower than the threshold values of the latch circuit LATCH and the MOS transistor M3, and sets the output of the latch circuit LATCH to "H". The MOS transistor M3 is connected to a latch circuit LATC.
A low potential (for example, ground potential) VS is supplied to the H output terminal b, and the input of the latch circuit is set to “H” and the output is set to “L”.

The signal φd is applied to the gate of the MOS transistor M2, and the gate of the MOS transistor M3 is connected to the bit line BLai. The MOS transistor M2 is for setting the bit line BLai to the intermediate potential VI before reading.

Next, the read operation of the above-described nonvolatile semiconductor memory device will be described in detail. First, the signal φa is set to “H (power supply potential VCC)” to turn on the MOS transistor M1, and the signal φd is set to “H” to turn on the MOS transistor M2. At this time, since the intermediate potential VI is applied to the bit line BLai via the MOS transistors M1 and M2, all the bit lines BLai are set to the intermediate potential VI.

The intermediate potential VI is, for example, a value smaller than the threshold value of the latch circuit LATCH and the threshold value of the MOS transistor M3, and the output terminal b of the latch circuit LATCH.
Is set to “H”.

Thereafter, signal φa is set to “L (ground potential)”, and MOS transistor M1 is turned off. As a result, all the bit lines BLai enter the floating state.

For the unselected block BLK0, the unselected word lines (control gates), that is, all the word lines are raised from 0V to the power supply potential VCC, and the select gate CG1 is selected. , CG2 are set to 0V.

For the selected block BLK1, unselected word lines, that is, control gates CG1 to CG3 and CG
5-8 and the select gates CG1 and CG2 are raised from 0V to the power supply potential VCC, and the select word line, that is, the control gate CG4 is set to 0V.

When the data of the selected memory cell connected to the selected word line is "1", that is, when the threshold value of the selected memory cell is less than 0 V, the selected memory cell is turned on. Therefore, the potential of bit line BLai to which the selected memory cell is connected changes from intermediate potential VI to 0V.

On the other hand, when the data of the selected memory cell connected to the selected word line is "0", that is, when the threshold value of the selected memory cell exceeds 0 V, the selected memory cell is turned off. Therefore, the potential of the bit line BLai to which the selected memory cell is connected rises from the intermediate potential VI toward the power supply potential VCC due to the capacitive coupling between the word line and the bit line.

When the potential of bit line BLai changes to 0 V, the output of latch circuit LATCH remains at "H", but the potential of bit line BLai is changed to power supply potential VC.
When the voltage changes toward C and exceeds the threshold value of the MOS transistor M3, the output of the latch circuit LATCH becomes
Invert to “L”.

As described above, according to the state of the memory cell,
Since the output of the latch circuit LATCH is set to a binary value of "L" or "H", data of the memory cell can be read.

According to the nonvolatile semiconductor memory device having the above configuration, the potential of the bit line to which the selected memory cell having the threshold value of less than 0 V is connected decreases toward 0 V, and the selected memory cell having the threshold value of more than 0 V is selected. The potential of the connected bit line is the power supply potential V due to the capacitive coupling between the word line and the bit line.
Ascend toward CC.

Therefore, the bit line BL at the time of reading is
Since the fluctuation width of the potential ai can be reduced, it is possible to contribute to shortening of the reading time. According to the above configuration, the bit line BLai is precharged to the power supply potential VCC.
Instead, the potential of the bit line BLai is kept at 0 V or the power supply potential V.sub.V, depending on the state of the selected memory cell.
I try to raise it to CC.

The rise in the potential of the bit line BLai is
All word lines except the selected word line and the bit line BLai
This is done by capacitive coupling with In this case, the threshold is 0V
Since the bit lines to which less than the selected memory cells are connected are always connected to the ground, for example, even if the bit line adjacent thereto rises to the power supply potential VCC, the capacitance between the bit lines is reduced. The coupling does not greatly change (increase) the potential of the bit line.

In a bit line to which a selected memory cell having a threshold value exceeding 0 V is connected, the number of word lines (in non-selected blocks) to which the power supply potential VCC is applied is controlled so that the potential of the bit line is reduced. The climb speed can be adjusted.

The number of word lines (in unselected blocks) to which the power supply potential VCC is applied is such that the potential of the bit line connected to the ground greatly increases due to the capacitive coupling between the word line and the bit line. It is also necessary to set it to such an extent that it will not end up.

Further, in the nonvolatile semiconductor memory device having the above configuration, it is possible to eliminate the influence of capacitive coupling between bit lines at the time of reading without providing a current source for the bit lines BLai.

Therefore, in the present invention, it is not necessary to consider the problem of the floating source potential VS which occurs in the conventional method in which the current always flows through the bit lines and the influence of the capacitive coupling between the bit lines during reading is eliminated. Good. That is, in the present invention, since the source potential VS does not float, a sufficient read margin can be secured.

According to the nonvolatile semiconductor memory device having the above configuration, a control signal and a MOS transistor for determining a read timing are not required. That is, in the conventional case, for example, as shown in FIG.
Is required, but in the present invention, there is no transistor corresponding to the MOS transistor M4 in FIG.

That is, for one read circuit 11, 1
Since the number of MOS transistors can be omitted, in this embodiment, a total of 4096 MOS transistors can be omitted, so that the readout circuit can be reduced and the chip area can be reduced. This effect is due to MOS
The larger the size of the transistor M4, the more noticeable.

In the present invention, the power supply potential VCC is also applied to the word lines in the non-selected blocks. In this case, however, the increase in power consumption does not pose a significant problem. In this case, the power consumption is slightly increased in the word line driving circuit, but the word line itself is connected only to the power supply line and a large current does not flow through the word line.

[0084]

As described above, according to the nonvolatile semiconductor memory device of the present invention, the following effects can be obtained.
Instead of precharging the bit line to the power supply potential VCC, precharge it to a low potential (ground potential) or an intermediate potential, and keep the bit line potential at 0 V depending on the state of the selected memory cell. Or the power supply potential VCC. The rise of the potential of the bit line is effected by capacitive coupling between all the word lines except the selected word line and the bit line.

In this case, since the bit line to which the selected memory cell whose threshold value is less than 0 V is connected is always connected to the ground, for example, when the bit line adjacent to the selected memory cell rises to the power supply potential VCC. Even if there is, the potential of the bit line does not greatly fluctuate (rise) due to capacitive coupling between the bit lines.

In a bit line to which a selected memory cell having a threshold value exceeding 0 V is connected, the number of word lines (in non-selected blocks) to which the power supply potential VCC is applied is controlled so that the potential of the bit line is reduced. The climb speed can be adjusted.

The number of word lines (in unselected blocks) to which the power supply potential VCC is applied is such that the potential of the bit line connected to the ground greatly increases due to the capacitive coupling between the word line and the bit line. It is necessary to set it to such an extent that it does not end up.

Further, according to the present invention, it is possible to eliminate the influence of capacitive coupling between bit lines during reading without providing a current source for the bit lines. Therefore, it is not necessary to consider the problem of floating of the source potential VS which occurs in the conventional method in which the current always flows through the bit lines and the influence of the capacitive coupling between the bit lines at the time of reading is eliminated.

Further, according to the present invention, since a control signal and a MOS transistor for determining a read timing are not required, it is possible to contribute to a reduction in a read circuit and a reduction in a chip area. In the present invention, the power supply potential VCC is also applied to the word lines in the non-selected blocks, but the power consumption hardly increases.

[Brief description of the drawings]

FIG. 1 is a diagram showing a main part of a nonvolatile semiconductor memory device according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a potential of a bit line and a select gate and a timing of a signal φd in FIG. 1;

FIG. 3 is a diagram showing a main part of a nonvolatile semiconductor memory device according to a second embodiment of the present invention.

FIG. 4 is a diagram showing a circuit for generating an intermediate potential VI in FIG. 3;

FIG. 5 is a diagram showing a block configuration of a conventional nonvolatile semiconductor memory device.

FIG. 6 is a diagram showing a main part of a conventional nonvolatile semiconductor memory device.

FIG. 7 is a diagram showing threshold distributions of memory cells in a write state and an erase state.

FIG. 8 is a diagram showing the potentials of the bit lines and select gates in FIG. 6 and the timing of the signal φp.

[Explanation of symbols]

11: readout circuit, 21: constant current source, 22, M1 to M4: N-channel MOS transistor, LATCH: latch circuit.

Claims (9)

[Claims] A plurality of memory cells connected in series, one end of each of the plurality of memory cells connected in series being connected to a bit line via a select gate transistor, and a plurality of memory cells connected in series; The other end of the memory cell is connected to a terminal for supplying a low potential via a select gate transistor, and the threshold value of the plurality of memory cells is lower than the first potential or higher than the first potential and lower than the power supply potential. In one non-volatile semiconductor memory device, a latch circuit and, prior to reading, setting an output of the latch circuit to a high potential and setting a bit line potential to the low potential or an intermediate potential exceeding the low potential Means for setting the potential of a selected word line to the first potential at the time of reading and setting the potential of a non-selected word line to the power supply potential; And a third means for inverting the output of the latch circuit to the low potential when the potential of the bit line exceeds the threshold, the threshold being higher than the intermediate potential and lower than the power supply potential. Nonvolatile semiconductor memory device. 2. A memory cell having a control gate for storing information; a bit line electrically connected to the memory cell; and a memory cell electrically connected to the control gate. A latch circuit for temporarily holding data read from the memory cell via the bit line or data to be written to the memory cell via the bit line; First means for setting the output of the latch circuit to a high potential and setting the potential of the bit line to a low potential or an intermediate potential exceeding the low potential at the time of reading; Second means for setting the potential to the read potential and setting the potential of the non-selected word line to the power supply potential; and sensing a change in the potential of the bit line at the time of reading and setting the output of the latch circuit to the low level. For inverting to the potential A nonvolatile semiconductor memory device having three means. 3. The memory cell array of the nonvolatile semiconductor memory device is composed of a plurality of blocks, a select gate transistor of a selected block including the selected word line is set to an ON state, and the selected word is turned on. 3. The nonvolatile semiconductor memory device according to claim 1, wherein a select gate transistor of a non-selected block not including a gate line is set to an off state. 4. The nonvolatile semiconductor memory device according to claim 1, wherein said first potential and said low potential are ground potentials, and said high potential is equal to said power supply potential. 5. The non-volatile memory according to claim 1, wherein said first means comprises a MOS transistor having a drain connected to an input terminal of said latch circuit and turned on before said reading. Semiconductor memory device. 6. The third means is connected between the bit line and an input terminal of the latch circuit, and has a MOS transistor which is turned on before the read operation and turned off when the read operation, and a drain of which is connected to the latch circuit. And a MOS transistor connected to the output terminal of the bit line and having a gate connected to the bit line.
14. The nonvolatile semiconductor memory device according to claim 1. 7. A data reading method for a nonvolatile semiconductor memory device including a memory cell having a threshold value lower than a first potential and a memory cell having a threshold value higher than the first potential and lower than a power supply potential. Setting the potential of the bit line to a low potential or an intermediate potential exceeding the low potential, applying the first potential to a selected word line during reading, and applying the power supply potential to a non-selected word line; When the selected memory cell connected to the word line is in the on state, the potential of the bit line is set to the low potential. When the selected memory cell connected to the word line is in the off state, the potential of the bit line is reduced. A data reading method for a nonvolatile semiconductor memory device, wherein the potential of the bit line is raised toward the power supply potential by capacitive coupling between a non-selected word line and the bit line. 8. A select gate transistor of a selected block including the selected word line is set to an on state,
8. The data reading method for a nonvolatile semiconductor memory device according to claim 7, wherein a select gate transistor of a non-selected block not including said selected word line is set to an off state. 9. The nonvolatile semiconductor memory device according to claim 7, wherein said bit line potential is recognized by means having a threshold value exceeding said low potential and said intermediate potential and less than said power supply potential. Data reading method.