JPH10247902A - Signal correction circuit and signal correction method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the number of connected electronic devices to transmit a signal from being limited by avoiding the effect of deviation in delay times by a buffer. SOLUTION: Rising of a clock signal received by a buffer 1 is received by a D flip-flop 2 and a delay element 3 and an XOR gate 4 are used to recover a corrected clock signal with the same frequency. Furthermore, a latch 5 corrects an input data signal by using the correction clock signal and the signal is used in the device and outputted externally.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal correction circuit and a signal correction method in an electronic device for transmitting signals.

[0002]

2. Description of the Related Art When a plurality of electronic devices are connected and a data signal is to be transmitted through these devices, a data signal has been conventionally transmitted in synchronization with a clock signal. FIG. 6 is a diagram showing a main part of a conventional device for performing such signal transmission. In the figure, reference numeral 1 denotes a buffer on the signal input side, and 6 denotes a buffer on the output side.

In the above configuration, the data signal is passed to the buffer 1 together with the clock signal. The output of the buffer 1 is used inside the apparatus and is output through a buffer 6 at the subsequent stage. In other words, in this device, both the clock signal and the data signal are output as they are via the buffers 1 and 6, and the buffer may have a one-stage configuration.

FIG. 7 is a circuit diagram showing another conventional example. In the figure, reference numeral 7 denotes a shift register or the like provided on a data line between the buffers 1 and 6, and this device receives, converts, and transmits data. In this device, the clock signal is output as it is via the buffers 1 and 6, and the data signal is output after being converted by the shift register 7 in synchronization with the clock signal. In this case, the buffer may have a single-stage configuration as described above.

[0005]

By the way, in the conventional signal circuit as described above, when a signal is to be transmitted at a high speed through, for example, several tens of devices, the rising propagation time in the buffer and the rising propagation time in the buffer are required. Number of falling propagation times ns
There is a possibility that the pulse width of the clock signal changes due to the sum of the shifts of ec and becomes smaller than the pulse width that can be determined by the device. FIG. 8 shows this state, and the pulse width gradually decreases by passing through a large number of buffers (1 to n).

In the case of the circuit shown in FIG. 6, the clock signal and the data signal may be shifted due to the sum of the shifts of several nsec of the signal propagation signal of each buffer, which may hinder the operation of the device. . (In the circuit of FIG. 7, this problem is small because the timing of the data signal output is corrected by the clock signal. However, since the data output change is close to the clock change, there is a risk of malfunction depending on the transmission situation.) Since the higher the number of connected devices, the higher the speed of signal transmission, the more the above problem needs to be solved in order to guarantee product operation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and can correct a deviation of a clock signal or a data signal, and can provide a signal which does not hinder the operation even if a large number of devices are connected. It is an object to provide a correction circuit and a signal correction method.

[0008]

A signal correction circuit and a signal correction method according to the present invention are configured as follows.

(1) A correction circuit for correcting a clock signal, comprising: an extracting means for extracting only a rising edge or a falling edge of a clock signal; and a generating means for generating a correction signal having the same frequency based on the extracted output. And with.

(2) A correction circuit for correcting another signal based on a clock signal, comprising: an extracting means for extracting only the rising edge or the falling edge of the clock signal; and a correction circuit for correcting the same frequency based on the extracted output. Generating means for generating a signal, wherein the other signal is corrected based on the generated correction signal of the clock signal.

(3) A correction method for correcting a clock signal, wherein only a rising edge or a falling edge of a clock signal is extracted, and a correction signal of a clock signal having the same frequency is generated based on the extracted output. .

(4) A correction method for correcting another signal based on a clock signal, wherein only a rising edge or a falling edge of a clock signal is extracted, and a correction signal of a clock signal having the same frequency based on the extracted output. Is generated, and the other signal is corrected based on the correction signal.

[0013]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention, which is an improvement over the conventional one shown in FIG.

In FIG. 1, reference numeral 1 denotes an input-side buffer;
Is a D-flip-flop (extraction means) for taking in only the rising edge of the input clock signal, 3 is a delay element for delaying a fixed signal, and 4 and 4 are the same frequency as the input clock signal based on the output of the flip-flop 2. The output of the delay element 3 and the output of the flip-flop 2 are input to each of the two XOR gates (generation means) for generating the corrected clock signal, and the corrected clock signal (CS) is directly output from one of the XOR gates 4. Output from the other XOR gate 4 and an inverted correction clock signal (CS
Bar) is output. In this circuit example, the CS bar is used as a CS delay signal. Therefore, a signal obtained by delaying the correction clock signal (CS) may be used as the location of the inverted correction clock signal (CS bar).

Reference numeral 5 denotes a latch for correcting a data signal based on the correction clock signal, which is constituted by a D-flip-flop, the output of which is also used inside the device. 6
Is an output buffer.

In the above circuit configuration, the rising edge of the input clock signal is extracted, and a corrected clock signal of the same frequency corrected based on the extracted clock signal is generated. At the same time, the input data signal is latched at the rise of the correction clock signal, and the data signal is corrected.

As described above, the clock signal having the same frequency is re-created on the basis of the rising edge of the input clock signal, and the data signal is corrected based on the signal. For this reason,
The pulse width of the clock signal does not change below a predetermined value, and the difference between the rise delay time and the fall delay time of the buffer can be corrected. In addition, by correcting the change timing of another data signal using the clock signal, it is possible to correct a shift in the delay time of each buffer. Therefore, even if a large number of devices are connected, the operation is not hindered, and the number of connected devices is not limited.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. This embodiment shows a variation of the circuit shown in FIG. 1, in which the clock signal output from the buffer 1 is used as the input clock signal for the latch 5. This is based on the fact that the input clock signal has already been corrected by the device connected in the previous stage and that the first signal has not been deviated, and the input data signal is latched at the rising edge of the input clock signal and corrected. I do.

The output clock signal is output by correcting the input clock signal as described above.
However, the signal is delayed from the data change.

In this embodiment having such a configuration, the timings of the clock signal and the other data signals are corrected in the same manner as in the above-described embodiment. The restrictions of need not be considered.

FIG. 3 is a circuit diagram showing a third embodiment of the present invention. The same reference numerals as in FIG. 1 denote the same components. This embodiment is an improvement over the conventional one shown in FIG. In the figure, reference numeral 7 denotes a shift register interposed in a data line, and the output of the shift register 7 is used inside the apparatus.

In this embodiment, similarly to the embodiment of FIG. 1, a clock signal corrected on the basis of the rising edge of the input clock signal is generated, and the internal data signal is corrected based on the corrected clock signal. That is, both the output clock signal and the output data signal are corrected based on the corrected clock signal, and the same operation and effect as in the above-described embodiment can be obtained.

However, in the present embodiment, the change timing of the output data signal needs to be sufficiently separated from the rise of the output clock signal, and the output data signal is output or delayed at the fall timing of the correction clock signal. If you take such measures, it will be safer. That is, it is safer to delay the data signal, for example, by providing a delay circuit 8 between the shift register 7 and the buffer 6 on the output side and latching it at the falling edge of the clock signal.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention. This embodiment shows a variation of the circuit of FIG. 3, in which a clock signal from the buffer 1 is directly input to the shift register 7 as in the circuit of FIG. That is,
This circuit is also premised on that the input clock signal has already been corrected by the device connected in the preceding stage, as in the circuit of FIG. The output clock signal is output after correcting the input clock signal.

In this embodiment, since the timing of clock output and data becomes more dangerous than the circuit of FIG. 3, the data signal is delayed by providing a delay circuit 8 and latching the falling edge of the clock signal. Is more secure.

FIG. 5 shows the relationship between the input clock signal and the correction clock signal (output clock signal) in each of the above embodiments. In the figure, T indicates a delay time of each correction circuit, and W indicates a pulse width generated by the delay element 3 and the like. The delay element 3 is configured by a buffer element that transmits a signal with a limited fixed delay time.

Here, the signal delay time of the delay element 3 or the like for generating the pulse width is α, where α is a time width that may be shifted by a circuit. ) + Α, and the maximum value is (one cycle of the maximum usable frequency clock) − (minimum pulse width that can be determined by the device) −α.

In each of the above embodiments, the case where both the clock signal and the data signal are corrected on the basis of the rise of the clock signal has been described. However, the same operation and effect can be obtained even on the basis of the fall of the clock signal. . Further, the correction circuit of the embodiment may be provided not for each product but for each of several connected devices.

[0029]

As described above, according to the present invention, the pulse width of the clock signal is re-created, so that the pulse width of the clock signal can be corrected. It will not hinder you.

Further, the timing of the clock signal and the timing of other signals can be corrected, and similarly, the number of connected devices is not limited.

[Brief description of the drawings]

FIG. 1 is a circuit configuration diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit configuration diagram showing a third embodiment of the present invention.

FIG. 4 is a circuit diagram showing a fourth embodiment of the present invention.

FIG. 5 is a waveform chart showing a relationship between an input clock and a correction clock according to the embodiment.

FIG. 6 is a circuit diagram showing a conventional example.

FIG. 7 is a circuit configuration diagram showing another conventional example.

FIG. 8 is an explanatory diagram showing signal waveforms passed through a number of buffers.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer 2 D-flip-flop (extraction means) 3 Delay element 4 XOR gate (generation means) 5 Latch 6 Buffer 7 Shift register 8 Delay circuit

Claims (4)

[Claims] 1. A correction circuit for correcting a clock signal, comprising: extracting means for extracting only the rising edge or falling edge of the clock signal; and generating means for generating a correction signal having the same frequency based on the extracted output. A signal correction circuit comprising: 2. A correction circuit for correcting another signal based on a clock signal, comprising: extraction means for extracting only the rising edge or the falling edge of the clock signal; and a correction signal having the same frequency based on the extracted output. Generating means for generating the clock signal, and correcting the other signal based on the generated correction signal of the clock signal. 3. A correction method for correcting a clock signal, wherein only a rising edge or a falling edge of a clock signal is extracted and a correction signal of a clock signal having the same frequency is generated based on the extracted output. A signal correction method characterized by the above-mentioned. 4. A correction method for correcting another signal based on a clock signal, wherein only a rising edge or a falling edge of a clock signal is extracted, and a correction signal of a clock signal having the same frequency is extracted based on the extracted output. A signal correction method comprising: generating and correcting the other signal based on the correction signal.