JP2008042501A - Electronic circuit equipment - Google Patents

Abstract

The present invention provides an electronic circuit device capable of reducing variations in pulse width and further reducing jitter in transmission of a signal such as NRZ that intentionally changes the pulse width.
Two edge detection circuits (11, 12), two variable delay circuits (13, 14), and an SR latch circuit (15) are provided. 12 outputs are connected, and the outputs of the variable delay circuits 13, 14 are connected to the S input and R input of the SR latch circuit, respectively.
[Selection] Figure 1

Description

  The present invention relates to an electronic circuit device that performs high-speed signal generation or signal waveform shaping.

  In an electronic circuit using a pulse signal, when transmitting the same pulse signal in a plurality of different transmission systems, a variable delay circuit is used to adjust a skew that is a deviation from an expected value of phase or time generated between the signals. May need to be transmitted over the network. This variable delay circuit can be composed of multi-stage inverters and gate elements, but in such a case, the width of the pulse that has passed through the multi-stage circuit is not constant because it spreads or narrows due to variations in each element. There is.

  As a method for solving this problem, a pulse shaping circuit that generates an arbitrary pulse width independent of the pulse width of an input pulse has been proposed (for example, see Patent Document 1). FIG. 10 shows a simplified configuration of the pulse shaping circuit 40. This circuit includes an edge detection circuit 41 that detects a falling edge, a variable delay circuit 42, an OR circuit 43, and an SR (set / reset type, hereinafter) latch circuit 44.

In this pulse shaping circuit 40, the SR latch circuit 44 is set when the output of the edge detection circuit 41 rises to a high level in response to the fall of the input signal, and the output of the edge detection circuit 41 is delayed by the variable delay circuit 42. When the received signal rises to the high level, the SR latch circuit 44 is reset, so that the input signal is shaped into a signal having a predetermined pulse width and output from the SR latch circuit 44.
Japanese Patent No. 3653115

  However, the pulse shaping circuit shown in FIG. 10 can be used when outputting a signal having a fixed pulse width (for example, a repetitive simple signal called a clock signal or an RZ signal). When a signal that is intentionally changed (for example, an NRZ signal) is input to the pulse shaping circuit, there is a problem that the output is different from the intended signal.

  An object of the present invention is to reduce the variation in pulse width even in transmission of a signal (for example, an NRZ signal) that intentionally changes the pulse width, and to thereby reduce jitter (phase noise). Is to provide.

To achieve the above object, an electronic circuit device according to a first aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, and first and second edge detection circuits, The output of the first edge detection circuit is connected to the input of one variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and S of the SR latch circuit The output of the first variable delay circuit is connected to the input, and the output of the second variable input circuit is connected to the R input of the SR latch circuit.
The invention according to claim 2 includes an SR latch circuit, first and second variable delay circuits, and first, second, third and fourth edge detection circuits, wherein the first variable delay circuit includes: The output of the first edge detection circuit is connected to the input, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the output of the first variable delay circuit is connected to the first variable delay circuit. The input of the third edge detection circuit, the output of the second variable delay circuit is connected to the input of the fourth edge detection circuit, and the S input of the SR latch circuit is connected to the S input of the third edge detection circuit. An output is connected, and an output of the fourth edge detection circuit is connected to an R input of the SR latch circuit.
According to a third aspect of the present invention, in the electronic circuit device according to the first or second aspect, one of the first and second variable delay circuits is deleted, and the deleted portion is short-circuited.
According to a fourth aspect of the present invention, in the electronic circuit device according to the first, second, or third aspect, a signal obtained by logically inverting a signal input to the first edge detection circuit is input to the second edge detection circuit. It is characterized by inputting.
According to a fifth aspect of the present invention, in the electronic circuit device according to the second or fourth aspect, the first edge detection circuit and the first variable delay circuit or the second edge detection circuit and the second variable The delay circuit is deleted, and the deleted portion is short-circuited.
According to a sixth aspect of the present invention, in the electronic circuit device according to the first, second, third, fourth or fifth aspect, the first and second edge detection circuit inputs are the first and second edge detection circuit inputs. A signal having a pulse width smaller than the minimum pulse width of the signal to be output is output.
The invention according to claim 7 is the electronic circuit device according to claim 2, 3, 4, 5 or 6, wherein the third and fourth edge detection circuits are replaced with the third and fourth edge detection circuits. A signal having a pulse width smaller than the minimum pulse width of the input signal is output.

  According to the present invention, a pulse shaping circuit for an NRZ signal can be realized, and output jitter of the pulse shaping circuit can be reduced. In addition, the electronic circuit device can be used as a variable delay circuit by changing both delay amounts while maintaining the difference between the delay amounts of the first and second variable delay circuits. Further, when the third and fourth edge detection circuits are used, it is possible to relax the limitation on the minimum value of the pulse width of the output pulse of the pulse shaping circuit.

  Embodiments of the present invention will be described below with reference to the drawings. In addition, the same number is assigned to the common part in all drawings, and duplication description is avoided.

  FIG. 1 is a diagram illustrating a configuration of an electronic circuit device 10A according to a first embodiment of the present invention. The electronic circuit device 10A includes a first edge detection circuit 11, a second edge detection circuit 12, a first variable delay circuit 13, a second variable delay circuit 14, and an SR latch circuit 15. The output 11a of the first edge detection circuit 11 is connected to the input of the first variable delay circuit 13, and the output 12a of the second edge detection circuit 12 is connected to the input of the second variable delay circuit 14. The output 13a of the first variable delay circuit 13 is connected to the S (set, the same hereinafter) input of the SR latch circuit 15, and the second (reset, same hereinafter) input of the SR latch circuit 15 is connected to the second input. The output 14a of the variable delay circuit 14 is connected.

  The first edge detection circuit 11 detects the edge (rising or falling) of the signal input A1, and outputs the timing information of the edge from the output 11a as the output timing of a pulse signal having a predetermined pulse width. . The second edge detection circuit 12 detects the edge (rising or falling) of the signal input A2, and outputs the timing information of the edge from the output 12a as the output timing of a pulse signal having a predetermined pulse width. .

  The first variable delay circuit 13 delays the signal input from the first edge detection circuit 11 by the delay amount set by the delay amount setting input B1, and outputs it from the output 13a. The second variable delay circuit 14 delays the signal input from the second edge detection circuit 12 by the delay amount set by the delay amount setting input B2, and outputs the delayed signal from the output 14a.

  The SR latch circuit 15 outputs a high level from the output Q when a high level signal is input to the S input, and a low level when a high level signal is input to the R input.

  FIG. 2 is a timing chart when the electronic circuit device 10A is used as a pulse shaping circuit for an NRZ signal. Here, a case where the first and second edge detection circuits 11 and 12 detect a rising edge will be described. When used as a pulse shaping circuit for the NRZ signal, a signal obtained by logically inverting the signal of the signal input A1 is input to the signal input A2.

  As shown in FIG. 2, the rising timing and falling timing of the output Q of the SR latch circuit 15 can be freely set by setting the delay amounts of the first and second variable delay circuits 13 and 14. Here, the delay time t2 is set by the first variable delay circuit 13, and the delay time t3 is set by the second variable delay circuit 14, respectively. t1 is the time difference between the signals of the inputs A1 and A2.

  The above function is a configuration in which the arrangement of the first edge detection circuit 11 and the first variable delay circuit 13 is exchanged, and the arrangement of the second edge detection circuit 12 and the second variable delay circuit 14 is exchanged. However, it is feasible, but such a configuration has the following problems.

  In FIG. 3, the inputs of the first edge detection circuit 11 and the second edge detection circuit 12 are connected to the outputs 13a and 14a of the first variable delay circuit 13 and the second variable delay circuit 14, and the first edge is detected. The configuration of an electronic circuit device 10B in which the outputs 11a and 12a of the detection circuit 11 and the second edge detection circuit 12 are connected to the S input and the R input of the SR latch circuit 15 is shown. 2 is a timing chart when used as a pulse shaping circuit.

  When the minimum pulse width of the signal input A1 and the signal input A2 which is the logical inversion signal thereof is sufficiently large, as shown in FIG. 4A, the signals of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 are output. Since signal degradation such as a partial decrease in logical amplitude (or voltage amplitude in a normal electronic circuit device) hardly occurs, the signal input to the SR latch circuit 15 is the same signal as in FIG. For this reason, the rising timing and falling timing of the output Q of the SR latch circuit are the same as those in FIG.

  However, when the minimum pulse width of the signal input A1 and the signal input A2 that is the logical inversion signal thereof is reduced to some extent, as shown in FIG. 4B, the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 are output. A partial decrease in the logical amplitude of the signal occurs. As a result, the rising timing of the signals 11a and 12a of the first and second edge detection circuits 11 and 12 input to the SR latch circuit 15 is shown in FIG. It differs from the case of 2. In FIG. 4B, the waveform in the normal case is indicated by a broken line.

  As a result, the rising timing and falling timing of the output Q of the SR latch circuit 15 are also different from those in FIG. As shown in FIG. 4B, the magnitude of this timing deviation does not become a constant magnitude. Therefore, the pulse width of the output Q of the SR latch circuit 15 does not become as set. Note that a timing shift such as the output Q of the SR latch circuit 15 is generally called jitter (phase noise).

  On the other hand, FIG. 5 shows a timing chart when the electronic circuit device 10A of FIG. 1 is used as a pulse shaping circuit for an NRZ signal and a signal input similar to FIG. 4B is input. The pulse widths of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 do not depend on the pulse widths of the input signals (A1 and A2).

  As shown in FIG. 5, there are cases where the logical amplitude of the signals 13a and 14a of the first and second variable delay circuits 13 and 14 decreases, but the logical amplitude decreases in the same manner for all pulses. As a result, the pulse width of the output Q of the SR latch circuit 15 is almost the same as the set value. That is, the jitter of the output Q of the SR latch circuit 15 is smaller than that in the case of FIG. 4B.

  As described above, according to the electronic circuit device 10A of the first embodiment, it is possible to realize a pulse shaping circuit for an NRZ signal and to reduce output jitter of the pulse shaping circuit. Further, as shown in the timing charts of FIGS. 2 and 5, both while maintaining the difference between the delay amount setting value of the first variable delay circuit 13 and the delay amount setting value of the second variable delay circuit 14. It is possible to use the electronic circuit device 10A of FIG. 1 as a variable delay circuit by changing the set value.

  FIG. 6 is a diagram showing a configuration of an electronic circuit device 10C according to the second embodiment of the present invention. The electronic circuit device 10 </ b> C includes a first edge detection circuit 11, a second edge detection circuit 12, a first variable delay circuit 13, a second variable delay circuit 14, and a third edge detection circuit 16. And the second edge detection circuit 17 and the SR latch circuit 15, the output 11 a of the first edge detection circuit 11 is connected to the input of the first variable delay circuit 13, and the second variable delay The output 12a of the second edge detection circuit 12 is connected to the input of the circuit 14, the input of the third edge detection circuit 16 is connected to the output 13a of the first variable delay circuit 13, and the second The input of the fourth edge detection circuit 17 is connected to the output 14a of the variable delay circuit 14, the output 16a of the third edge detection circuit 16 is connected to the S input of the SR latch circuit 15, and the SR latch circuit 15 R inputs It is characterized by connecting the serial output 17a of the fourth edge detection circuit 17.

  The first and second edge detection circuits 11 and 12 and the SR latch circuit 15 are the same as those in the electronic circuit device 10A of the first embodiment. The third edge detection circuit 16 detects an edge (rising or falling) of the output 13a of the first variable delay circuit 13, and outputs the timing information of the edge as a pulse signal output timing having a predetermined pulse width. Is output from the output 16a. The fourth edge detection circuit 17 detects the edge (rising or falling) of the output 14a of the second variable delay circuit 14, and outputs the timing information of the edge as a pulse signal output timing having a predetermined pulse width. Is output from the output 17a.

  FIG. 7 is a timing chart when the electronic circuit device 10C is used as a pulse shaping circuit for an NRZ signal. Here, a case where the first to fourth edge detection circuits 11, 12, 16, and 17 detect a rising edge will be described. When used as a pulse shaping circuit for the NRZ signal, a signal obtained by logically inverting the signal of the signal input A1 is input to the signal input A2.

  As shown in FIG. 7, the rising timing and falling timing of the output Q of the SR latch circuit 15 can be freely set by setting the delay amounts of the first and second variable delay circuits 13 and 14. In addition, since the first and second edge detection circuits 11 and 12 are connected to the inputs of the first and second variable delay circuits 13 and 14, SR is the same as in the electronic circuit device 10A of FIG. It is possible to reduce the jitter of the output Q of the latch circuit 15.

  Compared with the electronic circuit device 10A of FIG. 1, the electronic circuit device 10C of FIG. 6 has the following advantages because the third and fourth edge detection circuits 16 and 17 are mounted. Usually, the SR latch circuit has a problem that it cannot operate normally when a high level signal is simultaneously input to the S input and the R input. Therefore, the pulse width input to the SR latch circuit 15 should be as small as possible.

  However, in the electronic circuit device 10A of FIG. 1, if the output pulse width of the edge detection circuits 11 and 12 is extremely small, the logic of the pulses input to the SR latch circuit 15 via the variable delay circuits 13 and 14 is achieved. The amplitude becomes extremely small, which may cause the SR latch circuit 15 to be unable to operate normally.

  On the other hand, in the electronic circuit device 10C of FIG. 6, since the variable delay circuit is not inserted between the third and fourth edge detection circuits 16, 17 and the SR latch circuit 15, the third and fourth edges The output pulse width of the detection circuits 16 and 17 can be made smaller than the output pulse width of the first and second edge detection circuits 11 and 12 of the electronic circuit device 10A of FIG. That is, the width of the pulse input to the SR latch circuit 15 can be further reduced, and the logical amplitude at that time can be prevented from being lowered. The fact that the pulse width inputted to the SR latch circuit 15 can be made smaller means that the minimum value of the timing difference between the S input and the R input inputted to the SR latch circuit 15, that is, the output Q pulse of the SR latch circuit 15. This means that the minimum value of the pulse width can be made smaller.

  As described above, according to the electronic circuit device 10C of the second embodiment, it is possible to realize a pulse shaping circuit for an NRZ signal and to reduce output jitter of the pulse shaping circuit. Furthermore, it is possible to relax the restriction on the minimum value of the pulse width of the output pulse of the pulse shaping circuit. Further, as shown in the timing chart of FIG. 7, both set values are maintained while maintaining the difference between the set value of the delay amount of the first variable delay circuit 13 and the set value of the delay amount of the second variable delay circuit 14. It is possible to use the electronic circuit device 10C as a variable delay circuit by changing.

  FIG. 8 is a block diagram showing a configuration example of the edge detection circuits 11, 12, 16, and 17 applicable to the electronic circuit devices 10A and 10C according to the first and second embodiments of the present invention. FIG. 8A shows an edge detection circuit 20A for detecting a rising edge, which is composed of an inverter 21, a delay circuit 22, and an AND circuit 23. FIG. 8B shows a falling edge detection edge detection circuit 20B, which includes an inverter 24, a delay circuit 25, and an AND circuit 26. The pulse widths of the output pulses of these edge detection circuits 20A and 20B are determined by the delay amounts of the delay circuits 22 and 25. When these edge detection circuits 20A and 20B are used, if the minimum pulse width of the input signal is T seconds, the delay amounts of the delay circuits 22 and 25 need to be smaller than T seconds. In the case of a high-speed signal, the minimum pulse width of the input signal may be 100 ps or less.

  FIG. 9 is a diagram illustrating a configuration example of the variable delay circuits 13 and 14 applicable to the electronic circuit devices 10A and 10C according to the first and second embodiments of the present invention. FIG. 9A shows a variable delay circuit 30A in which different delay times can be set. The variable delay circuit 30A includes delay circuits 31 and 32 and a signal selection circuit 33 in which different delay times are set. FIG. 9B shows a variable delay circuit 30B that can select whether to delay by a predetermined amount or not, and includes a delay circuit 34 and a signal selection circuit 35.

  In the electronic circuit device 10A according to the first embodiment described above, the same effect can be obtained even when the first variable delay circuit 13 or the second variable delay circuit 14 is deleted and the deleted portion is short-circuited. . Further, in the electronic circuit device 10C according to the second embodiment, the first edge detection circuit 11 and the first variable delay circuit 13 or the second edge detection circuit 12 and the second variable delay circuit 14 are deleted, and the deletion is performed. A similar effect can be obtained even in a configuration in which the portions are short-circuited. Further, when an RZ signal or the like is input, it is possible to input the same signal as the signal input A1 to the signal input A2.

It is a block diagram which shows the structure of the electronic circuit apparatus of Example 1 of this invention. 2 is a timing chart illustrating an operation of the electronic circuit device of FIG. 1. It is a block diagram which shows the structure of the modification of the electronic circuit device of FIG. 4 is a timing chart showing an operation when a minimum pulse width of an input signal to the electronic circuit device of FIG. 3 is sufficiently large. 4 is a timing chart showing an operation when a minimum pulse width of an input signal to the electronic circuit device of FIG. 3 is small. 2 is a timing chart showing an operation when a minimum pulse width of an input signal to the electronic circuit device of FIG. 1 is small. It is a block diagram which shows the structure of the electronic circuit apparatus of Example 2 of this invention. 7 is a timing chart showing an operation of the electronic circuit device of FIG. 6. It is a block diagram which shows the structural example of the edge detection circuit applicable to the electronic circuit apparatus of this invention. It is a block diagram which shows the structural example of the variable delay circuit applicable to the electronic circuit apparatus of this invention. It is a block diagram which shows the structure of the conventional pulse shaping circuit.

Explanation of symbols

A1, A2: signal input, B1, B2: delay amount setting input, Q: signal output 10A, 10B, 10C: electronic circuit device, 11, 12: edge detection circuit, 13, 14: variable delay circuit, 15: SR latch Circuit, 16, 17: Edge detection circuit 20A, 20B: Edge detection circuit, 21: Inverter, 22: Delay circuit, 23: AND circuit, 24: Inverter, 25: Delay circuit, 26: AND circuit 30A, 30B: Variable Delay circuit 31, 32: Delay circuit 33: Signal selection circuit 34: Delay circuit 35: Signal selection circuit 40: Pulse shaping circuit 41: Edge detection circuit 42: Variable delay circuit 43: OR circuit 44 : SR latch circuit

Claims (7)

  An SR latch circuit, first and second variable delay circuits, and first and second edge detection circuits are provided, and an output of the first edge detection circuit is connected to an input of the first variable delay circuit. The output of the second edge detection circuit is connected to the input of the second variable delay circuit, the output of the first variable delay circuit is connected to the S input of the SR latch circuit, and the SR latch circuit An electronic circuit device, wherein an output of the second variable input circuit is connected to an R input.   An SR latch circuit; first and second variable delay circuits; and first, second, third, and fourth edge detection circuits, wherein the first edge detection is input to the first variable delay circuit. An output of the circuit is connected, an output of the second edge detection circuit is connected to an input of the second variable delay circuit, and an output of the first variable delay circuit is connected to an input of the third edge detection circuit. An output of the second variable delay circuit is connected to an input of the fourth edge detection circuit; an output of the third edge detection circuit is connected to an S input of the SR latch circuit; An electronic circuit device, wherein an output of the fourth edge detection circuit is connected to an R input of the circuit. The electronic circuit device according to claim 1 or 2,
One of the first and second variable delay circuits is deleted, and the deleted portion is short-circuited. The electronic circuit device according to claim 1, 2, or 3,
An electronic circuit device, wherein a signal obtained by logically inverting a signal input to the first edge detection circuit is input to an input of the second edge detection circuit. The electronic circuit device according to claim 2 or 4,
An electronic circuit device, wherein the first edge detection circuit and the first variable delay circuit or the second edge detection circuit and the second variable delay circuit are deleted, and the deleted portion is short-circuited. The electronic circuit device according to claim 1, 2, 3, 4 or 5,
The electronic circuit device, wherein the first and second edge detection circuits output a signal having a pulse width smaller than a minimum pulse width of a signal input to the first and second edge detection circuits. The electronic circuit device according to claim 2, 3, 4, 5 or 6,
The electronic circuit device, wherein the third and fourth edge detection circuits output a signal having a pulse width smaller than a minimum pulse width of a signal input to the third and fourth edge detection circuits.

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