JP2009005029A - Electronic circuit equipment - Google Patents

Abstract

In transmission of a signal such as NRZ in which the pulse width is intentionally changed, variation in pulse width is reduced, and jitter is further reduced.
Two edge detection circuits (11, 12), two variable delay circuits (13, 14), and an SR latch circuit (15) are provided, and the edge detection circuits (11, 11) are respectively input to the variable delay circuits (13, 14). 12 outputs are connected, and the outputs of the variable delay circuits 13, 14 are connected to the S input and R input of the SR latch circuit, respectively. The SR latch circuit 15 detects the pulse termination edge of the outputs of the variable delay circuits 13 and 14 and performs a set / reset operation.
[Selection] Figure 1

Description

  The present invention relates to an electronic circuit device that performs high-speed signal generation or signal waveform shaping.

  In an electronic circuit using a pulse signal, when transmitting the same pulse signal in a plurality of different transmission systems, a variable delay circuit is used to adjust a skew that is a deviation from an expected value of phase or time generated between the signals. May need to be transmitted over the network. This variable delay circuit can be composed of multi-stage inverters and gate elements. In such a configuration, the pulse width of the signal that has passed through the multi-stage circuit is constant because the pulse width of the variable widens or narrows due to variations in each element. There is a case not to do.

  As a method for solving this problem, a pulse shaping circuit that generates an arbitrary pulse width independent of the pulse width of an input signal has been proposed (for example, see Patent Document 1). FIG. 20 shows a simplified configuration of an example of the pulse shaping circuit. The pulse shaping circuit 50 includes an edge detection circuit 51 that detects a falling edge, a variable delay circuit 52, an OR circuit 53, and an SR (set / reset type, hereinafter the same) latch circuit 54.

In this pulse shaping circuit 50, the SR latch circuit 54 is set when the output of the edge detection circuit 51 rises to H level in response to the fall of the input signal, and the output of the edge detection circuit 51 is changed by the variable delay circuit 52. When the delayed signal rises to the H level, the SR latch circuit 54 is reset, so that the input signal is shaped into a signal having a predetermined pulse width and output from the SR latch circuit 54.
Japanese Patent No. 3653115

  However, the pulse shaping circuit 50 shown in FIG. 20 can be used when outputting a signal having a fixed pulse width (for example, a repetitive simple signal called a clock signal or an RZ signal). When a signal (for example, NRZ signal) that intentionally changes the signal is input to the pulse shaping circuit 50, there is a problem that the output is different from the intended signal.

  An object of the present invention is to reduce variations in pulse width even in transmission of a signal (for example, an NRZ signal) that intentionally changes the pulse width, thereby further reducing jitter (phase noise) and further increasing the speed of a high-speed signal. It is an object of the present invention to provide an electronic circuit device that enables output timing adjustment and output pulse width adjustment.

An electronic circuit device according to a first aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, and first and second edge detection circuits, and is input to the first variable delay circuit. The output of the first edge detection circuit is connected, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the first variable delay is connected to the S input of the SR latch circuit. The output of the second variable delay circuit is connected to the R input of the SR latch circuit, and the SR latch circuit is connected to the pulse termination side of the outputs of the first and second variable delay circuits. An edge is detected and a set / reset operation is performed.
An electronic circuit device according to a second aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, and first, second, third, and fourth edge detection circuits, and the first The output of the first edge detection circuit is connected to the input of the variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the output of the first variable delay circuit The input of the third edge detection circuit is connected to the output, the input of the fourth edge detection circuit is connected to the output of the second variable delay circuit, and the third input is connected to the S input of the SR latch circuit. The output of the edge detection circuit is connected, the output of the fourth edge detection circuit is connected to the R input of the SR latch circuit, and the third edge detection circuit is connected to the pulse termination side of the output of the first variable delay circuit. Detecting an edge and outputting a pulse, the fourth edge Detection circuit is characterized in that so as to output a pulse by detecting a pulse termination side edge of the output of said second variable delay circuit.
An electronic circuit device according to a third aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, first and second edge detection circuits, and first and second polarity switching circuits. The output of the first edge detection circuit is connected to the input of the first variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and The first polarity switching circuit is connected to the output of one variable delay circuit, the second polarity switching circuit is connected to the output of the second variable delay circuit, and the second input is connected to the S input of the SR latch circuit. The output of the first polarity switching circuit is connected, and the output of the second polarity switching circuit is connected to the R input of the SR latch circuit.
An electronic circuit device according to a fourth aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, first and second edge detection circuits, and first and second polarity switching circuits. The output of the first edge detection circuit is connected to the input of the first polarity switching circuit, the output of the second edge detection circuit is connected to the input of the second polarity switching circuit, The input of the first variable delay circuit is connected to the output of the first polarity switching circuit, the input of the second variable delay circuit is connected to the output of the second polarity switching circuit, and the first variable delay circuit The S input of the SR latch circuit is connected to the output of the circuit, and the R input of the SR latch circuit is connected to the output of the second variable delay circuit.
An electronic circuit device according to a fifth aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, first, second, third and fourth edge detection circuits, first and second Polarity switching circuit, the output of the first edge detection circuit is connected to the input of the first variable delay circuit, and the output of the second edge detection circuit is connected to the input of the second variable delay circuit Connecting the input of the first polarity switching circuit to the output of the first variable delay circuit, connecting the input of the second polarity switching circuit to the output of the second variable delay circuit, and The input of the third edge detection circuit is connected to the output of the first polarity switching circuit, the output of the second polarity switching circuit is connected to the input of the fourth edge detection circuit, and the SR latch circuit The SR input is connected to the output of the third edge detection circuit, and the SR ladder is connected. Characterized in that connects the output of said fourth edge detection circuit to the R input of the circuit.
An electronic circuit device according to a sixth aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, and first, second, third, and fourth edge detection circuits. The output of the first edge detection circuit is connected to the input of the variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the output of the first variable delay circuit The input of the third edge detection circuit is connected to the output, the input of the fourth edge detection circuit is connected to the output of the second variable delay circuit, and the third input is connected to the S input of the SR latch circuit. The output of the edge detection circuit is connected, the output of the fourth edge detection circuit is connected to the R input of the SR latch circuit, and the third edge detection circuit is connected to the pulse termination side of the output of the first variable delay circuit. Detect pulse by detecting edge or edge of pulse start side The output can be switched to output, and the fourth edge detection circuit can be switched to detect a pulse termination side edge or a pulse start side edge of the output of the second variable delay circuit and output a pulse. Features.
An electronic circuit device according to a seventh aspect of the present invention includes an SR latch circuit, first and second variable delay circuits, first, second, third and fourth edge detection circuits, first and second The polarity switching circuit, the output of the first edge detection circuit is connected to the input of the first polarity switching circuit, and the output of the second edge detection circuit is connected to the input of the second polarity switching circuit. Connecting the input of the first variable delay circuit to the output of the first polarity switching circuit, connecting the input of the second variable delay circuit to the output of the second polarity switching circuit, and An input of the third edge detection circuit is connected to an output of the first variable delay circuit, an input of the fourth edge detection circuit is connected to an output of the second variable delay circuit, and the SR latch circuit The SR input is connected to the output of the third edge detection circuit, and the SR ladder is connected. Characterized in that connects the output of said fourth edge detection circuit to the R input of the circuit.
The invention according to claim 8 is the electronic circuit device according to any one of claims 1 to 7, wherein one of the first and second variable delay circuits is deleted and the deleted portion is short-circuited. Features.
The invention according to claim 9 is the electronic circuit device according to any one of claims 1 to 8, wherein a signal obtained by logically inverting a signal input to the first edge detection circuit is the second edge detection circuit. It is characterized by inputting to the input.
The invention according to claim 10 is the electronic circuit device according to claim 2, 3, 5 or 6, wherein the first edge detection circuit and the first variable delay circuit or the second edge detection circuit and the The second variable delay circuit is deleted, and the deleted portion is short-circuited.
According to an eleventh aspect of the present invention, in the electronic circuit device according to the first, third, or fourth aspect, the signals input to the first and second edge detection circuits by the first and second edge detection circuits. A signal having a pulse width smaller than the minimum pulse width is output.
According to a twelfth aspect of the present invention, in the electronic circuit device according to the second, fifth, sixth, or seventh aspect, the third and fourth edge detection circuits are input to the third and fourth edge detection circuits. A signal having a pulse width smaller than the minimum pulse width of the output signal is output.

  According to the present invention, even in the transmission of a signal (for example, an NRZ signal) that intentionally changes the pulse width, variations in pulse width can be reduced, jitter (phase noise) can be reduced, and high-speed signal output can be performed. Timing adjustment and output pulse width adjustment are also possible.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In addition, the same number is assigned to the common part in all drawings, and duplication description is avoided.

<Example 1>
FIG. 1 is a diagram showing a configuration of an electronic circuit device 10A according to a first embodiment of the present invention. The electronic circuit device 10 </ b> A includes a first edge detection circuit 11, a second edge detection circuit 12, a first variable delay circuit 13, a second variable delay circuit 14, and an SR latch circuit 15. Then, the output 11a of the first edge detection circuit 11 is connected to the input of the first variable delay circuit 13, the output 12a of the second edge detection circuit 12 is connected to the input of the second variable delay circuit 14, The output 13a of the first variable delay circuit 13 is connected to the S (set, same hereinafter) input of the SR latch circuit 15, and the second variable input circuit 14 is connected to the R (reset, same hereinafter) input of the SR latch circuit 15. The output 14a is connected.

  The first edge detection circuit 11 detects the edge (rising or falling) of the signal input A1, and outputs the timing information of the edge from the output 11a as the output timing of a pulse signal having a predetermined pulse width. . The second edge detection circuit 12 detects an edge (rising or falling) of the signal input A2, and outputs information on the timing of the edge from the output 12a as an output timing of a pulse signal having a predetermined pulse width. .

  The first variable delay circuit 13 delays the signal input from the first edge detection circuit 11 by the delay amount set by the delay amount setting input B1, and outputs it from the output 13a. The second variable delay circuit 14 delays the signal input from the second edge detection circuit 12 by the delay amount set by the delay amount setting input B2, and outputs the delayed signal from the output 14a.

  The SR latch circuit 15 detects the pulse termination side edges of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 and performs a set / reset operation. Here, the termination edges of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 are edges (falling edges) at which the outputs 13a and 14a change from H level to L level. is there. The SR latch circuit 15 outputs an H level when the S input changes from the H level to the L level, and outputs an L level when the R input changes from the H level to the L level.

  FIG. 2 shows a timing chart when the electronic circuit device 10A is used as a pulse shaping circuit for an NRZ signal. However, the first and second edge detection circuits 11 and 12 are assumed to detect the rising edges of the inputs A1 and A2. When used as a pulse shaping circuit for the NRZ signal, a signal obtained by logically inverting the signal of the signal input A1 is input to the signal input A2.

  As shown in FIG. 2, the rising timing and falling timing of the output Q of the SR latch circuit 15 can be freely set by setting the delay amounts of the first and second variable delay circuits 13 and 14. Here, the delay time t2 is set by the first variable delay circuit 13, and the delay time t3 is set by the second variable delay circuit 14, respectively. t1 is the time difference between the signals of the inputs A1 and A2.

  The above function is a configuration in which the arrangement of the first edge detection circuit 11 and the first variable delay circuit 13 is exchanged, and the arrangement of the second edge detection circuit 12 and the second variable delay circuit 14 is exchanged. However, it is feasible, but such a configuration has the following problems.

  In FIG. 3, the first and second edge detection circuits 11, 12 are connected to the outputs 13a, 14a of the first and second variable delay circuits 13, 14, and the first and second edge detection circuits 11, 12 are connected. The electronic circuit device 10B in which the outputs 11a and 12a are connected to the S input and the R input of the SR latch circuit 15 is shown. 4A and 4B show timing charts when this is used as a pulse shaping circuit for an NRZ signal.

  When the minimum pulse width of the signal input A1 and the signal input A2 which is the logical inversion signal thereof is sufficiently large, as shown in FIG. 4A, the signals of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 are output. Since signal degradation such as a partial decrease in logical amplitude (or voltage amplitude in a normal electronic circuit device) hardly occurs, the signal input to the SR latch circuit 15 is the same signal as in FIG.

  However, when the minimum pulse width of the signal input A1 and the signal input A2 that is the logical inversion signal thereof is reduced to some extent, as shown in FIG. 4B (the scale of the time axis is expanded from that in FIG. 4A), the first The first and second edge detection circuits 11 input to the SR latch circuit 15 result in a partial decrease in the logic amplitude of the signals at the outputs 13 a and 14 a of the second variable delay circuits 13 and 14. , 12 output signals 11a and 12a fall at different timings from those in FIG. In addition, the broken line of FIG. 4B shows the waveform in a normal case.

  As a result, the rising timing and falling timing of the output Q of the SR latch circuit 15 are also different from those in FIG. As shown in FIG. 4B, the magnitude of this timing deviation does not become a constant magnitude. Therefore, the pulse width of the output Q of the SR latch circuit 15 does not become as set. Note that a timing shift such as the output Q of the SR latch circuit 15 is generally called jitter (phase noise).

  On the other hand, when the electronic circuit device 10A of FIG. 1 is used as a pulse shaping circuit for an NRZ signal and a signal input similar to that of FIG. 4B is input, a timing chart is shown in FIG. It is shown in The pulse widths of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 do not depend on the pulse widths of the input signals (A1 and A2).

  As shown in FIG. 5, there are cases where the logical amplitude of the signals 13a and 14a of the first and second variable delay circuits 13 and 14 decreases, but the logical amplitude decreases in the same manner for all pulses. As a result, the pulse width of the output Q of the SR latch circuit 15 is almost the same as the set value. That is, the jitter of the output Q of the SR latch circuit 15 is smaller than in the case of FIG. 4B.

  From the above, according to the electronic circuit device 10A of the first embodiment, it is possible to realize a pulse shaping circuit for an NRZ signal and to reduce output jitter of the pulse shaping circuit. Also, as shown in the timing charts of FIGS. 2 and 5, the difference between the delay amount setting value t2 of the first variable delay circuit 13 and the delay amount setting value t3 of the second variable delay circuit 14 is maintained. By changing both the set values t2 and t3, it is possible to use the electronic circuit device 10A of FIG. 1 as a variable delay circuit.

<Example 2>
FIG. 6 is a diagram showing a configuration of an electronic circuit device 10C according to the second embodiment of the present invention. The electronic circuit device 10 </ b> C includes a first edge detection circuit 11, a second edge detection circuit 12, a first variable delay circuit 13, a second variable delay circuit 14, and a third edge detection circuit 16. And a second edge detection circuit 17 and an SR latch circuit 15 ′. The output 11a of the first edge detection circuit 11 is connected to the input of the first variable delay circuit 13, and the output 12a of the second edge detection circuit 12 is connected to the input of the second variable delay circuit 14. The input of the third edge detection circuit 16 is connected to the output 13a of the first variable delay circuit 13, the input of the fourth edge detection circuit 17 is connected to the output 14a of the second variable delay circuit 14, and SR. The output 16a of the third edge detection circuit 16 is connected to the S input of the latch circuit 15 ′, and the output 17a of the fourth edge detection circuit 17 is connected to the R input of the SR latch circuit 15 ′.

  The SR latch circuit 15 'is different from that in the electronic circuit device 10A of the first embodiment, and detects the pulse start side edge of the outputs 16a and 17a of the first and second edge detection circuits 16 and 17 to perform the set / reset operation. I do. Here, the start side edges of the outputs 16a and 17a are edges (rising edges) at which the outputs 16a and 17a change from the L level to the H level. The SR latch circuit 15 'outputs the H level when the S input changes from the L level to the H level, and outputs the L level when the R input changes from the L level to the H level.

  The third edge detection circuit 16 detects the terminal-side edge of the output 13a of the first variable delay circuit 13, and uses the timing information of the edge as the output timing of a pulse signal having a predetermined pulse width. Output from. The fourth edge detection circuit 17 detects the terminal-side edge of the output 14a of the second variable delay circuit 14, and uses the timing information of the edge as the output timing of a pulse signal having a predetermined pulse width. Output from.

  FIG. 7 shows a timing chart when the electronic circuit device 10C is used as a pulse shaping circuit for an NRZ signal. When used as a pulse shaping circuit for the NRZ signal, a signal obtained by logically inverting the signal of the signal input A1 is input to the signal input A2.

  As shown in FIG. 7, the rising timing and falling timing of the output Q of the SR latch circuit 15 ′ can be freely set by setting the delay amounts of the first and second variable delay circuits 13 and 14. In addition, since the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 are connected to the inputs of the first and second variable delay circuits 13 and 14, the electronic circuit device 10A of FIG. Similarly to the above, it is possible to reduce the jitter of the output Q of the SR latch circuit 15 ′.

  When the electronic circuit device 10C of FIG. 6 is compared with the electronic circuit device 10A of FIG. 1, the electronic circuit device 10C of FIG. 6 has the third and fourth edge detection circuits 16 and 17 mounted thereon. Therefore, there are the following advantages. Usually, the SR latch circuit has a problem that it cannot operate normally when a signal of H level is simultaneously input to the S input and the R input. Therefore, the pulse width input to the SR latch circuit should be as small as possible. Therefore, in the electronic circuit device 10A of FIG. 1, it is preferable to make the pulse widths of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 smaller than the minimum pulse width of the input pulses.

  However, in the electronic circuit device 10A of FIG. 1, if the pulse widths of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 are extremely small, the first and second variable delay circuits 13 and 14 are used. As a result, the logic amplitude of the pulse input to the SR latch circuit 15 becomes extremely small, which may cause the SR latch circuit 15 to be unable to operate normally.

  On the other hand, in the electronic circuit device 10C of FIG. 6, no variable delay circuit is inserted between the third and fourth edge detection circuits 16, 17 and the SR latch circuit 15 ′. The pulse widths of the outputs 16a and 17a of the edge detection circuits 16 and 17 can be made smaller than the pulse widths of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 in the electronic circuit device 10A of FIG. . That is, it is possible to make the width of the pulse input to the SR latch circuit 15 'smaller (smaller than the minimum input pulse width). The fact that the width of the pulse input to the SR latch circuit 15 ′ can be made smaller means that the minimum value of the timing difference between the S input and the R input input to the SR latch circuit 15 ′, that is, the SR latch circuit 15 This means that the minimum value of the pulse width of the output pulse of the output Q can be made smaller.

  As described above, according to the electronic circuit device 10C of the second embodiment, it is possible to realize a pulse shaping circuit for an NRZ signal and to reduce output jitter of the pulse shaping circuit. Further, it is possible to relax the restriction on the minimum value of the pulse width of the output pulse of the pulse shaping circuit. Further, as shown in the timing chart of FIG. 7, both the delay amount setting value t2 of the first variable delay circuit 13 and the delay amount setting value t3 of the second variable delay circuit 14 are maintained while maintaining the difference between them. By changing the set value, the electronic circuit device 10C can be used as a variable delay circuit.

  FIG. 8 is a block diagram showing a configuration example of the edge detection circuits 11, 12, 16, and 17 applicable to the electronic circuit devices 10A and 10C according to the first and second embodiments of the present invention. FIG. 8A shows an edge detection circuit 30 </ b> A for detecting a rising edge, which includes an inverter 31, a delay circuit 32, and an AND circuit 33. FIG. 8B shows an edge detection circuit 30B for detecting a falling edge, which includes an inverter 34, a delay circuit 35, and an AND circuit 36. The pulse widths of the output pulses of these edge detection circuits 30A and 30B are determined by the delay amounts of the delay circuits 32 and 35. When these edge detection circuits 30A and 30B are used, if the minimum pulse width of the input signal is T seconds, the delay amounts of the delay circuits 32 and 35 must be smaller than T seconds. In the case of a high-speed signal, the minimum pulse width of the input signal may be 100 ps or less.

  FIG. 9 is a diagram illustrating a configuration example of the variable delay circuits 13 and 14 applicable to the electronic circuit devices 10A and 10C according to the first and second embodiments of the present invention. FIG. 9A shows a variable delay circuit 40A in which different delay times can be set. The variable delay circuit 40A includes delay circuits 41 and 42 and a signal selection circuit 33 in which different delay times are set. FIG. 9B shows a variable delay circuit 40B that can select whether to delay by a predetermined amount or not, and includes a delay circuit 44 and a signal selection circuit 45. Note that a plurality of these delay circuits connected in cascade so that any delay circuit output can be selected can be used as the variable delay circuit.

<Example 3>
By the way, in the description so far, the jitters of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 are not considered. In other words, when the jitter at the termination edge of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 is negligibly small, the effects described above can be obtained.

  However, when the first and second edge detection circuits 11 and 12 are configured by, for example, the edge detection circuit 30A as shown in FIG. 8, the jitter at the termination edge of the output of the edge detection circuit 30A is more than the jitter at the start edge. Also grows. This is because the jitter of the signal input to the AND circuit 33 through the delay circuit 32 is larger than the jitter of the signal input to the AND circuit 33 without passing through the delay circuit 32.

  Therefore, depending on the jitter characteristics of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12, an SR latch circuit is formed at the termination side edges of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14. 15 (or the third and fourth edge detection circuits 16 and 17) without operating the SR latch circuit 15 (or the start edge of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14). In some cases, the jitter of the output Q of the SR latch circuit 15 becomes smaller when the third and fourth edge detection circuits 16 and 17) are operated.

  In consideration of this point, the SR latch circuit 15 (or the third and fourth) is selected by selecting either the termination side edge or the start side edge of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14. By adding a circuit for operating the edge detection circuits 16, 17), it is possible to select and use a condition with smaller jitter after the manufacture of the electronic circuit device.

  The configuration of the electronic circuit device 10D to which a circuit for performing this selection is added is, for example, as shown in FIG. In FIG. 10, 18 and 19 are inverters, and 20 and 21 are signal selection circuits. The inverter 18 and the signal selection circuit 20 constitute a first polarity switching circuit, and the inverter 19 and the signal selection circuit 21 constitute a second polarity switching circuit.

  FIG. 11 shows a specific operation example when the selection setting inputs C1 and C2 are input so that the outputs of the inverters 18 and 19 are input to the SR latch circuit 15 (the electronic circuit device 10D is the electronic circuit of the first embodiment). This is an example in the case of operating in the same manner as the apparatus 10A). When the output 13a of the first variable delay circuit 13 changes from the L level to the H level, the S input of the SR latch circuit 15 changes from the H level to the L level. H level is output. On the other hand, when the output 14a of the second variable delay circuit 14 changes from the L level to the H level, the R input of the SR latch circuit 15 changes from the H level to the L level. Q outputs L level.

<Example 4>
FIG. 12 shows another example in which an electronic circuit device 10E equivalent to the electronic circuit device 10D of FIG. Here, inverters 18 and 19 and a signal selection circuit 20 are provided between the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 and the inputs of the first and second variable delay circuits 13 and 14, respectively. , 21 is inserted. The inverter 18 and the signal selection circuit 20 constitute a first polarity switching circuit, and the inverter 19 and the signal selection circuit 21 constitute a second polarity switching circuit.

  FIG. 13 shows a specific operation example when the selection setting inputs C1 and C2 are input so that the outputs of the inverters 18 and 19 are input to the variable delay circuits 13 and 14, respectively. When the output 11a of the edge detection circuit 11 changes from the L level to the H level, the output 20a of the signal selection circuit 20 changes from the H level to the L level, and after the delay time elapses, the output 13a of the variable delay circuit 13 changes to the H level. When changing from L to L level, the output Q of the SR latch circuit 15 outputs H level at that time. On the other hand, when the output 12a of the edge detection circuit 11 changes from the L level to the H level, the output 21a of the signal selection circuit 21 changes from the H level to the L level, and the output 14a of the variable delay circuit 14 changes after the delay time elapses. When the level changes from H level to L level, the output Q of the SR latch circuit 15 outputs L level at that time.

<Example 5>
FIG. 14 operates the third and fourth edge detection circuits 16 and 17 by selecting either the termination edge or the start edge of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14. It is an example of a structure of the electronic circuit device 10F at the time of adding the circuit to make. Here, inverters 18 and 19 and a signal selection circuit 20 are provided between the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 and the inputs of the third and fourth edge detection circuits 16 and 17, respectively. , 21 is inserted. The inverter 18 and the signal selection circuit 20 constitute a first polarity switching circuit, and the inverter 19 and the signal selection circuit 21 constitute a second polarity switching circuit.

  FIG. 15 shows a specific operation example when selection setting inputs C1 and C2 are input so that the outputs of the inverters 18 and 19 of the electronic circuit device 10F are input to the third and fourth edge detection circuits 16 and 17, respectively. (In this example, the electronic circuit device 10E operates in the same manner as the electronic circuit device 10C of the second embodiment). When the output 13a of the first variable delay circuit 13 changes from the L level to the H level, the input of the third edge detection circuit 16 changes from the H level to the L level. 16 outputs a pulse. Similarly, when the output 14a of the second variable delay circuit 14 changes from the L level to the H level, the input of the fourth edge detection circuit 17 changes from the H level to the L level. The detection circuit 17 outputs a pulse.

  FIG. 16 is a diagram showing an edge detection circuit 30C in which the output of the rising edge detection circuit 30A and the output of the falling edge detection circuit 30B shown in FIG. is there. By replacing the edge detection circuit 30C with the third and fourth edge detection circuits 16 and 17 in the electronic circuit device 10C of FIG. 6, respectively, a circuit equivalent to the electronic circuit device 10F of FIG. Operates equally.

<Example 6>
FIG. 17 shows another example in which an electronic circuit device 10G equivalent to the electronic circuit device 10E of FIG. Here, inverters 18 and 19 and a signal selection circuit 20 are provided between the outputs 11a and 12a of the first and second edge detection circuits 11 and 12 and the inputs of the first and second variable delay circuits 13 and 14, respectively. , 21 is inserted. The inverter 18 and the signal selection circuit 20 constitute a first polarity switching circuit, and the inverter 19 and the signal selection circuit 21 constitute a second polarity switching circuit.

  FIG. 18 shows a specific example of the case where the selection setting inputs C1 and C2 are input so that the outputs of the inverters 17 and 18 are input to the first and second variable delay circuits 13 and 14 in the electronic circuit device 10G of FIG. (Example in which electronic circuit device 10F operates in the same manner as electronic circuit device 10C of the second embodiment). When the output 11a of the first edge detection circuit 11 changes from L level to H level, the output 13a of the first variable delay circuit 13 changes from H level to L level. Similarly, when the output 14a of the second edge detection circuit 12 changes from L level to H level, the output 14a of the second variable delay circuit 14 changes from H level to L level.

  As described above, in the electronic circuit devices 10F and 10G according to the fifth and sixth embodiments, in consideration of the jitter of the outputs 11a and 12a of the first and second edge detection circuits 11 and 12, By adding a circuit for operating the SR latch circuit 15 (or the third and fourth edge detection circuits 16 and 17) by selecting one of the start side edges, the jitter becomes smaller after the electronic circuit device is manufactured. It becomes possible to select and use conditions.

  However, if the jitter at the end edge of the pulse does not become smaller than that at the start edge, a circuit for making such a selection is not necessary, so the jitter at the end edge of the pulse is not A description of an example that becomes smaller than the side edge is added.

  Consider the jitter at the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 when the electronic circuit device 10A of the first embodiment operates as shown in the timing chart of FIG. In the timing chart of FIG. 5, the waveforms of the outputs 13a and 14a of the first and second variable delay circuits 13 and 14 are approximated by straight lines, but the actual waveforms are as shown in FIG. That is, the slope (absolute value) of the head portion is the largest for both rising and falling, and the slope (absolute value) gradually decreases as going backward. Further, depending on the characteristics of the variable delay circuits 13 and 14, it may take a considerably long time to return to the ideal L level. If the time required to return to the ideal L level is Tf (FIG. 19 (a)), if the pulse interval is smaller than Tf, the next pulse will rise before returning to the ideal L level. .

  As described above, when the waveform when the pulse interval is short is compared with the waveform when the pulse interval is long, the output voltage (potential) when the pulse starts to rise is different, and the waveform is shifted by the potential difference. The jitter due to this waveform shift is almost inversely proportional to the slope (absolute value) of the waveform at the logic judgment threshold.

  In addition, when comparing the slope of the waveform at the logic judgment threshold at the rise and fall of the pulse, if the absolute value of the slope of the leading edge of the rising edge and the slope of the leading edge of the falling edge is the same, the falling edge is logical in a shorter time. Since the determination threshold is reached, the falling slope (absolute value) in the logical determination threshold is larger than the rising slope (absolute value) (see FIG. 19B).

  Therefore, when the characteristics of the electronic circuit device substantially satisfy the preconditions described above, the slope (absolute value) of the pulse fall at the logic determination threshold value is larger than the slope (absolute value) of the rise. The jitter that is almost inversely proportional to the slope (the absolute value thereof) is such that the falling edge of the pulse is smaller than the rising edge.

<Other embodiments>
In the electronic circuit devices 10A, 10C, 10D, 10E, 10F, and 10G described above, the first variable delay circuit 13 or the second variable delay circuit 14 may be deleted and the deleted portion may be short-circuited. Similar effects can be obtained. Further, in the electronic circuit devices 10C, 10D, and 10F, the first edge detection circuit 11 and the first variable delay circuit 13 or the second edge detection circuit 12 and the second variable delay circuit 14 are deleted, and the deletion is performed. A similar effect can be obtained even in a configuration in which the portions are short-circuited. Further, when an RZ signal or the like is input, it is possible to input the same signal as the signal input A1 to the signal input A2.

It is a block diagram which shows the structure of 10 A of electronic circuit apparatuses of Example 1 of this invention. It is a timing chart which shows operation | movement of 10 A of electronic circuit apparatuses of Example 1 of this invention. It is a block diagram which shows the structure of electronic circuit device 10B which replaced the edge detection circuit and variable delay circuit of electronic circuit device 10A of Example 1 of this invention. 4 is a timing chart showing the operation of the electronic circuit device 10B of FIG. 3 (when the minimum pulse width of the input signal is sufficiently large). 4 is a timing chart showing the operation of the electronic circuit device 10B of FIG. 3 (when the minimum pulse width of the input signal is small). It is a timing chart which shows operation | movement of 10 A of electronic circuit apparatuses of Example 1 of this invention (when the minimum pulse width of an input signal is small). It is a block diagram which shows the structure of 10C of electronic circuit apparatuses of Example 2 of this invention. It is a timing chart which shows operation | movement of 10 C of electronic circuit apparatuses of Example 2 of this invention. It is a block diagram which shows the structural example of the edge detection circuit applicable to each Example of this invention. It is a block diagram which shows the structural example of the variable delay circuit applicable to each Example of this invention. It is a block diagram which shows the structure of electronic circuit device 10D of Example 3 of this invention. It is a timing chart which shows operation | movement of electronic circuit device 10D of Example 3 of this invention. It is a block diagram which shows the structure of the electronic circuit apparatus 10E of Example 4 of this invention. It is a timing chart which shows operation | movement of the electronic circuit apparatus 10E of Example 4 of this invention. It is a block diagram which shows the structure of the electronic circuit apparatus 10F of Example 5 of this invention. It is a timing chart which shows operation | movement of the electronic circuit apparatus 10F of Example 5 of this invention. It is a block diagram which shows the structural example of the edge detection circuit applicable to the electronic circuit apparatus 10F of Example 5 of this invention. It is a block diagram which shows the structure of the electronic circuit apparatus 10G of Example 6 of this invention. It is a timing chart which shows operation | movement of the electronic circuit apparatus 10G of Example 6 of this invention. It is a waveform diagram of the output of the variable delay circuit in the electronic circuit device of the present invention. It is a block diagram which shows the structure of the conventional pulse shaping circuit.

Explanation of symbols

10A, 10B, 10C, 10D, 10E, 10F, 10G: electronic circuit device, 11, 12: edge detection circuit, 13, 14: variable delay circuit, 15: SR latch circuit, 16, 17: edge detection circuit, 18, 19: inverter, 20, 21: signal selection circuit 30A, 30B, 30C: edge detection circuit, 31: inverter, 32: delay circuit, 33: AND circuit, 34: inverter, 35: delay circuit, 36: AND circuit, 37 : Signal selection circuit 40A, 40B: Variable delay circuit, 41, 42: Delay circuit, 43: Signal selection circuit, 44: Delay circuit, 45: Signal selection circuit 50: Electronic circuit device, 51: Edge detection circuit, 52: Variable Delay circuit, 53: OR circuit, 54: SR latch circuit

Claims (12)

An SR latch circuit; first and second variable delay circuits; and first and second edge detection circuits;
The SR latch circuit connects the output of the first edge detection circuit to the input of the first variable delay circuit, connects the output of the second edge detection circuit to the input of the second variable delay circuit, and An output of the first variable delay circuit is connected to an S input of the second latch circuit, an output of the second variable delay circuit is connected to an R input of the SR latch circuit,
An electronic circuit device, wherein the SR latch circuit detects a pulse termination side edge of the outputs of the first and second variable delay circuits and performs a set / reset operation. An SR latch circuit; first and second variable delay circuits; and first, second, third and fourth edge detection circuits,
The output of the first edge detection circuit is connected to the input of the first variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the first The input of the third edge detection circuit is connected to the output of the variable delay circuit, the input of the fourth edge detection circuit is connected to the output of the second variable delay circuit, and the S input of the SR latch circuit. Connecting the output of the third edge detection circuit, connecting the output of the fourth edge detection circuit to the R input of the SR latch circuit;
The third edge detection circuit detects a pulse termination side edge of the output of the first variable delay circuit and outputs a pulse, and the fourth edge detection circuit outputs a pulse termination side of the output of the second variable delay circuit An electronic circuit device characterized in that an edge is detected and a pulse is output. An SR latch circuit; first and second variable delay circuits; first and second edge detection circuits; and first and second polarity switching circuits;
The output of the first edge detection circuit is connected to the input of the first variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the first The first polarity switching circuit is connected to the output of the variable delay circuit, the second polarity switching circuit is connected to the output of the second variable delay circuit, and the first input to the S input of the SR latch circuit. An electronic circuit device comprising: an output of a polarity switching circuit connected; and an output of the second polarity switching circuit connected to an R input of the SR latch circuit. An SR latch circuit; first and second variable delay circuits; first and second edge detection circuits; and first and second polarity switching circuits;
The output of the first edge detection circuit is connected to the input of the first polarity switching circuit, the output of the second edge detection circuit is connected to the input of the second polarity switching circuit, and the first The input of the first variable delay circuit is connected to the output of the polarity switching circuit, the input of the second variable delay circuit is connected to the output of the second polarity switching circuit, and the output of the first variable delay circuit An electronic circuit device comprising: an S input of the SR latch circuit connected to an output; and an R input of the SR latch circuit connected to an output of the second variable delay circuit. An SR latch circuit; first and second variable delay circuits; first, second, third and fourth edge detection circuits; and first and second polarity switching circuits;
The output of the first edge detection circuit is connected to the input of the first variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the first The input of the first polarity switching circuit is connected to the output of the variable delay circuit, the input of the second polarity switching circuit is connected to the output of the second variable delay circuit, and the output of the first polarity switching circuit The output of the third edge detection circuit is connected to the output, the output of the second polarity switching circuit is connected to the input of the fourth edge detection circuit, and the third input is connected to the S input of the SR latch circuit. An electronic circuit device comprising: an output of an edge detection circuit connected; and an output of the fourth edge detection circuit connected to an R input of the SR latch circuit. An SR latch circuit; first and second variable delay circuits; and first, second, third and fourth edge detection circuits,
The output of the first edge detection circuit is connected to the input of the first variable delay circuit, the output of the second edge detection circuit is connected to the input of the second variable delay circuit, and the first The input of the third edge detection circuit is connected to the output of the variable delay circuit, the input of the fourth edge detection circuit is connected to the output of the second variable delay circuit, and the S input of the SR latch circuit. Connecting the output of the third edge detection circuit, connecting the output of the fourth edge detection circuit to the R input of the SR latch circuit;
The third edge detection circuit is switchable to detect a pulse termination side edge or a pulse start side edge of the output of the first variable delay circuit and output a pulse, and the fourth edge detection circuit is configured to output the pulse. 2. An electronic circuit device capable of being switched to output a pulse upon detecting a pulse end side edge or a pulse start side edge of the output of the two variable delay circuits. An SR latch circuit; first and second variable delay circuits; first, second, third and fourth edge detection circuits; and first and second polarity switching circuits;
The output of the first edge detection circuit is connected to the input of the first polarity switching circuit, the output of the second edge detection circuit is connected to the input of the second polarity switching circuit, and the first The input of the first variable delay circuit is connected to the output of the polarity switching circuit, the input of the second variable delay circuit is connected to the output of the second polarity switching circuit, and the output of the first variable delay circuit The input of the third edge detection circuit is connected to the output, the input of the fourth edge detection circuit is connected to the output of the second variable delay circuit, and the third input is connected to the S input of the SR latch circuit. An electronic circuit device comprising: an output of an edge detection circuit connected; and an output of the fourth edge detection circuit connected to an R input of the SR latch circuit. The electronic circuit device according to any one of claims 1 to 7,
One of the first and second variable delay circuits is deleted, and the deleted portion is short-circuited. The electronic circuit device according to any one of claims 1 to 8,
An electronic circuit device, wherein a signal obtained by logically inverting a signal input to the first edge detection circuit is input to an input of the second edge detection circuit. The electronic circuit device according to claim 2, 3, 5 or 6,
An electronic circuit device, wherein the first edge detection circuit and the first variable delay circuit or the second edge detection circuit and the second variable delay circuit are deleted, and the deleted portion is short-circuited. The electronic circuit device according to claim 1, 3 or 4,
The electronic circuit device, wherein the first and second edge detection circuits output a signal having a pulse width smaller than a minimum pulse width of a signal input to the first and second edge detection circuits. The electronic circuit device according to claim 2, 5, 6, or 7,
The electronic circuit device, wherein the third and fourth edge detection circuits output a signal having a pulse width smaller than a minimum pulse width of a signal input to the third and fourth edge detection circuits.

Images