JPH10223773A - Power supply protection circuit - Google Patents

Abstract

(57) [Problem] To provide an inter-power supply protection circuit capable of preventing a large current from flowing through a transistor connected between power supply lines even when a reverse voltage is applied to the power supply line. SOLUTION: An NMOS transistor 1 for protection between power supplies connected between a power supply line 4 for operating power supply and a power supply line 5 for grounding, and N connected in series between the power supply lines 4 and 5
NMOS transistors 2 and 3 for controlling the gate voltage of the MOS transistor 1 are provided. During normal operation, transistor 2 is off, transistor 3 is on, and transistor 1 is off. When a reverse voltage is applied, the transistor 2 is turned on, the transistor 3 is turned off, and the transistor 1 is turned off. As described above, the transistor 1 is turned off both during the normal operation and when the reverse voltage is applied, so that a large current can be prevented from flowing through the transistor 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply protection circuit for a semiconductor device.

[0002]

2. Description of the Related Art FIG. 7 shows a configuration of a conventional power supply protection circuit of a semiconductor device. In FIG. 7, reference numeral 31 denotes an NMOS transistor for power supply protection, and 32 denotes an operating voltage Vc.
Reference numeral 33 denotes a power supply line for operating power supply for applying c, and reference numeral 33 denotes a power supply line for ground for applying ground voltage Vss.

In this conventional power supply protection circuit, an NMOS transistor 31 is connected between power supply lines 32 and 33. The NMOS transistor 31 has a drain connected to a power supply line 32 for operating power supply, a source and a gate. Are connected to a power supply line 33 for grounding. This NM
Since the gate of the OS transistor 31 is connected to the power supply line 33 for grounding, the OS transistor 31 is always kept off during normal operation.

[0004]

However, in the above-described conventional configuration, for example, when the power supply lines 32 and 33 are reversely inserted and connected to the power supply, or when a reverse voltage is applied to the power supply lines 32 and 33, for example, That is, when the ground voltage Vss is applied to the power supply line 32 for operating power supply and the operating voltage Vcc is applied to the power supply line 33 for grounding, N
The MOS transistor 31 is always turned on, and has a problem that a large current flows.

An object of the present invention is to provide an inter-power supply protection circuit capable of preventing a large current from flowing through transistors connected between power supply lines even when a reverse voltage is applied to the power supply lines. .

[0006]

In order to achieve this object, an inter-power supply protection circuit according to the present invention comprises a first inter-power supply protection circuit connected between a power supply line for operating power supply and a power supply line for grounding. And the first transistor connected in series between the operating power supply line and the grounding power supply line during normal operation.
Second and third gates for controlling the gate voltage of the first transistor so that the gate voltage is always off when the reverse voltage is applied.
Transistors.

[0007]

According to a first aspect of the present invention, there is provided an inter-power supply protection circuit comprising: a first NMOS transistor having a drain connected to a power supply line for operating power supply and a source connected to a power supply line for grounding; Connect to the power line for grounding,
A second NMOS transistor having a drain connected to a power supply line for operating power and a source connected to the gate of the first transistor.
And an NMOS third transistor having a gate connected to a power supply line for operating power supply, a source connected to a power supply line for grounding, and a drain connected to the gate of the first transistor.

According to this configuration, in the normal operation in which the operating voltage is applied to the power supply line for the operating power supply and the ground voltage is applied to the power supply line for grounding, the second transistor is turned off and the third transistor is turned off. Is turned on, and the first transistor is turned off. Further, when a ground voltage is applied to the power supply line for the operation power supply and a reverse voltage is applied to the power supply line for ground, the second transistor is turned on.
The third transistor is turned off, and the first transistor is turned off. Thus, the first power supply line connected between the power supply lines
Are turned off even when a reverse voltage is applied, and a large current can be prevented from flowing.

According to a second aspect of the present invention, there is provided an inter-power supply protection circuit comprising: an NMOS first transistor having a drain connected to an operation power supply line and a source connected to a ground power supply line; And a second transistor of a PMOS having a drain connected to the gate of the first transistor, a gate and a drain connected to a power supply line for grounding, and a source connected to the gate of the first transistor. And a third PMOS transistor.

According to this configuration, during normal operation, the second
Transistor is off, the third transistor is on,
The first transistor is off. When a reverse voltage is applied, the second transistor is turned on, the third transistor is turned off, and the first transistor is turned off. Thus, the first transistor connected between the power supply lines
It is turned off even when a reverse voltage is applied, so that a large current can be prevented from flowing. The protection circuit between power supplies according to claim 3,
An NMOS first transistor having a drain connected to a power supply line for operating power and a source connected to a power supply line for grounding; a gate and a source connected to a power supply line for operating power; a drain connected to the first transistor The second transistor of the PMOS connected to the gate of the first transistor, the gate of the second transistor connected to the power supply line for operating power, the source connected to the power supply line for ground, and the second transistor of the NMOS connected to the gate of the first transistor 3 transistors.

According to this configuration, during normal operation, the second
Transistor is off, the third transistor is on,
The first transistor is off. When a reverse voltage is applied, the second transistor is turned on, the third transistor is turned off, and the first transistor is turned off. Thus, the first transistor connected between the power supply lines
It is turned off even when a reverse voltage is applied, so that a large current can be prevented from flowing.

According to a fourth aspect of the present invention, in the power supply protection circuit, a first transistor of a PMOS having a source connected to a power supply line for an operation power supply and a drain connected to a power supply line for grounding, and a gate and a drain connected to an operation power supply NMOS transistor having a source connected to the gate of the first transistor, a gate and a source connected to the ground power supply line, and a drain connected to the gate of the first transistor. And a third NMOS transistor.

According to this configuration, during normal operation, the second
Transistor is on, the third transistor is off,
The first transistor is off. When a reverse voltage is applied, the second transistor is turned off, the third transistor is turned on, and the first transistor is turned off. Thus, the first transistor connected between the power supply lines
It is turned off even when a reverse voltage is applied, so that a large current can be prevented from flowing.

According to a fifth aspect of the present invention, there is provided an inter-power supply protection circuit, wherein a first transistor of a PMOS having a source connected to a power supply line for operating power supply and a drain connected to a power supply line for grounding, and a power supply for grounding the gate. A second transistor of a PMOS having a source connected to a power supply line for operating power supply, a drain connected to the gate of the first transistor, a gate connected to a power supply line for operating power supply, and a drain connected A PMOS third transistor connected to a power supply line for grounding and having a source connected to the gate of the first transistor.

According to this configuration, during normal operation, the second
Transistor is on, the third transistor is off,
The first transistor is off. When a reverse voltage is applied, the second transistor is turned off, the third transistor is turned on, and the first transistor is turned off. Thus, the first transistor connected between the power supply lines
It is turned off even when a reverse voltage is applied, so that a large current can be prevented from flowing.

According to a sixth aspect of the present invention, the power supply protection circuit includes a first PMOS transistor having a source connected to a power supply line for operating power supply and a drain connected to a power supply line for grounding, and a power supply for grounding a gate. A second transistor of a PMOS having a source connected to a power supply line for operating power supply, a drain connected to a gate of the first transistor, a gate and a source connected to a power supply line for grounding, And an NMOS third transistor connected to the gate of the first transistor.

According to this configuration, during normal operation, the second
Transistor is on, the third transistor is off,
The first transistor is off. When a reverse voltage is applied, the second transistor is turned off, the third transistor is turned on, and the first transistor is turned off. Thus, the first transistor connected between the power supply lines
It is turned off even when a reverse voltage is applied, so that a large current can be prevented from flowing.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. [First Embodiment] FIG. 1 is a block diagram of an inter-power supply protection circuit according to a first embodiment of the present invention. In FIG. 1, 1 is an NMOS transistor for protecting between power supplies (first transistor), 2 and 3 are NMOS transistors (second and third transistors) for controlling a gate voltage of the NMOS transistor 1 for protecting between power supplies, 4 is the operating voltage Vcc
And 5, a power supply line for operating power supply for applying the ground voltage and a power supply line for grounding for applying the ground voltage Vss.

The power supply protection circuit according to the first embodiment comprises an NMOS transistor 1 for power supply protection, and an NMO
NM that controls the gate voltage of S transistor 1
OS transistors 2 and 3 are provided. The NMOS transistor 1 has a drain connected to a power supply line 4 for operating power supply and a source connected to a power supply line 5 for grounding. The NMOS transistor 2 has a gate connected to the power supply line 5 for grounding, a drain connected to the power supply line 4 for operating power supply, and a source connected to the gate of the NMOS transistor 1. The NMOS transistor 3 has a gate connected to the power supply line 4 for operating power, a source connected to the power supply line 5 for ground, and a drain connected to the gate of the NMOS transistor 1.

The operation of the inter-power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the power supply line 4 for operating power supply and the ground voltage Vss is applied to the power supply line 5 for grounding, the NMOS transistor 2 is turned off.
Transistor 3 turns on, and thus NMOS transistor 1 turns off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 4 for operating power and the operating voltage Vcc is applied to the power supply line 5 for grounding, the NMOS transistor 2 is turned on and the NMOS transistor 2 is turned on.
Transistor 3 turns off, and thus NMOS transistor 1 turns off.

As described above, according to the present embodiment, the gate voltage of the NMOS transistor 1 for protection between power supplies connected between the power supply lines 4 and 5 is changed to the NMOS transistors 2 and
3, the NMOS transistor 1 can always be turned off during normal operation and when a reverse voltage is applied. As a result, a large current can be prevented from flowing through the NMOS transistor 1 when a reverse voltage is applied. .

[Second Embodiment] FIG. 2 shows a second embodiment of the present invention.
FIG. 3 is a configuration diagram of a power supply protection circuit according to the embodiment. In FIG. 2, 6 is an NMOS transistor (first transistor) for protection between power supplies, and 7 and 8 are NMOS transistors for protection between power supplies.
PMO controlling the gate voltage of transistor 6
S transistors (second and third transistors), 9 are power supply lines for operating power supply for applying operating voltage Vcc, and 10 are power supply lines for grounding for applying ground voltage Vss.

The power supply protection circuit according to the second embodiment includes an NMOS transistor 6 for protection between power supplies and an NMO
PM that controls the gate voltage of S transistor 6
OS transistors 7 and 8 are provided. The NMOS transistor 6 has a drain connected to a power supply line 9 for operating power supply, and a source connected to a power supply line 10 for grounding. The PMOS transistor 7 has a gate and a source connected to a power supply line 9 for operating power, and a drain connected to an NMO.
Connected to the gate of S transistor 6. The PMOS transistor 8 has a gate and a drain connected to the power supply line 10 for grounding, and a source connected to the NMOS transistor 6.
Connected to the gate.

The operation of the power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the power supply line 9 for operating power supply and the ground voltage Vss is applied to the power supply line 10 for grounding, the PMOS transistor 7 is turned off.
The S transistor 8 turns on, and the NMOS transistor 6 turns off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 9 for operating power supply and the operating voltage Vcc is applied to the power supply line 10 for grounding, the PMOS transistor 7 is turned on and PM
The OS transistor 8 is turned off, so that the NMOS transistor
The transistor 6 is turned off.

As described above, according to the present embodiment, the gate voltage of the NMOS transistor 6 for protecting the power supply connected between the power supply lines 9 and 10 is controlled by the PMOS transistors 7 and 8 so that the NMOS transistor 6 Can be always turned off both during normal operation and when a reverse voltage is applied, and as a result, a large current can be prevented from flowing through the NMOS transistor 6 when a reverse voltage is applied.

[Third Embodiment] FIG. 3 shows a third embodiment of the present invention.
FIG. 3 is a configuration diagram of a power supply protection circuit according to the embodiment. In FIG. 3, reference numeral 11 denotes an NMOS transistor for protecting between power supplies (first transistor), reference numerals 12 and 13 denote a PMOS transistor (second transistor) for controlling a gate voltage of the NMOS transistor 11 for protecting power supply, and N
MOS transistors (third transistors), 14 are power supply lines for operating power supply for applying the operating voltage Vcc, and 15 are power supply lines for grounding for applying the ground voltage Vss.

The power supply protection circuit according to the third embodiment includes an NMOS transistor 11 for power supply protection and an NM
A PMOS transistor 12 and an NMOS transistor 13 for controlling the gate voltage of the OS transistor 11 are provided. The NMOS transistor 11 has a drain connected to a power supply line 14 for operating power supply and a source connected to a power supply line 15 for grounding. The PMOS transistor 12 has a gate and a source connected to a power supply line 14 for operating power, and a drain connected to the gate of the NMOS transistor 11. The NMOS transistor 13 has a gate connected to a power supply line 14 for operating power, a source connected to a power supply line 15 for ground, and a drain connected to the gate of the NMOS transistor 11.

The operation of the inter-power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the power supply line 14 for operating power supply and the ground voltage Vss is applied to the power supply line 15 for grounding, the PMOS transistor 12 is turned off.
MOS transistor 13 is turned on, so that NM
The OS transistor 11 turns off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 14 for operation power supply and the operation voltage Vcc is applied to the power supply line 15 for ground supply, the PMOS transistor 12
Is turned on, the NMOS transistor 13 is turned off, and the NMOS transistor 11 is turned off.

As described above, according to the present embodiment, the NMOS for protection between power supplies connected between the power supply lines 14 and 15 is provided.
The gate voltage of the transistor 11 is controlled by the PMOS transistor 12 and the NMOS transistor 13 so that the NMOS transistor 11 can be always turned off both during normal operation and when a reverse voltage is applied. As a result, when the reverse voltage is applied, the NMOS transistor 11 is turned off. 11 can be prevented from flowing a large current.

[Fourth Embodiment] FIG. 4 shows a fourth embodiment of the present invention.
FIG. 3 is a configuration diagram of a power supply protection circuit according to the embodiment. In FIG. 4, reference numeral 16 denotes a PMOS transistor (first transistor) for protection between power supplies, reference numerals 17 and 18 denote NMOS transistors (second and third transistors) for controlling the gate voltage of the PMOS transistor 16 for protection between power supplies, Reference numeral 19 denotes a power supply line for operating power supply for applying the operation voltage Vcc, and reference numeral 20 denotes a power supply line for ground for applying the ground voltage Vss.

The power supply protection circuit of the fourth embodiment comprises a PMOS transistor 16 for protection between power supplies,
NMOS transistors 17 and 18 for controlling the gate voltage of the OS transistor 16 are provided. PM
The OS transistor 16 has a drain connected to a power supply line 19 for operating power supply and a source connected to a power supply line 20 for grounding.
Connected to The NMOS transistor 17 has a gate and a drain connected to a power supply line 19 for operating power, and a source connected to the gate of the PMOS transistor 16. The NMOS transistor 18 has a gate and a source connected to the power supply line 20 for grounding, and a drain connected to the gate of the PMOS transistor 16.

The operation of the inter-power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the power supply line 19 for operating power supply and the ground voltage Vss is applied to the power supply line 20 for grounding, the NMOS transistor 17 is turned on.
The MOS transistor 18 is turned off, so that PM
The OS transistor 16 is turned off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 19 for operating power supply and the operating voltage Vcc is applied to the power supply line 20 for grounding, the NMOS transistor 17
Is turned off, the NMOS transistor 18 is turned on, and the PMOS transistor 16 is turned off.

As described above, according to the present embodiment, the PMOS for protection between power supplies connected between the power supply lines 19 and 20 is provided.
The gate voltage of the transistor 16 is controlled by the NMOS transistors 17 and 18 so that the PMOS transistor 16 can be always turned off both during the normal operation and when the reverse voltage is applied.
A large current can be prevented from flowing through the OS transistor 16.

[Fifth Embodiment] FIG. 5 shows a fifth embodiment of the present invention.
FIG. 3 is a configuration diagram of a power supply protection circuit according to the embodiment. In FIG. 5, 21 is a PMOS transistor for protecting between power supplies (first transistor), 22 and 23 are PMOS transistors (second and third transistors) for controlling a gate voltage of the PMOS transistor 21 for protecting between power supplies, Reference numeral 24 denotes a power supply line for operating power supply for applying the operating voltage Vcc, and reference numeral 25 denotes a power supply line for grounding for applying the ground voltage Vss.

The power supply protection circuit according to the fifth embodiment includes a PMOS transistor 21 for power supply protection, a PM transistor
PMOS transistors 22 and 23 for controlling the gate voltage of the OS transistor 21 are provided. PM
The OS transistor 22 has a gate connected to a power supply line 25 for grounding, a source connected to a power supply line 24 for operating power supply, and a drain connected to the gate of the PMOS transistor 21. The PMOS transistor 23 has a gate connected to a power supply line 24 for operating power, a drain connected to a power supply line 25 for ground, and a source connected to the gate of the PMOS transistor 21.

The operation of the power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the operating power supply power supply line 24 and the ground voltage Vss is applied to the grounding power supply line 25, the PMOS transistor 22 is turned on.
The MOS transistor 23 is turned off, so that PM
The OS transistor 21 is turned off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 24 for operating power and the operating voltage Vcc is applied to the power supply line 25 for grounding, the PMOS transistor 22
Is turned off, the PMOS transistor 23 is turned on, and the PMOS transistor 21 is turned off.

As described above, according to the present embodiment, the PMOS for protection between power supplies connected between the power supply lines 24 and 25 is provided.
The gate voltage of the transistor 21 is controlled by the PMOS transistors 22 and 23, so that the PMOS transistor 21 can be always turned off both during normal operation and when a reverse voltage is applied.
A large current can be prevented from flowing through the OS transistor 21.

[Sixth Embodiment] FIG. 6 shows a sixth embodiment of the present invention.
FIG. 3 is a configuration diagram of a power supply protection circuit according to the embodiment. In FIG. 6, reference numeral 26 denotes a PMOS transistor for protecting between power supplies (first transistor), 27 and 28 denote PMOS transistors (second transistor) for controlling the gate voltage of the PMOS transistor 26 for protecting power supply, and N
MOS transistor (third transistor), 29 is a power supply line for operating power supply for applying operating voltage Vcc, and 30 is a power supply line for grounding for applying ground voltage Vss.

The power supply protection circuit according to the sixth embodiment includes a PMOS transistor 26 for power supply protection,
A PMOS transistor 27 and an NMOS transistor 28 for controlling the gate voltage of the OS transistor 26 are provided. The PMOS transistor 27 has a gate connected to a power supply line 30 for grounding, a source connected to a power supply line 29 for operating power supply, and a drain connected to a PMOS power supply line 29.
Connected to the gate of transistor 26. The NMOS transistor 28 has a gate and a source connected to the power supply line 30 for grounding, and a drain connected to the gate of the PMOS transistor 26.

The operation of the power supply protection circuit configured as described above will be described below. During normal operation, that is, when the operating voltage Vcc is applied to the power supply line 29 for operating power supply and the ground voltage Vss is applied to the power supply line 30 for grounding, the PMOS transistor 27 is turned on.
MOS transistor 28 is turned off, and therefore PM transistor
The OS transistor 26 is turned off. When a reverse voltage is applied, that is, when the ground voltage Vss is applied to the power supply line 29 for operation power and the operation voltage Vcc is applied to the power supply line 30 for ground, the PMOS transistor 27
Is turned off, the NMOS transistor 28 is turned on, and the PMOS transistor 26 is turned off.

As described above, according to the present embodiment, the PMOS for protecting the power supply connected between the power supply lines 29 and 30 is provided.
The gate voltage of the transistor 26 is controlled by the PMOS transistor 27 and the NMOS transistor 28 so that the PMOS transistor 26 can be always turned off both during normal operation and when a reverse voltage is applied. As a result, when the reverse voltage is applied, the PMOS transistor 26 is turned off. 26 can be prevented from flowing a large current.

[0042]

As described above, the present invention provides the second and third embodiments.
By controlling the gate voltage of the first transistor connected between the power supply lines by the transistor, the first transistor can be always turned off both during normal operation and when a reverse voltage is applied. As a result, the reverse voltage A large current can be prevented from flowing through the first transistor at the time of application.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a protection circuit between power supplies according to a first embodiment of the present invention.

FIG. 2 is a configuration diagram of an inter-power supply protection circuit according to a second embodiment of this invention.

FIG. 3 is a configuration diagram of a power supply protection circuit according to a third embodiment of the present invention.

FIG. 4 is a configuration diagram of a protection circuit between power supplies according to a fourth embodiment of the present invention.

FIG. 5 is a configuration diagram of an inter-power supply protection circuit according to a fifth embodiment of the present invention.

FIG. 6 is a configuration diagram of a protection circuit between power supplies according to a sixth embodiment of the present invention.

FIG. 7 is a configuration diagram of a conventional power supply protection circuit.

[Explanation of symbols]

1 NMOS transistor (first transistor) for protection between power supplies 2 NMOS transistor (second transistor) 3 NMOS transistor (third transistor) 4 power supply line for operation power supply 5 power supply line for grounding 6 protection for power supply NMOS transistor (first transistor) 7 PMOS transistor (second transistor) 8 PMOS transistor (third transistor) 9 power supply line for operating power supply 10 power supply line for grounding 11 NMOS transistor for power supply protection (first 1 transistor) 12 PMOS transistor (second transistor) 13 NMOS transistor (third transistor) 14 power supply line for operating power supply 15 grounding power supply line 16 PMOS transistor (first transistor) 1 for protection between power supplies 1 NMOS transistor (second transistor) 18 NMOS transistor (third transistor) 19 power supply line for operating power supply 20 power supply line for grounding 21 PMOS transistor for protection between power supplies (first transistor) 22 PMOS transistor (secondary transistor) 23 PMOS transistor (third transistor) 24 Power supply line for operating power supply 25 Grounding power supply line 26 PMOS transistor for protection between power supplies (first transistor) 27 PMOS transistor (second transistor) 28 NMOS Transistor (third transistor) 29 Power supply line for operating power supply 30 Power supply line for grounding

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 19/00 19/003

Claims (6)

[Claims] 1. An NMOS having a drain connected to a power supply line for operating power supply and a source connected to a power supply line for grounding.
A second transistor of an NMOS having a gate connected to the power supply line for grounding, a drain connected to a power supply line for operating power, and a source connected to the gate of the first transistor. A power supply comprising: an NMOS third transistor having a gate connected to the power supply line for operating power, a source connected to the power supply line for grounding, and a drain connected to the gate of the first transistor. Protection circuit. 2. An NMOS having a drain connected to a power supply line for operating power supply and a source connected to a power supply line for grounding.
A second transistor of a PMOS having a gate and a source connected to a power supply line for the operation power supply, and a drain connected to a gate of the first transistor; and a gate and a drain connected to the ground for the ground. A power supply protection circuit comprising: a PMOS third transistor connected to a power supply line and having a source connected to the gate of the first transistor. 3. An NMOS having a drain connected to a power supply line for operating power supply and a source connected to a power supply line for grounding.
A second transistor of a PMOS having a gate and a source connected to a power supply line for the operation power supply, and a drain connected to a gate of the first transistor; a power supply for the operation power supply An NMOS third transistor having a source connected to the ground, a source connected to the power supply line for grounding, and a drain connected to the gate of the first transistor. 4. A PMOS having a source connected to a power supply line for operating power supply and a drain connected to a power supply line for grounding.
A second transistor of NMOS having a gate and a drain connected to the power supply line for the operation power supply, and a source connected to the gate of the first transistor; and a gate and a source for the ground. An NMOS third transistor connected to a power supply line and having a drain connected to the gate of the first transistor; 5. A PMOS having a source connected to a power supply line for operating power supply and a drain connected to a power supply line for grounding.
And a second transistor of a PMOS having a gate connected to the power supply line for grounding, a source connected to a power supply line for the operation power supply, and a drain connected to the gate of the first transistor. And a third transistor of a PMOS having a gate connected to the power supply line for the operation power supply, a drain connected to the power supply line for grounding, and a source connected to the gate of the first transistor. Protection circuit. 6. A PMOS having a source connected to a power supply line for operating power supply and a drain connected to a power supply line for grounding.
And a second transistor of a PMOS having a gate connected to the power supply line for grounding, a source connected to a power supply line for the operation power supply, and a drain connected to the gate of the first transistor. And an NMOS third transistor having a gate and a source connected to the ground power supply line and a drain connected to the gate of the first transistor.