JPH10214944A - Method for manufacturing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent separation of a Pt layer of a lower electrode from a barrier layer (TiN layer) by a method wherein, after the barrier layer and lower electrode are sequentially formed, they are heat treated in the nitrogen or inactive gas atmosphere, and an interface between the barrier layer and lower electrode is alloyed, and thereafter a ferroelectric film is formed on the lower electrode. SOLUTION: After switching transistors 11 are coated with an interlayer insulation film 2, surfaces of the interlayer insulation film 2 and a polysilicon plug 3 are flatted and a TiN film serving as a barrier layer 7 is formed using a sputter method, and a TiN/Ti film is formed, and continuously a Pt film is deposited to form a lower electrode. Next, they are heat-treated (annealed) in the inactive gas atmosphere of nitrogen, argon and the like, and a Pt/TiN/Ti lamination film is alloyed to form lamination films 5a, 6a. Further, after a PZT7 film is formed using a sol-gel method and crystallized, an insulation film 8 is deposited and a contact hole is formed on an upper part of a ferroelectric film. Thereafter, a Pt upper electrode 13 is formed. A film separation is hard to occur.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device using a ferroelectric thin film or a high dielectric thin film.

[0002]

2. Description of the Related Art In recent years, semiconductor devices such as DRAMs and DSRAMs using a high dielectric thin film having a higher dielectric constant than a silicon oxide film and a ferroelectric thin film having spontaneous polarization have been actively studied. Most of these dielectric thin films are oxides, and require high-temperature heat treatment during formation. Therefore, from the viewpoint of heat resistance and oxidation resistance, P is used as a base electrode material.
A metal film containing t as a main component is used as a lower electrode.

The Pt or a metal film containing Pt, for example, P
a metal film containing t as a main component (such as an alloy of Pt and Rh)
In order to electrically connect to the silicon semiconductor region, Pt or Pb or Bi contained in the dielectric film is diffused into a conductive material or silicon, and is connected to the silicon semiconductor region by heat treatment when forming the dielectric film. In order to prevent oxidation of the conductive material, a high melting point metal such as TiN or Ta or a metal film containing a high melting point metal, for example, a metal film containing a high melting point metal as a main component is required. It is used as a laminated structure of a Ti film and each high melting point metal film for avoiding poor conduction.

Hereinafter, a manufacturing process of a conventional semiconductor memory device having a high dielectric thin film or a ferroelectric thin film will be described with reference to FIG.

First, as shown in FIG. 2A, after a switching transistor 11 is formed by a MOSFET forming step and covered with an interlayer insulating film 2, only a portion where a bit line contacts an impurity diffusion region 12 of a substrate is known. A contact hole 4 is formed by using a photolithography method and a dry etching method, and polysilicon in which impurities are diffused is buried. Then, the surface of the interlayer insulating film and the surface of the polysilicon plug 3 are planarized by a known CMP method.

Next, as shown in FIG. 2B, a Ti film having a thickness of 300 to 500 ° is formed on the polysilicon plug by using a DC magnetron sputtering method, and is further formed by a magnetron reactive sputtering method. 2000N TiN
By forming a film, a TiN / Ti film 5 is formed. Subsequently, a Pt film 6 having a thickness of 1000 ° is deposited by using a DC magnetron sputtering method to form a lower electrode.

Further, a 0.20 μm PZT film 7 is formed by using a sol-gel method. This PZT film 7 first has a 2-
Using methoxyethanol as a solvent, lead acetate, titanium (I
V) Isopropoxide and zirconium isopropoxide are respectively dissolved so that Pb: Ti: Zr = 100: 52: 48 to obtain a sol-gel stock solution, and the stock solution is applied using a spinner at a rotation speed of 3000 rpm. .

Next, after drying in the air at 150 ° C. for 10 minutes, and further in the air for 30 minutes,
Temporary sintering is performed at 400 ° C. for 30 minutes in the air. After this 6
The PZT film 7 is crystallized in a mixed atmosphere of nitrogen and oxygen (flow ratio N ₂ : O ₂ = 4: 1) at 00 to 650 ° C. for 30 minutes.
Next, the PZT / Pt / TiN / Ti layer is formed by a known photolithography method and a dry etching method as shown in FIG.
The shape was as shown in FIG.

Next, as shown in FIG. 2C, TiO for preventing a reaction between the PZT film 7 and the silicon oxide film 9 is formed.
Or the like is deposited by a known sputtering method, then a silicon oxide film 9 is deposited by a known CVD method, and a known photolithography method and a dry etching method are formed on the ferroelectric film. Form a contact hole. After that, a Pt upper electrode 13 is formed as shown in FIG.

[0010]

In the semiconductor memory device shown in FIG. 2D having no adhesion layer of Ti or the like, TiN is used in a crystallization step of a ferroelectric film in a mixed atmosphere of nitrogen and oxygen.
Stress is applied to oxidize the surface of the TiN layer with oxygen or cause plastic deformation of the TiN layer. As a result, film peeling occurs between Pt and TiN, which makes it difficult to measure the characteristics of the ferroelectric film.

In order to prevent the separation between Pt and TiN, there is a technique of forming an adhesion layer 14 between the Pt layer 6 of the lower electrode and the TiN layer forming the barrier layer 7, as shown in FIG. . When such an adhesion layer 14 of Ti or the like is used,
Although the adhesion layer is oxidized in the crystallization step, peeling of the film can be prevented.

However, there is a problem that the resistance is increased due to the oxidation of the adhesion layer, and the characteristics cannot be measured.

FIG. 2 is a view showing a process of forming a semiconductor memory device having a first conventional ferroelectric film or high dielectric film, and FIG. 3 is a view showing a second conventional ferroelectric film or high dielectric film. FIG. 3 is a cross-sectional view of a semiconductor memory device having a dielectric film. 2 and 3, reference numeral 1 denotes a semiconductor substrate, and reference numeral 10 denotes an element isolation portion.

[0014]

According to a first aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: forming a transistor and a capacitor having a high dielectric film or a ferroelectric film from platinum or an alloy containing platinum as a main component. A lower electrode formed of a conductive material and a barrier layer made of a high melting point metal or a high melting point metal compound, the barrier layer and the lower electrode are sequentially formed. After that, heat treatment is performed in a nitrogen or inert gas atmosphere to alloy the interface between the barrier layer and the lower electrode, and then form the high dielectric film or the ferroelectric film on the lower electrode. It is a feature.

According to a second aspect of the present invention, in the method of manufacturing a semiconductor device, the barrier layer comprises a titanium nitride film,
2. The method according to claim 1, wherein the heat treatment is performed in a nitrogen atmosphere.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one embodiment.

FIG. 1 is a diagram showing a manufacturing process of a semiconductor device according to an embodiment of the present invention. In FIG. 1, reference numeral 10 denotes an element isolation portion.

Hereinafter, a manufacturing process of a semiconductor memory device having a high dielectric thin film or a ferroelectric thin film according to an embodiment of the present invention will be described with reference to FIG.

First, as shown in FIG. 1A, after the switching transistor 11 is formed by the MOSFET forming step and covered with the interlayer insulating film 2, only the portion where the bit line contacts the impurity diffusion region 12 of the semiconductor substrate 1 is formed. A contact hole 4 is formed by using a known photolithography method and a dry etching method, and polysilicon in which impurities are diffused is buried. Then, the surfaces of the interlayer insulating film 2 and the polysilicon plug 3 are planarized by a known CMP method. .

Next, as shown in FIG. 1B, a Ti film having a thickness of 300 to 500 ° is formed on the polysilicon plug 3 by using a DC magnetron sputtering method, and further a film is formed by a magnetron reactive sputtering method. By forming a TiN film to be a barrier layer having a thickness of 2000 °, TiN / T
An i film is formed. Here, the TiN layer constituting the barrier layer is composed of oxygen and nitrogen, which are gases at the time of heat treatment, and P, which is a lower electrode.
At the same time, it works to prevent diffusion of Pb or the like contained in the dielectric film into the polysilicon plug 3.

Subsequently, a Pt film having a thickness of 1000 ° is deposited by using a DC magnetron sputtering method to form a lower electrode.

Next, the Pt / TiN / Ti laminated film is alloyed by subjecting it to a heat treatment at a temperature of 500 to 600 ° C. in an atmosphere of an inert gas such as nitrogen or argon to cause eutectic and plastic change. A) forming the laminated films 5a and 6b;
Since the Pt film is formed by the magnetron reactive sputtering after raising the wafer temperature to 450 to 500 ° C.
It is not necessary to perform the heat treatment after the film formation at 500 ° C. or lower. If the heat treatment temperature is too high (for example, 650)
° C), depending on the film formation conditions of the TiN film, a problem that the TiN film is cracked may occur. Therefore, in order to obtain desired characteristics of the semiconductor device having the ferroelectric film, it is necessary to perform heat treatment at 500 to 600 ° C. is there. Also, when a TiN film is used for the barrier layer, if heat treatment is performed in a nitrogen atmosphere, unreacted Ti in the TiN film reacts with nitrogen, and the degree of nitridation of TiN is improved. Can be.

Further, a 0.20 μm PZT film 7 is formed by using a sol-gel method. This PZT film 7 first has a 2-
Using methoxyethanol as a solvent, lead acetate, titanium (I
V) Isopropoxide and zirconium isopropoxide are respectively dissolved so that Pb: Ti: Zr = 100: 52: 48 to obtain a sol-gel stock solution, and the stock solution is applied using a spinner at a rotation speed of 3000 rpm. .

Next, after drying at 150 ° C. in the air for 10 minutes, and further drying in the air for 30 minutes,
Temporary sintering is performed at 400 ° C. for 30 minutes in the air. After this 6
The PZT film is crystallized in a mixed atmosphere of nitrogen and oxygen (flow rate ratio N ₂ : O ₂ = 4: 1) at 00 to 650 ° C. for 30 minutes. Next, the PZT / Pt / TiN / Ti layer is formed by a known photolithography method and a dry etching method as shown in FIG.
The shape was as shown in FIG.

Next, as shown in FIG. 1C, TiO for preventing a reaction between the PZT film 7 and the silicon oxide film 9 is formed.
Or the like is deposited by a known sputtering method, then a silicon oxide film 9 is deposited by a known CVD method, and a known photolithography method and a dry etching method are formed on the ferroelectric film. Form a contact hole. Thereafter, a Pt upper electrode 13 is formed as shown in FIG.

A comparison between the semiconductor device formed by the above process and the conventional semiconductor device shows that in the prior art without annealing, the film peeled off, whereas the film peeled off in a nitrogen atmosphere.
0 ° C, 30 minutes annealing, 600 ° C, 30 minutes in the same atmosphere
In the present invention in which annealing was performed for a minute, film peeling did not occur.

In the case where Ta (tantalum) is used for the barrier layer, Ta may be plastically deformed in the heat treatment step for crystallization of the PZT film in a mixed atmosphere of nitrogen and oxygen, or Ta may be used.
After forming the Pt electrode serving as the lower electrode, a heat treatment at 500 to 600 ° C. may be performed in a nitrogen atmosphere so that the Pt and Ta films do not peel off due to the eutectic at the interface between Pt and Ta. Since Ta is easily oxidized, it is oxidized during the crystallization of the PZT film. However, since Ta has a characteristic that it has conductivity even if oxidized, there is no problem in measuring the characteristics of the ferroelectric film. .

[0028]

As described above in detail, by using the present invention, the peeling of the film between Pt and TiN, which is a problem in the semiconductor device manufacturing process, can be prevented without using the adhesion layer, Since the dielectric thin film and the high dielectric thin film can be formed without generating cracks, the characteristics of the ferroelectric film and the high dielectric film can be measured.

According to the second aspect of the present invention, the quality of the TiN film constituting the barrier layer can be improved by annealing for eutectic formation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an apparatus for manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a view showing a process of forming a semiconductor memory device having a first conventional ferroelectric film or high-dielectric film.

FIG. 3 is a cross-sectional view of a semiconductor memory device having a second conventional ferroelectric film or high-dielectric film.

[Explanation of symbols]

 Reference Signs List 1 semiconductor substrate 2 interlayer insulating film 3 polysilicon plug 4 contact hole 5 TiN / Ti film 5a TiN / Ti film alloyed with Pt 6 Pt film 6a Pt film alloyed with TiN 7 PZT film 8 insulating film 9 silicon Oxide film 10 Element isolation portion 11 Switching transistor 12 Impurity diffusion region 13 Upper electrode of capacitor

Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (2)

[Claims] A high-melting-point metal or a high-melting-point metal comprising a transistor and a capacitor having a high-dielectric film or a ferroelectric film, wherein a lower electrode made of platinum or an alloy containing platinum as a main component is formed of a plug made of a conductive material. In a method for manufacturing a semiconductor device electrically connected via a barrier layer made of a compound, after sequentially forming the barrier layer and the lower electrode, a heat treatment is performed in an atmosphere of nitrogen or an inert gas, and A method for manufacturing a semiconductor device, comprising: alloying an interface with a lower electrode; and thereafter, forming the high dielectric film or the ferroelectric film on the lower electrode. 2. The method according to claim 1, wherein said barrier layer is made of a titanium nitride film, and said heat treatment is performed in a nitrogen atmosphere.