JPH10209561A - Semiconductor laser device - Google Patents
Semiconductor laser deviceInfo
- Publication number
- JPH10209561A JPH10209561A JP1094897A JP1094897A JPH10209561A JP H10209561 A JPH10209561 A JP H10209561A JP 1094897 A JP1094897 A JP 1094897A JP 1094897 A JP1094897 A JP 1094897A JP H10209561 A JPH10209561 A JP H10209561A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor
- carrier concentration
- conductivity type
- grown
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
- 239000004065 semiconductor Substances 0.000 title claims description 43
- 239000000758 substrate Substances 0.000 claims description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 8
- 230000000903 blocking effect Effects 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 5
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005253 cladding Methods 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 239000000969 carrier Substances 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 238000000034 method Methods 0.000 description 2
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- Semiconductor Lasers (AREA)
Abstract
(57)【要約】
【課題】リーク電流を低減した低閾値埋込ヘテロレーザ
を提供する。
【解決手段】変曲点の無い滑らかな側面形状を持つメサ
ストライプを形成し、最初にｐ型ＩｎＰ層を埋め込み成
長し、次に成長するｎ型ＩｎＰ層（ｎ−ＩｎＰ電流ブロ
ック層）を、第１及び、第１のキャリア濃度よりも大き
い第２のキャリア濃度の層からなり、この順序で成長す
る２層構造とし、その後、埋め込むｐ型ＩｎＰ層のキャ
リア濃度を第２のキャリア濃度以上とし、さらにｎ型Ｉ
ｎＰ層で埋め込む。
(57) Abstract: A low-threshold buried heterolaser with reduced leakage current is provided. A mesa stripe having a smooth side surface shape without an inflection point is formed, a p-type InP layer is first buried and grown, and then an n-type InP layer (n-InP current block layer) to be grown is formed. It has a two-layer structure consisting of a first and a second carrier concentration layer higher than the first carrier concentration and grown in this order, and then the carrier concentration of the p-type InP layer to be embedded is set to be equal to or higher than the second carrier concentration. , And n-type I
It is embedded with an nP layer.
Description
【０００１】[0001]
【発明の属する技術分野】本発明は半導体レーザに関す
る。[0001] The present invention relates to a semiconductor laser.
【０００２】[0002]
【従来の技術】半導体レーザの低閾値化を達成するため
には、活性領域以外を流れるリーク電流の低減が必須で
ある。埋込ヘテロ（ＢＨ；Buried Heterostructure）構
造レーザでは、従来電流ブロック層としてｐ−ｎ接合や
高抵抗半導体層（Ｆｅ及びＴｉドープ等）が用いられて
おり、ｐ基板を用いたＢＨレーザの例は、エレクトロニ
クス・レターズ ２８巻 ナンバー１９ １９９２年
１８４４頁(ElectronicsLetters Vol.28 No.19 1992 p.
1844）に記載のように、有機金属気相成長（ＭＯＣＶ
Ｄ；Metalorganic Chemical Vapor Deposition）法によ
るｐ−ｎ接合埋込型のＢＨレーザがある。2. Description of the Related Art In order to lower the threshold value of a semiconductor laser, it is essential to reduce leakage current flowing in areas other than the active region. In a buried heterostructure (BH) laser, a pn junction or a high-resistance semiconductor layer (Fe and Ti doping) is conventionally used as a current blocking layer. An example of a BH laser using a p substrate is as follows. , Electronics Letters, Volume 28, Number 19, 1992
1844 (Electronics Letters Vol. 28 No. 19 1992 p.
1844), metal organic chemical vapor deposition (MOCV)
D: Metal organic Chemical Vapor Deposition) method, there is a pn junction buried BH laser.
【０００３】[0003]
【発明が解決しようとする課題】従来技術でｐ−ｎ接合
埋込によるＢＨレーザを作製すると、図２に示すように
ｎ型ＩｎＰ埋込層６とｎ型ＩｎＰ層９，１０がつながり
易く（ｎ−ｎ接続ができ易く）、電流がこのｎ−ｎ接続
を通じて流れるため充分な低閾値化ができない。When a BH laser with a pn junction is buried in the prior art, the n-type InP buried layer 6 and the n-type InP layers 9 and 10 are easily connected as shown in FIG. nn connection is easily formed), and a current cannot be reduced sufficiently because the current flows through the nn connection.
【０００４】本発明の目的は、このようなｎ−ｎ接続の
無い低リーク電流埋込構造を達成することにより、ＢＨ
レーザの低閾値化を図ることにある。An object of the present invention is to achieve a low leakage current buried structure without such an nn connection, thereby achieving a BH
The object is to reduce the threshold of the laser.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するため
の手段を、図１により説明する。変曲点の無い滑らかな
側面形状を持つメサストライプを形成し、その埋込成長
で最初にＺｎドープｐ型ＩｎＰ層５を、次にＳｉドープ
ｎ型ＩｎＰ層６，７（ｎ−ＩｎＰ電流ブロック層），Ｚ
ｎドープｐ型ＩｎＰ層８，Ｓｉドープｎ型ＩｎＰ層９を
連続して成長する。これらの層のキャリア濃度の大きさ
は、ｎ型ＩｎＰ層６＜ｎ型ＩｎＰ層７＜ｐ型ＩｎＰ層８
とする。Means for achieving the above object will be described with reference to FIG. A mesa stripe having a smooth side surface shape without an inflection point is formed. In the buried growth, a Zn-doped p-type InP layer 5 is first formed, and then a Si-doped n-type InP layer 6, 7 (n-InP current block) is formed. Layer), Z
An n-doped p-type InP layer 8 and a Si-doped n-type InP layer 9 are continuously grown. The carrier concentration of these layers is such that n-type InP layer 6 <n-type InP layer 7 <p-type InP layer 8
And
【０００６】この時、図１（ａ）に示すように、最初に
成長したｐ型ＩｎＰ層５によって結晶成長速度の遅い結
晶面が完全に形成されず、次に成長するｎ型ＩｎＰ層の
成長初期にその成長フロントがメサ最上部に達してしま
う場合がある。その場合でも、ｎ型ＩｎＰ層６，７のキ
ャリア濃度がｐ型ＩｎＰ層８よりも小さいために、図１
（ｂ）に示すように、ｐ型ＩｎＰ層８からのＺｎの拡散
によりｎ型ＩｎＰ層６，７上部のキャリアが相殺され
て、メサ最上部に達した成長フロント部は有効な電流リ
ーク経路とはならない。At this time, as shown in FIG. 1A, the crystal plane having a low crystal growth rate is not completely formed by the p-type InP layer 5 which has been grown first, and the growth of the n-type InP layer to be grown next. Initially, the growth front may reach the top of the mesa. Even in that case, since the carrier concentration of the n-type InP layers 6 and 7 is lower than that of the p-type InP layer 8, the structure shown in FIG.
As shown in (b), the carriers on the n-type InP layers 6 and 7 are offset by the diffusion of Zn from the p-type InP layer 8, and the growth front part reaching the top of the mesa becomes an effective current leakage path. Not be.
【０００７】すると、ｎ−ＩｎＰ電流ブロック層１７
（Ｓｉドープｎ型ＩｎＰ層６，７からＺｎが拡散したＩ
ｎＰ層１６を除いた部分）は、後にこの上方に成長する
ｎ型ＩｎＰ層９又は１０と分離された構造となる。Then, the n-InP current blocking layer 17
(I where Zn is diffused from Si-doped n-type InP layers 6 and 7)
The portion excluding the nP layer 16) has a structure that is separated from the n-type InP layer 9 or 10 which grows above the portion later.
【０００８】このような構造では、メサストライプの活
性領域以外を流れるリーク電流は効果的に抑止され、低
閾値半導体レーザが実現できる。With such a structure, a leak current flowing in areas other than the active region of the mesa stripe is effectively suppressed, and a low threshold semiconductor laser can be realized.
【０００９】[0009]
【発明の実施の形態】本発明をＩｎＧａＡｓＰ系ＢＨレ
ーザに適用した場合について、図１，図３により説明す
る。DESCRIPTION OF THE PREFERRED EMBODIMENTS A case where the present invention is applied to an InGaAsP-based BH laser will be described with reference to FIGS.
【００１０】有機金属気相成長（ＭＯＣＶＤ）法によ
り、ｐ−ＩｎＰ基板１（キャリア濃度４〜６Ｅ１８cm
~2）にｐ−ＩｎＰクラッド層２（キャリア濃度〜１Ｅ１
８cm~2，厚さ〜２μｍ）を成長した後InGaAsP／InGaAs
ＭＱＷ活性層３（波長１.３μｍ，厚さ〜０.２μｍ
）、ｎ−ＩｎＰクラッド層４（キャリア濃度〜２Ｅ１
８cm~2，厚さ〜１μｍ）を成長する。この時活性層３は
InGaAsP バルク活性層でも良く、ＭＱＷ構造に限定され
ない。A p-InP substrate 1 (carrier concentration of 4 to 6E18 cm) is formed by metal organic chemical vapor deposition (MOCVD).
~ 2 ) in the p-InP cladding layer 2 (carrier concentration ~ 1E1)
After growing 8cm ~ 2 , thickness ~ 2μm), InGaAsP / InGaAs
MQW active layer 3 (wavelength: 1.3 μm, thickness: 0.2 μm
), N-InP cladding layer 4 (carrier concentration ２2E1)
8cm ~ 2 , thickness ~ 1μm). At this time, the active layer 3
An InGaAsP bulk active layer may be used and is not limited to the MQW structure.
【００１１】その後、ＣＶＤ法によりＳｉＯ2 膜１５を
被着し、ホトリソグラフィー工程を経た後、ＳｉＯ2 膜
１５をマスクとしてウェットエッチングにより図３に示
されるような変曲点の無い滑らかな側面を有するメサス
トライプを形成する。メサストライプはＳｉＯ2膜１５
下部が側面からエッチングされ、ＳｉＯ2１５膜がオー
バーハング状になるようにする。また活性層幅は１〜２
μｍ、メサ深さは２.５〜４μｍである。After that, a SiO 2 film 15 is deposited by the CVD method, and after a photolithography process, a smooth side surface having no inflection point as shown in FIG. 3 is formed by wet etching using the SiO 2 film 15 as a mask. A mesa stripe is formed. Mesa stripe is SiO 2 film 15
The lower portion is etched from the side so that the SiO 2 15 film becomes overhanging. The width of the active layer is 1-2.
μm and the mesa depth is 2.5-4 μm.
【００１２】次にＭＯＣＶＤ法により、ＳｉＯ2 膜１５
を被着したままメサストライプの側面を、Ｚｎドープｐ
−ＩｎＰ層５（キャリア濃度〜１Ｅ１８cm~2，厚さ０.
５ 〜１μｍ），Ｓｉドープｎ−ＩｎＰ層６（キャリア
濃度〜１.５Ｅ１８cm~2 ，厚さ０.２〜０.５μｍ），Ｓ
ｉドープｎ−ＩｎＰ層７（キャリア濃度〜２Ｅ１８cm
~2，厚さ０.５ 〜１μｍ）で埋め込む。Next, the SiO 2 film 15 is formed by MOCVD.
While the side surface of the mesa stripe is
-InP layer 5 (carrier concentration ~1E18cm ~ 2, a thickness of 0.
5 to 1 μm), Si-doped n-InP layer 6 (carrier concentration: 1.5E18 cm 2 , thickness: 0.2 to 0.5 μm), S
i-doped n-InP layer 7 (carrier concentration ２2E18 cm)
2 and a thickness of 0.5 to 1 μm).
【００１３】その後Ｚｎドープｐ−ＩｎＰ層８（キャリ
ア濃度２Ｅ１８cm~2以上，厚さ１〜３μｍ），Ｓｉドー
プｎ−ＩｎＰ層９（キャリア濃度〜２Ｅ１８cm~2，厚さ
〜０.５μｍ ）を成長し、メサストライプを埋め込ん
だ。ｎ−ＩｎＰ層９はｐ−ｎ接合と再成長界面を分離す
るために設けたもので、本発明では特に挿入を限定され
るものではない。Thereafter, a Zn-doped p-InP layer 8 (carrier concentration of 2E18 cm to 2 or more, thickness of 1 to 3 μm) and a Si-doped n-InP layer 9 (carrier concentration of 2E18 cm to 2 and thickness of 0.5 μm) are grown. And embedded a mesa stripe. The n-InP layer 9 is provided for separating the pn junction and the regrowth interface, and the insertion is not particularly limited in the present invention.
【００１４】次に、ＳｉＯ2 膜を除去した後ｎ−ＩｎＰ
層１０（キャリア濃度〜２Ｅ１８cm~2，厚さ〜２μ
ｍ），ｎ−ＩｎＧａＡｓＰキャップ層１１（キャリア濃
度５Ｅ１８cm~2以上，厚さ〜０.２μｍ ）で平坦に埋め
込んだ。Next, after removing the SiO 2 film, the n-InP
Layer 10 (carrier concentration ~ 2E18cm ~ 2 , thickness ~ 2μ)
m), n-InGaAsP cap layer 11 (carrier concentration 5E18 cm ~ 2 or more, they flatly embedded in thick ~0.2μm).
【００１５】以上のようにして埋め込んだ構造では、図
１(ａ)に示すように、最初に成長したｐ型ＩｎＰ層５に
よって結晶成長速度の遅い結晶面が完全に形成されず、
次に成長するｎ型ＩｎＰ層の成長初期にその成長フロン
トがメサ最上部に達してしまう場合がある。その場合で
も、ｎ型ＩｎＰ層６，７のキャリア濃度がｐ型ＩｎＰ層
８よりも小さいために、図１（ｂ）に示すように、ｐ型
ＩｎＰ層８からのＺｎの拡散によりｎ型ＩｎＰ層６，７
上部のキャリアが相殺されて、メサ最上部に達した成長
フロント部は有効な電流リーク経路とはならない。In the structure buried as described above, as shown in FIG. 1A, a crystal plane having a low crystal growth rate is not completely formed by the p-type InP layer 5 grown first.
The growth front of the n-type InP layer to be grown next may reach the top of the mesa in the early stage of growth. Even in this case, since the carrier concentration of the n-type InP layers 6 and 7 is lower than that of the p-type InP layer 8, the diffusion of Zn from the p-type InP layer 8 as shown in FIG. Layer 6, 7
The growth front that reaches the top of the mesa due to the offset of the upper carriers does not provide an effective current leakage path.
【００１６】すると、ｎ−ＩｎＰ電流ブロック層１７
（Ｓｉドープｎ型ＩｎＰ層６，７からＺｎが拡散したＩ
ｎＰ層１６を除いた部分）は、後にこの上方に成長する
ｎ型ＩｎＰ層９又は１０と分離された構造となる。そし
てこのような構造では、メサストライプの活性領域以外
を流れるリーク電流は効果的に抑止され、低閾値半導体
レーザが実現できる。Then, the n-InP current blocking layer 17
(I where Zn is diffused from Si-doped n-type InP layers 6 and 7)
The portion excluding the nP layer 16) has a structure that is separated from the n-type InP layer 9 or 10 which grows above the portion later. In such a structure, a leak current flowing in areas other than the active region of the mesa stripe is effectively suppressed, and a low-threshold semiconductor laser can be realized.
【００１７】その後ＳｉＯ2 膜１２で電流狭窄を行った
後ｎ電極１３を形成、更に基板側を研磨してトータル膜
厚１００μｍ程度にした後ｐ電極１４を蒸着により形成
し、素子化を行った。After that, the current was confined by the SiO 2 film 12, the n-electrode 13 was formed, the substrate side was polished to a total film thickness of about 100 μm, and the p-electrode 14 was formed by vapor deposition to form an element. .
【００１８】本実施例によるＢＨレーザでは、発振波長
１.３μｍ ，閾電流値１０〜１２ｍＡ，スロ−プ効率
０.３ｍＷ／ｍＡ の素子が高歩留りで得られ、低リーク
電流で且つ低閾値の半導体レーザが実現できた。In the BH laser according to the present embodiment, an element having an oscillation wavelength of 1.3 μm, a threshold current value of 10 to 12 mA, and a slope efficiency of 0.3 mW / mA can be obtained at a high yield, a low leakage current and a low threshold voltage. A semiconductor laser has been realized.
【００１９】本実施例では半導体レーザへの適用につい
て説明したが、本発明は半導体レーザに限らず電流狭窄
を行う必要のある他のデバイスについても適用可能であ
る。In this embodiment, the application to a semiconductor laser has been described. However, the present invention is not limited to a semiconductor laser, but can be applied to other devices that need to perform current confinement.
【００２０】[0020]
【発明の効果】本発明のように、変曲点の無い滑らかな
側面形状を持つメサストライプをｐ−ｎ接合により埋め
込む構造で、ｎ−ＩｎＰ電流ブロック層を、第１及び、
第１のキャリア濃度よりも大きい第２のキャリア濃度の
層からなり、この順序で成長する２層構造とし、その後
埋め込むｐ型ＩｎＰ層のキャリア濃度を上記第２のキャ
リア濃度以上とすれば、ブロック層の成長フロントがメ
サ最上部に達してしまった場合でも、この部分のキャリ
アはその上に成長するｐ型ＩｎＰ層からのＺｎの拡散に
より相殺される。そのため、ｎ−ｎ接続が排除でき、リ
ーク電流が小さく、活性領域へ効率的に電流注入を行う
低閾値の素子が得られる。According to the present invention, a mesa stripe having a smooth side surface shape without an inflection point is buried by a pn junction, and an n-InP current blocking layer is formed by first and second n-InP current blocking layers.
A layer having a second carrier concentration higher than the first carrier concentration and having a two-layer structure grown in this order, and then having a carrier concentration of the p-type InP layer to be buried being equal to or higher than the second carrier concentration, a block is formed. Even if the growth front of the layer reaches the top of the mesa, the carriers in this area are offset by the diffusion of Zn from the overlying p-type InP layer. Therefore, an n-n connection can be eliminated, a leak current is small, and a low-threshold element that efficiently injects current into the active region can be obtained.
【図１】本発明の一実施例を示す半導体レーザの断面
図。FIG. 1 is a sectional view of a semiconductor laser showing one embodiment of the present invention.
【図２】従来例を示す半導体レーザの断面図。FIG. 2 is a sectional view of a semiconductor laser showing a conventional example.
【図３】本発明の一実施例の要部の説明図。FIG. 3 is an explanatory diagram of a main part of one embodiment of the present invention.
１…ｐ−ＩｎＰ基板、２…ｐ−ＩｎＰクラッド層、３…
ＭＱＷ活性層、４…ｎ−ＩｎＰクラッド層、５…ｐ−Ｉ
ｎＰ層、６…ｎ−ＩｎＰ層、７…Ｚｎ拡散ｐ−ＩｎＰ
層、８…ｐ−ＩｎＰ層、９…ｎ−ＩｎＰ層、１０…ｎ−
ＩｎＰ層、１１…ｎ−ＩｎＧａＡｓＰキャップ層、１２
…ＳｉＯ2 膜、１３…ｎ電極、１４…ｐ電極、１５…Ｓ
ｉＯ2 膜、１６…Ｚｎ拡散ＩｎＰ層、１７…ｎ−ＩｎＰ
電流ブロック層。1 ... p-InP substrate, 2 ... p-InP cladding layer, 3 ...
MQW active layer, 4 ... n-InP cladding layer, 5 ... pI
nP layer, 6 ... n-InP layer, 7 ... Zn diffusion p-InP
Layer, 8 ... p-InP layer, 9 ... n-InP layer, 10 ... n-
InP layer, 11... N-InGaAsP cap layer, 12
... SiO 2 film, 13 ... n electrode, 14 ... p electrode, 15 ... S
iO 2 film, 16 ... Zn diffusion InP layer, 17 ... n-InP
Current block layer.
Claims (4)
成し、上記多層構造を、側面が変曲点の無い滑らかな曲
面であるメサストライプ状に加工し、メサ側面を第１導
電型の半導体層及び第２導電型の半導体層を含む半導体
多層膜で埋め込む半導体装置において、最初に上記第１
導電型の半導体層を埋め込み成長し、次に成長する上記
第２導電型の半導体層を、第１及び第２のキャリア濃度
の層からなる２層構造とし、その後さらに第１導電型及
び第２導電型の半導体層により埋め込むことを特徴とす
る半導体レーザ装置。1. A multi-layered structure including an active layer is formed on a semiconductor substrate, and the multi-layered structure is processed into a mesa stripe shape having a smooth curved surface with no inflection point, and the mesa side surface is formed of a first conductivity type. A semiconductor device embedded with a semiconductor multilayer film including a semiconductor layer of a second conductivity type and a semiconductor layer of a second conductivity type.
The conductive type semiconductor layer is buried and grown, and the second conductive type semiconductor layer to be grown next has a two-layer structure including first and second carrier concentration layers. A semiconductor laser device embedded with a conductive semiconductor layer.
成し、該多層構造を、側面が変曲点の無い滑らかな曲面
であるメサストライプ状に加工し、メサ側面を第１導電
型の半導体層及び第２導電型の半導体層を含む半導体多
層膜で埋め込む半導体装置において、最初に第１導電型
の半導体層を埋め込み成長し、次に成長する第２導電型
の半導体層を、第１及び、第１のキャリア濃度よりも大
きい第２のキャリア濃度の層からなり、この順序で成長
する２層構造とし、その後、さらに上記第１導電型及び
上記第２導電型の半導体層により埋め込むことを特徴と
する半導体レーザ装置。2. A multi-layer structure including an active layer is formed on a semiconductor substrate, and the multi-layer structure is processed into a mesa stripe shape having a smooth curved surface with no inflection points. In the semiconductor device embedded with the semiconductor multilayer film including the semiconductor layer of the second conductivity type and the semiconductor layer of the second conductivity type, the semiconductor layer of the first conductivity type is first embedded and grown, and then the semiconductor layer of the second conductivity type is 1 and a layer having a second carrier concentration higher than the first carrier concentration, and has a two-layer structure grown in this order. Thereafter, the layer is further buried with the semiconductor layers of the first conductivity type and the second conductivity type. A semiconductor laser device characterized by the above-mentioned.
成し、該多層構造を、側面が変曲点の無い滑らかな曲面
であるメサストライプ状に加工し、メサ側面を第１導電
型の半導体層及び第２導電型の半導体層を含む半導体多
層膜で埋め込む半導体装置において、最初に第１導電型
の半導体層を埋め込み成長し、次に成長する第２導電型
の半導体層を、第１及び、第１のキャリア濃度よりも大
きい第２のキャリア濃度の層からなり、この順序で成長
する２層構造とし、その後埋め込む上記第１導電型の半
導体層のキャリア濃度を上記第２のキャリア濃度以上と
し、その後さらに上記第２導電型の半導体層により埋め
込むことを特徴とする半導体レーザ装置。3. A multi-layer structure including an active layer is formed on a semiconductor substrate, and the multi-layer structure is processed into a mesa stripe shape having a smooth curved surface with no inflection point, and the mesa side surface is formed of a first conductivity type. In the semiconductor device embedded with the semiconductor multilayer film including the semiconductor layer of the second conductivity type and the semiconductor layer of the second conductivity type, the semiconductor layer of the first conductivity type is first embedded and grown, and then the semiconductor layer of the second conductivity type is 1 and a layer having a second carrier concentration higher than the first carrier concentration, and has a two-layer structure grown in this order, and thereafter, the carrier concentration of the semiconductor layer of the first conductivity type to be embedded is adjusted to the second carrier concentration. A semiconductor laser device having a concentration equal to or higher than that of the first semiconductor layer and then burying the semiconductor layer with the second conductivity type semiconductor layer.
を形成し、該多層構造を、側面が変曲点の無い滑らかな
曲面であるメサストライプ状に加工し、メサ側面をＺｎ
ドープｐ型ＩｎＰ層及びＳｉドープｎ型ＩｎＰ層で埋め
込む半導体装置において、最初にｐ型ＩｎＰ層を埋め込
み成長し、次に成長するｎ型ＩｎＰ層を、第１及び、第
１のキャリア濃度よりも大きい第２のキャリア濃度の層
からなり、この順序で成長する２層構造とし、その後、
埋め込むｐ型ＩｎＰ層のキャリア濃度を上記第２のキャ
リア濃度以上とし、その後、さらにｎ型ＩｎＰ層で埋め
込むことを特徴とする半導体レーザ装置。4. A multi-layer structure including an active layer is formed on a p-type InP substrate, and the multi-layer structure is processed into a mesa stripe shape having a smooth curved surface without an inflection point, and a mesa side surface formed of Zn.
In a semiconductor device embedded with a doped p-type InP layer and a Si-doped n-type InP layer, a p-type InP layer is first buried and grown, and then the n-type InP layer to be grown has a first carrier concentration lower than the first carrier concentration. A two-layer structure consisting of a layer having a large second carrier concentration and growing in this order;
A semiconductor laser device wherein the carrier concentration of a p-type InP layer to be buried is set to be equal to or higher than the second carrier concentration, and then the n-type InP layer is further buried.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01094897A JP3877823B2 (en) | 1997-01-24 | 1997-01-24 | Semiconductor laser device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP01094897A JP3877823B2 (en) | 1997-01-24 | 1997-01-24 | Semiconductor laser device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10209561A true JPH10209561A (en) | 1998-08-07 |
| JP3877823B2 JP3877823B2 (en) | 2007-02-07 |
Family
ID=11764432
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP01094897A Expired - Fee Related JP3877823B2 (en) | 1997-01-24 | 1997-01-24 | Semiconductor laser device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3877823B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115023869A (en) * | 2020-01-28 | 2022-09-06 | 三菱电机株式会社 | Optical semiconductor device and method of manufacturing the same |
-
1997
- 1997-01-24 JP JP01094897A patent/JP3877823B2/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN115023869A (en) * | 2020-01-28 | 2022-09-06 | 三菱电机株式会社 | Optical semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3877823B2 (en) | 2007-02-07 |
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