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JPH10199934A - Semiconductor element mounting structure and semiconductor element mounting method - Google Patents

Semiconductor element mounting structure and semiconductor element mounting method

Info

Publication number
JPH10199934A
JPH10199934A JP364697A JP364697A JPH10199934A JP H10199934 A JPH10199934 A JP H10199934A JP 364697 A JP364697 A JP 364697A JP 364697 A JP364697 A JP 364697A JP H10199934 A JPH10199934 A JP H10199934A
Authority
JP
Japan
Prior art keywords
semiconductor element
circuit board
electrodes
conductive film
anisotropic conductive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP364697A
Other languages
Japanese (ja)
Inventor
Masaaki Okunaka
正昭 奥中
Yoshio Ozeki
良雄 大関
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP364697A priority Critical patent/JPH10199934A/en
Publication of JPH10199934A publication Critical patent/JPH10199934A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector

Landscapes

  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】半導体素子の電極パッドに金バンプを形成する
ことなく、異方性導電フィルムを用いたフリップチップ
アタッチ実装方式を実現してコスト低減をはかった半導
体素子実装構造体および半導体素子実装方法を提供する
ことにある。 【解決手段】半導体素子1を異方性導電フィルム3によ
り回路基板2に実装したフリップチップアタッチ方式の
半導体素子実装構造体において、前記半導体素子1をバ
ンプが形成されていない電極15を並設して構成し、前
記半導体素子と対向する回路基板上の実装面領域におい
て突起状の接続パッド部11、12、13を前記各電極
に対向する位置に並設し、該各突起状の接続パッド部1
1、12、13と前記各電極15の間を前記異方性導電
フィルムに内在する導電粒子10で接続して構成したこ
とを特徴とする。
(57) Abstract: A semiconductor element mounting structure which realizes a flip chip attach mounting method using an anisotropic conductive film without forming a gold bump on an electrode pad of a semiconductor element to reduce cost. And a semiconductor element mounting method. In a flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, an electrode on which no bump is formed is arranged on the semiconductor element. In the mounting surface area on the circuit board facing the semiconductor element, the protruding connection pad portions 11, 12, and 13 are juxtaposed at positions facing the respective electrodes, and the respective protruding connection pad portions are provided. 1
It is characterized in that the electrodes 1, 12, 13 and the respective electrodes 15 are connected by conductive particles 10 inherent in the anisotropic conductive film.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、異方性導電フィル
ムを用いたフリップチップアタッチ方式で半導体素子を
回路基板に接続実装した半導体素子実装構造体および半
導体素子実装方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor element mounting structure in which a semiconductor element is connected and mounted on a circuit board by a flip chip attachment method using an anisotropic conductive film, and a semiconductor element mounting method.

【0002】[0002]

【従来の技術】民生機器、特にノ−トパソコン、携帯電
話、PHS、PDAなどの携帯情報端末機器においては
高密度実装の必要性が益々高くなっている。これに対応
すべくこれらの機器における半導体素子の実装は、従来
のパッケ−ジ半導体実装から、半導体素子を直接基板に
実装する、いわゆるベアチップ実装方式が主流になりつ
つある。また、機器の小形化にともない、カメラ、ム−
ビの例からわかるように実装部材の種類、組合せ、組立
て、が複雑になり基板としてフレキシブルプリント基板
も多用されている。製品の高機能化、高密度実装化に対
応するために、このフレキシブルプリント基板にも半導
体素子を実装する必要のある場合も多くなっている。
2. Description of the Related Art Consumer equipment, especially portable information terminal equipment such as notebook personal computers, portable telephones, PHSs, PDAs, etc., is increasingly required to have high-density mounting. In order to cope with this, the so-called bare chip mounting system, in which the semiconductor element is directly mounted on a substrate, is becoming the mainstream from the conventional package semiconductor mounting for mounting the semiconductor element in these devices. Also, with the miniaturization of equipment, cameras,
As can be seen from the example, the type, combination, and assembling of the mounting members become complicated, and a flexible printed board is often used as a board. In many cases, it is necessary to mount a semiconductor element also on this flexible printed circuit board in order to cope with higher functionality and higher density mounting of products.

【0003】従来のベアチップ実装方法は、(1)半導
体チップ21をフェースアップで回路基板22に接着
し、半導体チップ21と回路基板22のパッド間を金線
23で接続し、さらにポッティング樹脂24で封止する
方法(図12に示す。)と、(2)はんだ、導電性接着
剤、異方性導電フィルムなどを接続材料とし、チップを
フェ−スダウンで回路基板に接続接着する方法(フリッ
プチップアタッチ方式)とがある。
The conventional bare chip mounting method is as follows: (1) A semiconductor chip 21 is adhered to a circuit board 22 face up, a pad between the semiconductor chip 21 and a pad of the circuit board 22 is connected by a gold wire 23, and a potting resin 24 is used. A method of sealing (shown in FIG. 12) and a method of (2) connecting a chip to a circuit board face-down by using solder, a conductive adhesive, an anisotropic conductive film or the like as a connection material (flip chip) Attach method).

【0004】前者の方法はチップの面積以外にワイヤボ
ンディング用のパッド面積が必要であるのに比べ、後者
の方法は回路基板22の必要搭載面積はチップサイズの
みであり、究極の高密度実装方式であると考えられ、下
記のようなフリップチップアタッチ方式が提案されてい
る。
The former method requires a pad area for wire bonding in addition to the chip area, whereas the latter method requires only the chip area for the mounting area of the circuit board 22. The following flip-chip attach method has been proposed.

【0005】(2−1)はんだ方式:半導体チップ21
のアルミ電極25上にバリアメタル26を形成し、回路
基板22と半導体チップ21とをはんだ27で接続す
る。次いで半導体チップ21と回路基板22との隙間に
樹脂28を充填硬化する(図13に示す。)。
(2-1) Soldering method: semiconductor chip 21
A barrier metal 26 is formed on the aluminum electrode 25 of the above, and the circuit board 22 and the semiconductor chip 21 are connected by solder 27. Next, a resin 28 is filled in the gap between the semiconductor chip 21 and the circuit board 22 and hardened (shown in FIG. 13).

【0006】(2−2)導電性接着剤方式:半導体チッ
プ21のアルミ電極25上にワイヤバンプ方式で金バン
プ29を形成する。つぎに、金バンプ29の先端に導電
性接着剤30を塗布し回路基板22に接着する。最後に
半導体チップ21と回路基板22との隙間に樹脂28を
充填硬化する(図14に示す。)。
(2-2) Conductive adhesive method: A gold bump 29 is formed on an aluminum electrode 25 of a semiconductor chip 21 by a wire bump method. Next, a conductive adhesive 30 is applied to the tip of the gold bump 29 and adhered to the circuit board 22. Finally, a resin 28 is filled in the gap between the semiconductor chip 21 and the circuit board 22 and hardened (as shown in FIG. 14).

【0007】(2−3)異方性導電フィルム方式:アル
ミ電極25上にワイヤバンプ方式、メッキ法などで金バ
ンプ29を形成した半導体チップ21と回路基板22と
を異方性導電フィルム31を介して加熱圧着する(図1
5に示す。)。
(2-3) Anisotropic conductive film method: A semiconductor chip 21 in which gold bumps 29 are formed on an aluminum electrode 25 by a wire bump method, a plating method or the like, and a circuit board 22 are interposed via an anisotropic conductive film 31. Thermocompression bonding (Fig. 1
It is shown in FIG. ).

【0008】以上のフリップチップアタッチ方式のう
ち、異方性導電フィルム方式は、工程数が少なく工完時
間が短い点で最も有利な方法である。
[0008] Among the above flip chip attach methods, the anisotropic conductive film method is the most advantageous method in that the number of steps is small and the completion time is short.

【0009】この異方性導電フィルム方式の接続組立図
を図16に示す。異方性導電フィルムを回路基板22の
接続端子部に貼り付ける。次に、ワイヤバンプ法、メッ
キ法などによりアルミ電極25上に金バンプ29を形成
した半導体チップ21を位置合わせ後、加熱ヘッドで半
導体チップ21を回路基板22に圧着する。この加熱圧
着により、チップの金バンプ電極29と回路基板の接続
パッドとが導電粒子を介して電気的に接続される。接続
部以外の導電粒子は圧力を受けないため元の分散状態を
保ったままであり隣接電極間の絶縁性が確保される。
FIG. 16 shows a connection assembly diagram of the anisotropic conductive film system. An anisotropic conductive film is attached to the connection terminal of the circuit board 22. Next, after positioning the semiconductor chip 21 having the gold bump 29 formed on the aluminum electrode 25 by a wire bump method, a plating method, or the like, the semiconductor chip 21 is pressure-bonded to the circuit board 22 by a heating head. By this heat compression bonding, the gold bump electrodes 29 of the chip and the connection pads of the circuit board are electrically connected via conductive particles. Since the conductive particles other than the connection portion do not receive the pressure, the original dispersion state is maintained and the insulation between the adjacent electrodes is secured.

【0010】[0010]

【発明が解決しようとする課題】上記したように、異方
性導電フィルムによる半導体素子のフリップチップアタ
ッチ実装方式は、工程数が少なくまた工完時間も短か
く、工業的に有利で実用性の高い方式である。しかしな
がら、従来の方法では半導体素子の電極パッドに金バン
プを形成する必要が生じ、コスト高になるという課題を
有していた。
As described above, the flip-chip attach mounting method of a semiconductor element using an anisotropic conductive film has a small number of steps and a short construction time, and is industrially advantageous and practical. It is a high method. However, in the conventional method, it is necessary to form a gold bump on the electrode pad of the semiconductor element, and there is a problem that the cost is increased.

【0011】本発明の目的は、上記課題を解決すべく、
半導体素子の電極パッドに金バンプを形成することな
く、異方性導電フィルムを用いたフリップチップアタッ
チ実装方式を実現してコスト低減をはかった半導体素子
実装構造体および半導体素子実装方法を提供することに
ある。
[0011] An object of the present invention is to solve the above problems.
Provided is a semiconductor element mounting structure and a semiconductor element mounting method which realize a flip chip attach mounting method using an anisotropic conductive film without forming a gold bump on an electrode pad of a semiconductor element and reduce cost. It is in.

【0012】[0012]

【課題を解決するための手段】上記目的を達成するため
に、本発明は、半導体素子を異方性導電フィルムにより
回路基板に実装したフリップチップアタッチ方式の半導
体素子実装構造体において、前記半導体素子をバンプが
形成されていない電極を複数並設して構成し、前記半導
体素子と対向する回路基板上の実装面領域において突起
状の接続パッド部を前記各電極に対向する位置に複数並
設し、該各突起状の接続パッド部と前記各電極の間を前
記異方性導電フィルムに内在する導電粒子で接続して構
成したことを特徴とする半導体素子実装構造体である。
In order to achieve the above object, the present invention relates to a flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film. Is formed by arranging a plurality of electrodes on which no bumps are formed, and a plurality of projecting connection pad portions are arranged in a position facing the respective electrodes in a mounting surface region on a circuit board facing the semiconductor element. A semiconductor element mounting structure, wherein each of the protruding connection pad portions and each of the electrodes are connected by conductive particles inherent in the anisotropic conductive film.

【0013】また本発明は、半導体素子を異方性導電フ
ィルムにより回路基板に実装したフリップチップアタッ
チ方式の半導体素子実装構造体において、前記半導体素
子をバンプが形成されていない電極を複数並設して構成
し、前記半導体素子と対向する回路基板上の実装面領域
において接続パッド部を前記各電極に対する間隙を狭め
て対向する位置に複数並設し、該各接続パッド部と前記
各電極の間を前記異方性導電フィルムに内在する導電粒
子で接続して構成したことを特徴とする半導体素子実装
構造体である。
Further, according to the present invention, in a flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, the semiconductor element is provided with a plurality of electrodes on which no bumps are formed. In the mounting surface area on the circuit board facing the semiconductor element, a plurality of connection pad portions are arranged in parallel at positions facing each other by narrowing a gap with respect to each of the electrodes, and between the connection pad portions and each of the electrodes. Are connected by conductive particles inherent in the anisotropic conductive film.

【0014】また本発明は、半導体素子を異方性導電フ
ィルムにより回路基板に実装したフリップチップアタッ
チ方式の半導体素子実装構造体において、前記半導体素
子をバンプが形成されていない電極を複数並設して構成
し、前記半導体素子と対向する回路基板上の実装面領域
において複数の配線パターンの各々に接続された突起状
の接続パッド部を前記各電極に対向する位置に複数並設
し、該各突起状の接続パッド部と前記各電極の間を前記
異方性導電フィルムに内在する導電粒子で接続して構成
したことを特徴とする半導体素子実装構造体である。
Further, according to the present invention, in a flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, the semiconductor element is provided with a plurality of electrodes on which no bumps are formed. In the mounting surface area on the circuit board facing the semiconductor element, a plurality of projecting connection pads connected to each of the plurality of wiring patterns are arranged in parallel at positions facing the respective electrodes. A semiconductor element mounting structure characterized in that a protruding connection pad portion and each of the electrodes are connected by conductive particles inherent in the anisotropic conductive film.

【0015】また本発明は、半導体素子を異方性導電フ
ィルムにより回路基板に実装したフリップチップアタッ
チ方式の半導体素子実装構造体において、前記半導体素
子をバンプが形成されていない電極を複数並設して構成
し、前記半導体素子と対向する回路基板上の実装領域に
おいて複数の配線パターンの各々に接続され、局部的に
変形させることによって突起した接続パッド部を前記各
電極に対向する位置に複数並設し、該各突起した接続パ
ッド部と前記各電極の間を前記異方性導電フィルムに内
在する導電粒子で接続して構成したことを特徴とする半
導体素子実装構造体である。
The present invention also provides a flip chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board using an anisotropic conductive film, wherein the semiconductor element is provided with a plurality of electrodes on which no bumps are formed. And a plurality of connection pad portions connected to each of the plurality of wiring patterns in a mounting region on the circuit board facing the semiconductor element and protruding by locally deforming the connection pads at positions facing the respective electrodes. A semiconductor element mounting structure, wherein each of the protruding connection pad portions and each of the electrodes are connected by conductive particles inherent in the anisotropic conductive film.

【0016】また本発明は、半導体素子を異方性導電フ
ィルムにより回路基板に実装したフリップチップアタッ
チ方式の半導体素子実装構造体において、前記半導体素
子をバンプが形成されていない電極を複数並設して構成
し、前記半導体素子と対向する回路基板上の実装領域に
おいて下層につながった接続パッド部のみを前記各電極
に対向する位置に複数並設し、該各接続パッド部と前記
各電極の間を前記異方性導電フィルムに内在する導電粒
子で接続して構成したことを特徴とする半導体素子実装
構造体である。
Further, according to the present invention, in a flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, the semiconductor element is provided with a plurality of electrodes on which no bumps are formed. In the mounting region on the circuit board facing the semiconductor element, only a plurality of connection pad portions connected to the lower layer are arranged in parallel at positions facing the respective electrodes, and between the respective connection pad portions and the respective electrodes. Are connected by conductive particles inherent in the anisotropic conductive film.

【0017】また本発明は、バンプを形成していない電
極を複数並設した半導体素子と、半導体素子の側に突起
状に変形した導体で形成された接続パッド部を前記各電
極と対向するように複数並設した回路基板とを異方性導
電フィルムを介して接続接着して構成したことを特徴と
する半導体素子実装構造体である。
Further, according to the present invention, a semiconductor element having a plurality of electrodes on which no bumps are formed and a connection pad portion formed of a conductor deformed in a protruding shape on the side of the semiconductor element face each of the electrodes. A semiconductor element mounting structure characterized in that a plurality of circuit boards arranged side by side are connected and bonded via an anisotropic conductive film.

【0018】また本発明は、フレキシブル回路基板に異
方性導電フィルムを貼付ける異方性導電フィルム貼付工
程と、該異方性導電フィルムを貼付けたフレキシブル回
路基板を、バンプを形成していない電極を複数並設した
半導体素子に対して位置合わせして搭載する搭載工程
と、該搭載工程で半導体素子に対して搭載されたフレキ
シブル回路基板に対して前記各電極の配置に対応して形
成された複数の突起を有する加熱ヘッドを押しつけるこ
とによってフレキシブル回路基板上に形成された導体を
突起状に変形させて複数の接続パッド部を形成して該各
接続パッド部と前記各電極との間を異方性導電フィルム
に内在する導電粒子で接続する加熱ヘッド押付工程とを
有することを特徴とする半導体素子実装方法である。
Further, the present invention provides a step of attaching an anisotropic conductive film to a flexible circuit board, and a step of attaching the flexible circuit board to which the anisotropic conductive film is attached to an electrode having no bump. A plurality of semiconductor elements arranged side by side are mounted in alignment with each other, and the flexible circuit board mounted on the semiconductor elements in the mounting step is formed in correspondence with the arrangement of the respective electrodes. By pressing a heating head having a plurality of projections, a conductor formed on the flexible circuit board is deformed into a projection shape to form a plurality of connection pad portions, and the difference between each connection pad portion and each of the electrodes is made. A heating head pressing step of connecting with conductive particles present in the isotropic conductive film.

【0019】また本発明は、バンプを形成していない電
極を複数並設した半導体素子に異方性導電フィルムを貼
付ける異方性導電フィルム貼付工程と、フレキシブル回
路基板を、前記異方性導電フィルムを貼付けた半導体素
子に対して位置合わせして搭載する搭載工程と、該搭載
工程で半導体素子に対して搭載されたフレキシブル回路
基板に対して前記各電極の配置に対応して形成された複
数の突起を有する加熱ヘッドを押しつけることによって
フレキシブル回路基板上に形成された導体を突起状に変
形させて複数の接続パッド部を形成して該各接続パッド
部と前記各電極との間を異方性導電フィルムに内在する
導電粒子で接続する加熱ヘッド押付工程とを有すること
を特徴とする半導体素子実装方法である。
The present invention also provides an anisotropic conductive film adhering step of adhering an anisotropic conductive film to a semiconductor element having a plurality of electrodes on which no bumps are formed, and a flexible circuit board, A mounting step of aligning and mounting the film on the semiconductor element, and a plurality of flexible circuit boards formed on the flexible circuit board mounted on the semiconductor element in the mounting step in correspondence with the arrangement of the electrodes. By pressing a heating head having protrusions, the conductor formed on the flexible circuit board is deformed into a protrusion shape to form a plurality of connection pad portions, and the connection pad portions and the electrodes are anisotropically. And a heating head pressing step of connecting with conductive particles existing in the conductive film.

【0020】また本発明は、バンプを形成していない電
極を複数並設した半導体素子と、導体からなる突起を有
する接続パッド部を複数並設した回路基板とを、異方性
導電フィルムで接続接着して構成したことを特徴とする
半導体素子実装構造体である。
Further, the present invention provides a method of connecting a semiconductor element having a plurality of electrodes on which no bumps are formed side by side and a circuit board having a plurality of connection pads having projections made of conductors by an anisotropic conductive film. A semiconductor element mounting structure characterized by being bonded.

【0021】また本発明は、前記半導体素子実装構造体
において、前記導体からなる突起を、導電性接着剤の硬
化物で形成したことを特徴とする。
Further, the present invention is characterized in that in the semiconductor element mounting structure, the projection made of the conductor is formed of a cured product of a conductive adhesive.

【0022】また本発明は、前記半導体素子実装構造体
において、前記導体からなる突起を、金属材料で形成し
たことを特徴とする。
Further, the present invention is characterized in that in the semiconductor element mounting structure, the projection made of the conductor is formed of a metal material.

【0023】また本発明は、バンプを形成していない電
極を複数並設した半導体素子と、ビアホール上に形成し
た接続パッド部を複数並設した回路基板とを、異方性導
電フィルムで接続接着して構成したことを特徴とする半
導体素子実装構造体である。
Further, according to the present invention, a semiconductor element having a plurality of electrodes having no bumps formed thereon and a circuit board having a plurality of connection pads formed on via holes are connected and bonded by an anisotropic conductive film. This is a semiconductor element mounting structure characterized by being configured as described above.

【0024】以上説明したように前記構成によれば、半
導体素子に並設された多数の電極上に金バンプを形成す
ることなく、半導体素子に並設された多数の電極の各々
と回路基板に前記電極に対応させて並設された接続パッ
ド部との間において主に圧力を受けるようにして異方性
導電フィルムに内在する導電粒子によって確実に圧着接
続して低抵抗で接続することができ、極めて低コストで
高信頼性を有する半導体ベアチップ実装を実現すること
ができる。即ち半導体素子が対向する実装面領域におけ
る電極と接続バッド部とが対向する接続部においてのみ
導電粒子が加圧され、この接続部以外の箇所において導
電粒子が加圧されないので、良好な低抵抗で接続するこ
とができる。
As described above, according to the above-described configuration, each of the plurality of electrodes arranged in parallel with the semiconductor element is formed on the circuit board without forming gold bumps on the plurality of electrodes arranged in parallel with the semiconductor element. The connection between the connection pads and the connection pads corresponding to the electrodes can be performed by applying pressure mainly by the conductive particles inherent in the anisotropic conductive film while receiving pressure mainly, thereby enabling connection with low resistance. Thus, it is possible to realize a semiconductor bare chip mounting with extremely low cost and high reliability. That is, the conductive particles are pressurized only at the connection portion where the electrode and the connection pad portion in the mounting surface region where the semiconductor element faces are opposed, and the conductive particles are not pressed at a portion other than this connection portion, so that good low resistance is obtained. Can be connected.

【0025】[0025]

【発明の実施形態】本発明に係るバンプを形成していな
い半導体素子(以下では、バンプレス半導体チップと記
す)を異方性導電フィルムを用いて回路基板にフリップ
チップアタッチ実装する方式(以下では、バンプレスの
フリップチップアタッチ実装方式と記す)の実施の形態
について図を用いて説明する。
BEST MODE FOR CARRYING OUT THE INVENTION A method of flip-chip attach-mounting a semiconductor device without bumps according to the present invention (hereinafter, referred to as a bumpless semiconductor chip) to a circuit board using an anisotropic conductive film (hereinafter, referred to as a bumpless semiconductor chip). An embodiment of the present invention will be described with reference to the drawings.

【0026】まず本発明に係る第1の実施の形態につい
て図1〜図7を用いて説明する。
First, a first embodiment according to the present invention will be described with reference to FIGS.

【0027】本第1の実施の形態は、フレキシブルプリ
ント基板とパッドレス半導体チップを異方性導電フィル
ムを介して加熱圧着する際に、加熱圧着ヘッドの先端部
に、パッドレス半導体チップの電極位置、サイズに対応
する突起を形成しておき、電極位置のみを印加してパッ
ドレス半導体チップをフレキシブルプリント基板に異方
性導電フィルムでベアチップ実装することである。
In the first embodiment, when the flexible printed circuit board and the padless semiconductor chip are thermocompression-bonded via an anisotropic conductive film, the electrode position of the padless semiconductor chip is located at the tip of the thermocompression bonding head. In this case, a projection corresponding to the size is formed, and only the electrode position is applied, and the padless semiconductor chip is mounted on a flexible printed board with a bare chip using an anisotropic conductive film.

【0028】図3には、本発明に係る第1の実施の形態
で用いる加熱圧着ヘッドの一実施の形態を示す斜視図で
ある。図4は、加熱圧着ヘッドに形成された突起を角形
に形成した場合を示す部分拡大図であり、図5は、加熱
圧着ヘッドに形成された突起を円形に形成した場合を示
す部分拡大図である。即ち、本発明に係る加熱圧着ヘッ
ド5の全体の大きさは、使用するバンプレス半導体チッ
プ(バンプレス半導体素子)1の大きさとほぼ同じか、
もしくは少し大きい程度に作られる。このヘッド5の先
端部には、バンプレス半導体チップ1に配置されたAl
等の電極15に対応して凸形状の突起4が必要数形成さ
れる。この突起4のサイズは、半バンプレス導体チップ
1の電極15のサイズより多少大きくても差し支えない
が、あまりにも大きい場合には接続に不具合が生じる。
従って、突起4のサイズは、バンプレス半導体チップ1
の電極15のサイズ以下であることが好ましい。突起4
の高さは、使用するフレキシブルプリント基板2aのト
ータルフィルム厚(ベース材、カバー材、銅箔配線パタ
ーン)により異なるが、一般的には0.003mm〜
0.3mm程度が好ましい。一方、突起4の高さが、使
用するフレキシブルプリント基板2aのトータルフィル
ム厚より厚くなると、加熱圧着ヘッド5とフレキシブル
プリント基板2aとが接触しなくなるため、熱が異方性
導電フィルム3に伝わらず、エポキシ樹脂が硬化しな
い。従って、加熱圧着ヘッド5に形成された突起4の高
さは、使用するフレキシブルプリント基板2aのトータ
ルフィルム厚以下とすることが好ましい。ヘッドの突起
4の形状についてはとくに制限はなく、図4に示す角形
4a、図5に示す円形4b、楕円形などから選択するこ
とができる。また、この突起4には必要に応じてテーパ
をつけることもできる。
FIG. 3 is a perspective view showing one embodiment of the thermocompression bonding head used in the first embodiment according to the present invention. FIG. 4 is a partially enlarged view showing a case where a protrusion formed on a thermocompression bonding head is formed in a square shape, and FIG. 5 is a partially enlarged view showing a case where a projection formed on a thermocompression bonding head is formed in a circular shape. is there. That is, the overall size of the thermocompression bonding head 5 according to the present invention is substantially the same as the size of the bumpless semiconductor chip (bumpless semiconductor element) 1 to be used,
Or made to a little bit larger. The tip of the head 5 is provided with Al disposed on the bumpless semiconductor chip 1.
The required number of protrusions 4 are formed corresponding to the electrodes 15 such as. The size of the projection 4 may be slightly larger than the size of the electrode 15 of the half bumpless conductor chip 1, but if it is too large, a connection failure occurs.
Accordingly, the size of the protrusion 4 is determined by the bumpless semiconductor chip 1.
It is preferable that the size is equal to or smaller than the size of the electrode 15. Protrusion 4
Varies depending on the total film thickness (base material, cover material, copper foil wiring pattern) of the flexible printed circuit board 2a to be used, but is generally from 0.003 mm to
It is preferably about 0.3 mm. On the other hand, if the height of the projections 4 is larger than the total film thickness of the flexible printed circuit board 2a to be used, the heating and pressing head 5 and the flexible printed circuit board 2a do not come into contact with each other, so that heat is not transmitted to the anisotropic conductive film 3. , The epoxy resin does not cure. Therefore, it is preferable that the height of the protrusions 4 formed on the thermocompression bonding head 5 be equal to or less than the total film thickness of the flexible printed circuit board 2a to be used. The shape of the projection 4 of the head is not particularly limited, and can be selected from a square 4a shown in FIG. 4, a circle 4b shown in FIG. In addition, the protrusion 4 can be tapered as required.

【0029】また加熱圧着ヘッド5における突起4はエ
ッチング法などにより容易に製作することができる。
The protrusions 4 in the thermocompression bonding head 5 can be easily manufactured by an etching method or the like.

【0030】次に、バンプレスのフリップチップアタッ
チ実装方式でバンプレス半導体チップ1を回路基板であ
るフレキシブルプリント基板2aに接続実装する方法に
ついて説明する。
Next, a method of connecting and mounting the bumpless semiconductor chip 1 to the flexible printed circuit board 2a which is a circuit board by the bumpless flip chip attach mounting method will be described.

【0031】フレキシブル基板2aは、フレキシブル基
材7上に配線パターン8が形成されて構成される。そし
て各配線パターン8の端部に接続パッド部が形成され
る。
The flexible substrate 2a is formed by forming a wiring pattern 8 on a flexible base material 7. Then, a connection pad portion is formed at an end of each wiring pattern 8.

【0032】異方性導電フィルム3は、未硬化のエポキ
シ樹脂9の中に導電粒子10を分散させたフィルムで形
成される。この導電粒子として、ニッケルなどの金属粒
子、または金メッキが施されたニッケルなどの金属粒
子、またはプラスチック粒子にニッケル皮膜及び金メッ
キ皮膜を形成した粒子等が多く用いられる。
The anisotropic conductive film 3 is formed of a film in which conductive particles 10 are dispersed in an uncured epoxy resin 9. As the conductive particles, metal particles such as nickel, metal particles such as nickel plated with gold, or particles obtained by forming a nickel film and a gold plating film on plastic particles are often used.

【0033】上記加熱圧着ヘッド5による加熱圧着条件
は、使用する異方性導電フィルム3により多少異なるが
約170〜200℃、約5〜20秒、約5〜400MP
a(突起24のセンタ部単位面積あたりの圧力)が好ま
しい。圧力が約5MPaより低い場合には、異方性導電
フィルム3の導電粒子が変形せず、良好な接続状態にな
らない場合がある。また、圧力が約400MPaより高
い場合には、バンプレス半導体チップ1を破壊する場合
がある。また、必要に応じて加熱圧着ヘッド5とフレキ
シブルプリント基板2aとの間に、シリコン樹脂、テフ
ロン樹脂、金属フィルム等のクッション材を挿入して圧
着する方法をとることもできる。
The conditions of the thermocompression bonding by the thermocompression bonding head 5 are slightly different depending on the anisotropic conductive film 3 to be used, but are about 170 to 200 ° C., about 5 to 20 seconds, about 5 to 400 MPa.
a (pressure per unit area of the center portion of the projection 24) is preferable. When the pressure is lower than about 5 MPa, the conductive particles of the anisotropic conductive film 3 may not be deformed and a good connection state may not be obtained. If the pressure is higher than about 400 MPa, the bumpless semiconductor chip 1 may be broken. If necessary, a method of inserting a cushion material such as a silicone resin, a Teflon resin, a metal film, or the like between the thermocompression bonding head 5 and the flexible printed circuit board 2a and performing compression bonding may be employed.

【0034】上記加熱圧着ヘッド5による加熱圧着方法
としては、次の2通りがあり、いずれの方法も採用可能
である。
There are the following two methods for the thermocompression bonding using the thermocompression head 5, and any of them can be adopted.

【0035】(a)図6に示すように、バンプレス半導
体チップ1に異方性導電フィルム3を貼付けておき、こ
れをフレキシブルプリント基板2aに搭載し、上記加熱
圧着ヘッド5を用いて加熱圧着する方法。
(A) As shown in FIG. 6, an anisotropic conductive film 3 is pasted on a bumpless semiconductor chip 1, mounted on a flexible printed circuit board 2a, and then thermocompression-bonded using the thermocompression head 5. how to.

【0036】(b)図7に示すように、フレキシブルプ
リント基板2aに異方性導電フィルム3を貼付けてお
き、これにバンプレス半導体チップ1を搭載し、上記加
熱圧着ヘッド5を用いて加熱圧着する方法。
(B) As shown in FIG. 7, the anisotropic conductive film 3 is pasted on the flexible printed board 2a, the bumpless semiconductor chip 1 is mounted thereon, and the thermocompression bonding head 5 is used for thermocompression bonding. how to.

【0037】図1には、上記加熱圧着ヘッド5による加
熱圧着状態を示す。図1に示すように、異方性導電フィ
ルム3をバンプレス半導体チップ1またはフレキシブル
プリント基板2aに貼付けておき、次に上記バンプレス
半導体チップ1を定盤6上に位置合わせ搭載し、次に、
突起4をAl等のチップ電極15に相当する位置に設け
た加熱圧着ヘッド5を用いて、フレキシブルプリント基
板2aの側からバンプレス半導体チップ1の側に、約1
70〜200℃、約5〜20秒、約5〜400MPaの
加熱圧着条件で加熱圧着すると、フレキシブルプリント
基板2a上のチップ電極15に対向する部分において突
起4の形状に倣って基材7と共に配線パターン(導体)
8の接続パッド部が突起状に変形し、この変形した突起
状の接続パッド部14とチップ電極15との間において
導電粒子10によって低い抵抗値で電気的に接続される
と共にエポキシ樹脂9が硬化されて実装されることにな
る。そして、この接続部以外の導電粒子は圧力を受けな
いため元の分散状態を保ったままであり、隣接電極間の
絶縁性について確保される。このようにして、図2に示
す半導体素子実装構造体を得ることができる。図2に示
すようにフレキシブルプリント基板2aが凹に変形した
構造となるが、実用上特に問題はない。
FIG. 1 shows a thermocompression bonding state by the thermocompression bonding head 5. As shown in FIG. 1, the anisotropic conductive film 3 is pasted on the bumpless semiconductor chip 1 or the flexible printed circuit board 2a, and then the bumpless semiconductor chip 1 is aligned and mounted on the surface plate 6, ,
Using a heating / compression bonding head 5 in which the projections 4 are provided at positions corresponding to the chip electrodes 15 of Al or the like, from the flexible printed board 2a side to the bumpless semiconductor chip 1 side, about 1
When thermocompression bonding is performed at 70 to 200 ° C. for about 5 to 20 seconds and about 5 to 400 MPa, wiring is performed together with the base member 7 in a portion facing the chip electrode 15 on the flexible printed circuit board 2 a according to the shape of the projection 4. Pattern (conductor)
The connection pad portion 8 is deformed into a protruding shape, and the deformed protruding connection pad portion 14 and the chip electrode 15 are electrically connected by the conductive particles 10 with a low resistance value and the epoxy resin 9 is cured. Will be implemented. Then, since the conductive particles other than the connection portion do not receive the pressure, the original dispersion state is maintained, and the insulation between the adjacent electrodes is ensured. Thus, the semiconductor element mounting structure shown in FIG. 2 can be obtained. As shown in FIG. 2, the flexible printed board 2a has a concavely deformed structure, but there is no practical problem.

【0038】次に、以上説明した第1の実施の形態につ
いて、更に具体的に実施例として説明する。
Next, the first embodiment described above will be described more specifically as an example.

【0039】[0039]

【実施例1】パッドレス半導体チップとして次に示す試
験チップを用いた。
Example 1 The following test chip was used as a padless semiconductor chip.

【0040】サイズ:8mm角 厚さ:0.45mm 接続パッドサイズ:0.105×105mm 接続パッドピッチ:0.13mm 接続配置:周辺4辺 フレキシブルプリント基板2aには、2層配線構造のフ
レキシブル基板(約0.075mm厚)を用いた。銅配
線は厚さ約0.035mmを使用した。チップ接続の配
線幅は約0.09mm、配線間の間隔は約0.04mm
とした。接続抵抗を4端子法で測定できるよう上記試験
チップ1及びフレキシブルプリント基板2aの配線を設
計した。
Size: 8 mm square Thickness: 0.45 mm Connection pad size: 0.105 × 105 mm Connection pad pitch: 0.13 mm Connection arrangement: 4 sides of the periphery The flexible printed board 2 a has a two-layer wiring structure flexible board ( (About 0.075 mm thick). The copper wiring used had a thickness of about 0.035 mm. The wiring width of chip connection is about 0.09mm, and the space between wirings is about 0.04mm
And The wiring of the test chip 1 and the flexible printed board 2a was designed so that the connection resistance could be measured by the four-terminal method.

【0041】フレキシブルプリント基板2aのチップ接
続領域に、0.2〜0.3μm程度の厚さの金メッキが
施された直径約0.008mmのニッケル導電粒子と未
硬化エポキシ樹脂と(配合割合は体積比で10:90〜
20:80程度)からなる異方性導電フィルム3を貼り
付けた。次に上記バッドレス半導体チップ1を位置合わ
せ搭載した。次に、約0.08mm角、高さ約0.07
5mmの突起4をチップ電極に相当する位置に設けた加
熱圧着ヘッド5を用いて、フレキシブルプリント基板の
側からチップの側に加熱加圧した。その結果配線パター
ン(導体)8の接続パッド部が突起状に変形し、この変
形した突起状の接続パッド部14とチップ電極15との
間において導電粒子10によって接続されると共にエポ
キシ樹脂9が硬化されて実装されることになる。圧着温
度は約200℃、時間は約20秒、突起4の先端部単位
面積あたりの圧力は約100MPaで行なった。接続端
子の接続抵抗は平均25mΩ程度であり十分に低い抵抗
値が得られた。
A gold-plated nickel conductive particle having a thickness of about 0.2 to 0.3 μm and a diameter of about 0.008 mm, and an uncured epoxy resin are applied to the chip connection area of the flexible printed circuit board 2 a (mixing ratio is volume 10: 90 ~
(Approximately 20:80). Next, the above-mentioned bad semiconductor chip 1 was aligned and mounted. Next, about 0.08 mm square, height about 0.07
Using a thermocompression bonding head 5 provided with a 5 mm projection 4 at a position corresponding to the chip electrode, heat was applied from the flexible printed circuit board side to the chip side. As a result, the connection pad portion of the wiring pattern (conductor) 8 is deformed into a protruding shape, and a connection is made between the deformed protruding connection pad portion 14 and the chip electrode 15 by the conductive particles 10 and the epoxy resin 9 is cured. Will be implemented. The crimping temperature was about 200 ° C., the time was about 20 seconds, and the pressure per unit area of the tip of the projection 4 was about 100 MPa. The connection resistance of the connection terminal was about 25 mΩ on average, and a sufficiently low resistance value was obtained.

【0042】[0042]

【実施例2】パッドレス半導体チップ1およびフレキシ
ブルプリント基板は、上記実施例1と同一の部材を用い
た。半導体チップの電極側の全面に、0.2〜0.3μ
m程度の厚さの金メッキを施した直径約0.008mm
のニッケル導電粒子と未硬化エポキシ樹脂と(導電粒子
と未硬化エポキシ樹脂との配合割合は体積比で10:9
0〜20:80程度)からなる異方性導電フィルム3を
貼り付けた。次に上記チップ1をフレキシブルプリント
基板2aに位置合わせ搭載した。次に、直径約0.08
mm、高さ約0.050mmの突起4をチップ電極に相
当する位置に設けた加熱圧着ヘッド5を用いて、フレキ
シブルプリント基板の側からチップの側に加熱加圧し
た。その結果配線パターン(導体)8の接続パッド部が
突起状に変形し、この変形した突起状の接続パッド部1
4とチップ電極15との間において導電粒子10によっ
て接続されると共にエポキシ樹脂9が硬化されて実装さ
れることになる。圧着温度は約200℃、時間は約20
秒、突起4の先端部単位面積あたりの圧力は約200M
Paで行なった。接続端子の接続抵抗は平均30mΩ程
度であり十分に低い抵抗値が得られた。
Example 2 The same members as those in Example 1 were used for the padless semiconductor chip 1 and the flexible printed circuit board. 0.2-0.3μ on the entire surface of the semiconductor chip on the electrode side
Approximately 0.008mm in diameter with gold plating of about m thickness
Nickel conductive particles and uncured epoxy resin (the mixing ratio of conductive particles and uncured epoxy resin is 10: 9 by volume ratio)
0-20: 80) was attached. Next, the chip 1 was aligned and mounted on the flexible printed circuit board 2a. Next, a diameter of about 0.08
Using a thermocompression bonding head 5 provided with a protrusion 4 having a height of about 0.050 mm and a height of about 0.050 mm at a position corresponding to the chip electrode, heat was applied from the side of the flexible printed board to the side of the chip. As a result, the connection pad portion of the wiring pattern (conductor) 8 is deformed into a protruding shape, and the deformed protruding connection pad portion 1 is deformed.
4 and the chip electrode 15 are connected by the conductive particles 10 and the epoxy resin 9 is cured and mounted. Crimping temperature is about 200 ° C, time is about 20
Second, the pressure per unit area of the tip of the projection 4 is about 200M
Performed at Pa. The connection resistance of the connection terminal was about 30 mΩ on average, and a sufficiently low resistance value was obtained.

【0043】[0043]

【実施例3】パッドレス半導体チップ1およびフレキシ
ブルプリント基板2aは、上記実施例1と同一の部材を
用いた。フレキシブルプリント基板のチップ接続領域
に、0.2〜0.3μm程度の厚さの金メッキを施した
直径約0.008mmのニッケル導電粒子と未硬化エポ
キシ樹脂と(導電粒子と未硬化エポキシ樹脂との配合割
合は体積比で10:90〜20:80程度)からなる異
方性導電フィルム3を貼り付けた。次に上記チップ1を
位置合わせ搭載した。次に、直径約0.08mm、高さ
約0.050mmの突起をチップ電極に相当する位置に
設けた加熱圧着ヘッド5を用いて、フレキシブルプリン
ト基板の側からチップの側に加熱圧着した。その結果配
線パターン(導体)8の接続パッド部が突起状に変形
し、この変形した突起状の接続パッド部14とチップ電
極15との間において導電粒子10によって接続される
と共にエポキシ樹脂9が硬化されて実装されることにな
る。圧着温度は約200℃、時間は約20秒、突起4の
先端部単位面積あたりの圧力は約200MPaで行なっ
た。接続端子の接続抵抗は平均30mΩ程度であり十分
に低い抵抗値が得られた。
Embodiment 3 The same members as those in Embodiment 1 were used for the padless semiconductor chip 1 and the flexible printed circuit board 2a. A nickel conductive particle having a diameter of about 0.008 mm and an uncured epoxy resin and a gold plating having a thickness of about 0.2 to 0.3 μm are applied to a chip connection region of a flexible printed circuit board. An anisotropic conductive film 3 having a mixing ratio of about 10:90 to 20:80 by volume) was attached. Next, the chip 1 was aligned and mounted. Next, using a thermocompression bonding head 5 provided with a projection having a diameter of about 0.08 mm and a height of about 0.050 mm at a position corresponding to the chip electrode, the thermocompression bonding was performed from the flexible printed board side to the chip side. As a result, the connection pad portion of the wiring pattern (conductor) 8 is deformed into a protruding shape, and a connection is made between the deformed protruding connection pad portion 14 and the chip electrode 15 by the conductive particles 10 and the epoxy resin 9 is cured. Will be implemented. The compression temperature was about 200 ° C., the time was about 20 seconds, and the pressure per unit area of the tip of the projection 4 was about 200 MPa. The connection resistance of the connection terminal was about 30 mΩ on average, and a sufficiently low resistance value was obtained.

【0044】[0044]

【実施例4】パッドレス半導体チップ1およびフレキシ
ブルプリント基板2aは、上記実施例1と同一の部材を
用いた。フレキシブルプリント基板のチップ接続領域
に、直径約0.005mmのプラスチック粒子の表面に
ニッケルメッキ皮膜(厚さ0.3〜0.6μm程度)お
よび金メッキ皮膜(厚さ0.2〜0.1μm程度)を形
成した導電粒子と未硬化エポキシ樹脂と(導電粒子と未
硬化エポキシ樹脂との配合割合は体積比で10:90〜
20:80程度)からなる異方性導電フィルム3を貼り
付けた。次に上記チップ1を位置合わせ搭載した。次
に、約0.08mm角、高さ約0.08mmの突起4を
チップ電極に相当する位置に設けた加熱圧着ヘッド5を
用いて、フレキシブルプリント基板の側からチップの側
に加熱圧着した。その結果配線パターン(導体)8の接
続パッド部が突起状に変形し、この変形した突起状の接
続パッド部14とチップ電極15との間において導電粒
子10によって接続されると共にエポキシ樹脂9が硬化
されて実装されることになる。圧着温度は約200℃、
時間は約20秒、突起4の先端部単位面積あたりの圧力
は約200MPaで行なった。接続端子の接続抵抗は平
均35mΩ程度であり十分に低い抵抗値が得られた。
Embodiment 4 The same members as those in Embodiment 1 were used for the padless semiconductor chip 1 and the flexible printed circuit board 2a. Nickel plating film (thickness of about 0.3 to 0.6 μm) and gold plating film (thickness of about 0.2 to 0.1 μm) on the surface of plastic particles with a diameter of about 0.005 mm in the chip connection area of the flexible printed circuit board The conductive particles and the uncured epoxy resin formed with (the mixing ratio of the conductive particles and the uncured epoxy resin is 10:90 to
(Approximately 20:80). Next, the chip 1 was aligned and mounted. Next, using a thermocompression bonding head 5 provided with a projection 4 having a size of about 0.08 mm square and a height of about 0.08 mm at a position corresponding to the chip electrode, thermocompression bonding was performed from the flexible printed circuit board side to the chip side. As a result, the connection pad portion of the wiring pattern (conductor) 8 is deformed into a protruding shape, and a connection is made between the deformed protruding connection pad portion 14 and the chip electrode 15 by the conductive particles 10 and the epoxy resin 9 is cured. Will be implemented. The crimping temperature is about 200 ° C,
The time was about 20 seconds, and the pressure per unit area of the tip of the projection 4 was about 200 MPa. The connection resistance of the connection terminal was about 35 mΩ on average, and a sufficiently low resistance value was obtained.

【0045】次に本発明に係る第2の実施の形態につい
て図8〜図11を用いて説明する。
Next, a second embodiment according to the present invention will be described with reference to FIGS.

【0046】本第2の実施の形態は、回路基板2b上に
形成される配線パターン8が異方性導電フィルム3が配
置される領域まで入り込んで設置される場合には上記配
線パターンの接続パッド部に導体からなる突起11を形
成するか、回路基板2c上に形成される配線パターン8
が異方性導電フィルム3が配置される領域まで入り込ま
ないように設置する場合には上記配線パターン8と下層
を通して接続された独立した接続パッド部12を形成す
ることである。図8には、回路基板2bに形成された銅
等の配線パターン上の接続パッド部に導体からなる突起
11を形成した実施の形態を示す。また、図9には、バ
ンプレス半導体チップ1を異方性導電フィルム3を用い
て回路基板2bに加熱圧着して接続実装したときの断面
形状を示す。図9に示すように、回路基板2b上におい
て上記配線パターン8の接続パッド部に導体からなる突
起11を設けることによりチップ電極15と突起11と
の間以外での導電粒子10が加圧されることがなくバン
プレス半導体チップ1と基板2bとの間での直接接触を
防止することができる。
In the second embodiment, when the wiring pattern 8 formed on the circuit board 2b is installed so as to enter the region where the anisotropic conductive film 3 is arranged, the connection pad of the wiring pattern is used. Forming a projection 11 made of a conductor on the portion, or forming a wiring pattern 8 formed on the circuit board 2c.
In the case where is installed so as not to enter the region where the anisotropic conductive film 3 is arranged, an independent connection pad portion 12 connected to the wiring pattern 8 through a lower layer is formed. FIG. 8 shows an embodiment in which a projection 11 made of a conductor is formed on a connection pad portion on a wiring pattern made of copper or the like formed on a circuit board 2b. FIG. 9 shows a cross-sectional shape when the bumpless semiconductor chip 1 is connected to the circuit board 2 b by heating and pressure bonding using the anisotropic conductive film 3. As shown in FIG. 9, by providing a projection 11 made of a conductor on the connection pad portion of the wiring pattern 8 on the circuit board 2 b, the conductive particles 10 other than between the chip electrode 15 and the projection 11 are pressed. Therefore, direct contact between the bumpless semiconductor chip 1 and the substrate 2b can be prevented.

【0047】ところで、回路基板2b上への突起11の
形成は、多数個に裁断する前に一括形成が可能であるた
め、半導体チップへのバンプ形成と比べて極めて低コス
トとなる。この突起11としては、銅、ニッケルなどの
金属材料、あるいは銀、金、銅、ニッケルなどの導電性
接着剤の硬化物を用いる。
By the way, since the formation of the projections 11 on the circuit board 2b can be performed at once before cutting into many pieces, the cost is extremely low as compared with the formation of bumps on a semiconductor chip. As the projection 11, a metal material such as copper or nickel, or a cured product of a conductive adhesive such as silver, gold, copper, or nickel is used.

【0048】また、図10に示すように多層プリント基
板2cでは内層配線からビアホールを介して表面層に配
線し、この独立した配線自体を接続パッド部(導体から
なる突起)12とすることができる。この方法では、独
立した接続パッド部(導体からなる突起)12を形成の
ために新たな工程を要しない。この実施の形態では、多
層プリント基板2cの表面に配線パターン8が形成さ
れ、上記接続パッド部(導体からなる突起)12の厚さ
を配線パターン8の厚さとほぼ同様にする場合には、異
方性導電フィルム3が設置される領域に配線パターン8
が入り込まないようにして、チップ電極15と接続パッ
ド部12との間以外では、導電粒子10が加圧されるこ
とがないので、チップ電極15と接続パッド部12との
間において導電粒子10が加圧されて低い抵抗値で接続
することが可能となる。
Further, as shown in FIG. 10, in the multilayer printed circuit board 2c, wiring is performed from the inner wiring to the surface layer via via holes, and the independent wiring itself can be used as the connection pad portion (projection made of a conductor) 12. . In this method, a new step is not required for forming the independent connection pad portion (projection made of a conductor) 12. In this embodiment, when the wiring pattern 8 is formed on the surface of the multilayer printed circuit board 2c and the thickness of the connection pad portion (projection made of a conductor) 12 is made substantially the same as the thickness of the wiring pattern 8, a different The wiring pattern 8 is formed in the area where the isotropic conductive film 3 is set.
The conductive particles 10 are not pressurized except between the chip electrode 15 and the connection pad portion 12 so that the conductive particles 10 are not pressed between the chip electrode 15 and the connection pad portion 12. Pressurization enables connection with a low resistance value.

【0049】以上述べたように、異方性導電フィルム3
によるフリップチップアタッチ実装において、回路基板
2b、2cの接続パッド部に導体からなる突起11、1
2を形成することにより、一層の低コスト化を実現する
ことができる。
As described above, the anisotropic conductive film 3
In the flip-chip attach mounting according to the first embodiment, the protrusions 11 made of a conductor are provided on the connection pad portions of the circuit boards 2b and 2c.
By forming 2, further cost reduction can be realized.

【0050】回路基板2bの接続パッド部に金属材料か
らなる突起11は、プリント配線板製造工程において部
分メッキ方により容易に形成することができる。導電性
接着剤の硬化物からなる突起11は、プリント配線板製
造工程において導電性接着剤をスクリーン印刷あるいは
マイクロディスペンス塗布により電極パッド部に供給
し、これを加熱処理することにより容易に形成すること
ができる。
The projections 11 made of a metal material on the connection pads of the circuit board 2b can be easily formed by a partial plating method in the printed wiring board manufacturing process. The protrusions 11 made of a cured product of the conductive adhesive are easily formed by supplying the conductive adhesive to the electrode pad portion by screen printing or microdispensing in a printed wiring board manufacturing process, and heating the electrode pad. Can be.

【0051】回路基板2cの接続パッド部に金属材料か
らなる突起12を形成する別の方法は、図10、および
図11に示すように、多層プリント配線板2cの場合、
スルーホール13を通して内層と電気的に導通のある独
立した接続パッド部12を表面層に形成する方法であ
る。この方法は、突起を形成するためのあらたなプロセ
スを必要としないというメリットがある。
Another method of forming the projection 12 made of a metal material on the connection pad portion of the circuit board 2c is as shown in FIGS. 10 and 11, in the case of the multilayer printed wiring board 2c.
In this method, an independent connection pad portion 12 electrically connected to the inner layer through the through hole 13 is formed on the surface layer. This method has an advantage that a new process for forming a projection is not required.

【0052】回路基板2b、2cの接続パッド部に設け
る導体からなる突起11、12のサイズは、半導体チッ
プの電極15のサイズより多少大きくても差し支えない
が、あまりにも大きい場合には接続に不都合が生じる。
従って、突起11、12のサイズは半導体チップの電極
15のサイズ以下であることが好ましい。また、導体か
らなる突起11、12の高さは、約0.003mm〜
0.3mmが好ましい。高さが約0.003mm以下の
場合には、電極部以外の箇所でも半導体チップ1と回路
基板2b、2cとが異方性導電フィルム3の導電粒子1
0を介して接触する問題が生じる。突起11、12の高
さが0.3mm以上になると1回の工程で突起を形成す
ることが困難になると共に、接続ピッチが狭い場合に隣
接パッドでショートを起こす問題が生じる。導体からな
る突起11、12の形状は、円形、角形などとくに限定
されない。本発明に用いる回路基板2b、2cは、リジ
ットプリント基板、フレキシブルプリント基板、セラミ
ック基板、薄膜基板などの使用が可能で、特に限定され
ない。
The size of the projections 11 and 12 made of conductors provided on the connection pads of the circuit boards 2b and 2c may be slightly larger than the size of the electrode 15 of the semiconductor chip. Occurs.
Therefore, it is preferable that the size of the protrusions 11 and 12 is smaller than the size of the electrode 15 of the semiconductor chip. The height of the protrusions 11 and 12 made of a conductor is about 0.003 mm or more.
0.3 mm is preferred. When the height is about 0.003 mm or less, the semiconductor chip 1 and the circuit boards 2b and 2c are connected to the conductive particles 1 of the anisotropic conductive film 3 even at locations other than the electrode portions.
The problem of contact through 0 occurs. When the height of the projections 11 and 12 is 0.3 mm or more, it becomes difficult to form the projections in one process, and when the connection pitch is narrow, there is a problem that a short circuit occurs between adjacent pads. The shape of the protrusions 11 and 12 made of a conductor is not particularly limited to a circle, a square, or the like. As the circuit boards 2b and 2c used in the present invention, a rigid printed board, a flexible printed board, a ceramic board, a thin film board, or the like can be used, and is not particularly limited.

【0053】次に、以上説明した第2の実施の形態につ
いて、更に具体的に実施例として説明する。
Next, the second embodiment described above will be described more specifically as an example.

【0054】[0054]

【実施例5】バンプレス半導体チップ1として次に示す
試験チップを用いた。
Embodiment 5 The following test chip was used as the bumpless semiconductor chip 1.

【0055】サイズ:8mm角 厚さ:0.45mm 接続パッドサイズ:0.105×105mm 接続パッドピッチ:0.13mm 接続配置:周辺4辺 回路基板2bとして6層ガラスエポキシ基板(FR4)
を用い、チップ電極15に対応する接続用配線(銅厚
さ:約0.012mm)8を形成した。配線の幅は約
0.09mm、配線間の間隔は約0.04mmとした。
接続抵抗を4端子法で測定できるよう上記試験チップ及
び回路基板の配線を設計した。
Size: 8 mm square Thickness: 0.45 mm Connection pad size: 0.105 × 105 mm Connection pad pitch: 0.13 mm Connection arrangement: 4 peripheral sides Six-layer glass epoxy board (FR4) as circuit board 2b
Then, a connection wiring (copper thickness: about 0.012 mm) 8 corresponding to the chip electrode 15 was formed. The width of the wiring was about 0.09 mm, and the interval between the wirings was about 0.04 mm.
The test chip and the wiring of the circuit board were designed so that the connection resistance could be measured by the four-terminal method.

【0056】上記回路基板2bの接続端子部にスクリー
ン印刷法で熱硬化性導電性接着剤(Agペースト)パタ
ーンを形成し、約150℃で1時間硬化させ、約0.0
8mm角、高さ約0.04mmの突起11を形成した。
次に、この回路基板2bのチップ接続領域に、実施例1
〜3と同様な直径0.008mmの金メッキニッケル導
電粒子と未硬化エポキシ樹脂とからなる異方性導電フィ
ルム3を貼り付けた。次に上記バンプレス半導体チップ
1を位置合わせ搭載後該チップを加熱ヘッドで圧着し
た。圧着温度は約200℃、圧力は約6kg、時間は約
20秒で行った。接続端子の接続抵抗は平均10mΩ程
度であり、十分に低い抵抗値が得られた。
A thermosetting conductive adhesive (Ag paste) pattern is formed on the connection terminals of the circuit board 2b by a screen printing method, and is cured at about 150 ° C. for 1 hour.
A projection 11 having a size of 8 mm square and a height of about 0.04 mm was formed.
Next, in the chip connection area of the circuit board 2b,
An anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of 0.008 mm and an uncured epoxy resin similar to that of No. 3 was bonded. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 10 mΩ on average, and a sufficiently low resistance value was obtained.

【0057】[0057]

【実施例6】バンプレス半導体チップ1は実施例5と同
一チップを用いた。回路基板2bとして4層ガラスエポ
キシ基板(FR4)を用い、チップ電極15に対応する
接続用配線(銅厚さ:約0.012mm)8を形成し
た。配線の幅は約0.09mm、配線間の間隔は約0.
04mmとした。この基板のチップ接続パッド部には、
さらに金/ニッケル/銅からなる約0.08mm角、高
さ約0.015mmの突起11をメッキ法で形成した。
次に、この回路基板2bのチップ接続領域に、実施例1
〜3と同様な直径0.008mmの金メッキニッケル導
電粒子と未硬化エポキシ樹脂とからなる異方性導電フィ
ルム3を貼り付けた。次に上記バンプレス半導体チップ
1を位置合わせ搭載後該チップを加熱ヘッドで圧着し
た。圧着温度は約200℃、圧力は約6kg、時間は約
20秒で行った。接続端子の接続抵抗は平均10mΩ程
度であり十分に低い抵抗値が得られた。
Embodiment 6 The same bumpless semiconductor chip 1 as in Embodiment 5 was used. Using a four-layer glass epoxy substrate (FR4) as the circuit board 2b, connection wiring (copper thickness: about 0.012 mm) 8 corresponding to the chip electrode 15 was formed. The width of the wiring is about 0.09 mm, and the interval between the wirings is about 0.1 mm.
04 mm. In the chip connection pad part of this board,
Further, a projection 11 of about 0.08 mm square and about 0.015 mm in height made of gold / nickel / copper was formed by plating.
Next, in the chip connection area of the circuit board 2b,
An anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of 0.008 mm and an uncured epoxy resin similar to that of No. 3 was bonded. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 10 mΩ on average, and a sufficiently low resistance value was obtained.

【0058】[0058]

【実施例7】バンプレス半導体チップ1は実施例5と同
一チップを用いた。回路基板2bとして転写法により作
成した4層ガラスエポキシ基板を用いた。チップ接続領
域における配線幅は約0.09mm、配線間隔は約0.
04mmとした。転写法による基板は、チップ接続パッ
ド部に金/ニッケルからなる約0.08mm角、高さ約
0.025mmの突起11が形成されている。次に、こ
の回路基板2bのチップ接続領域に、実施例1〜3と同
様な直径約0.008mmの金メッキニッケル導電粒子
と未硬化エポキシ樹脂とからなる異方性導電フィルム3
を貼り付けた。次に上記バンプレス半導体チップ1を位
置合わせ搭載後該チップを加熱ヘッドで圧着した。圧着
温度は約200℃、圧力は約6kg、時間は約20秒で
行った。接続端子の接続抵抗は平均10mΩ程度であり
十分に低い抵抗値が得られた。
Embodiment 7 The same bumpless semiconductor chip 1 as that of Embodiment 5 was used. A four-layer glass epoxy substrate prepared by a transfer method was used as the circuit board 2b. The wiring width in the chip connection region is about 0.09 mm, and the wiring interval is about 0.5 mm.
04 mm. In the substrate formed by the transfer method, a protrusion 11 of about 0.08 mm square and about 0.025 mm in height made of gold / nickel is formed on the chip connection pad portion. Next, an anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of about 0.008 mm and an uncured epoxy resin similar to those in Examples 1 to 3 was provided in the chip connection area of the circuit board 2b.
Was pasted. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 10 mΩ on average, and a sufficiently low resistance value was obtained.

【0059】[0059]

【実施例8】バンプレス半導体チップ1は実施例5と同
一チップを用いた。回路基板2bとして6層セラミック
基板を用い、チップ電極に対応する接続用配線を形成し
た。配線幅は約0.09mm、配線間隔は約0.04m
mとした。この基板の表面配線層のチップ接続パッド部
には、さらに金/ニッケル/銅からなる約0.08mm
角、高さ約0.015mmの突起11をメッキ法で形成
した。次に、この回路基板のチップ接続領域に、実施例
1〜3と同様な直径約0.008mmの金メッキニッケ
ル導電粒子と未硬化エポキシ樹脂とからなる異方性導電
フィルム3を貼り付けた。次に上記バンプレス半導体チ
ップ1を位置合わせ搭載後該チップを加熱ヘッドで圧着
した。圧着温度は約200℃、圧力は約6kg、時間は
約20秒で行った。接続端子の接続抵抗は平均10mΩ
程度であり十分に低い抵抗値が得られた。
Embodiment 8 The same bumpless semiconductor chip 1 as that of Embodiment 5 was used. Using a six-layer ceramic substrate as the circuit substrate 2b, connection wirings corresponding to the chip electrodes were formed. Wiring width is about 0.09mm, wiring interval is about 0.04m
m. About 0.08 mm of gold / nickel / copper was further added to the chip connection pad portion of the surface wiring layer of this substrate.
A protrusion 11 having a corner and a height of about 0.015 mm was formed by plating. Next, an anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of about 0.008 mm and an uncured epoxy resin similar to those in Examples 1 to 3 was attached to the chip connection region of the circuit board. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. Connection resistance of connection terminal is 10mΩ on average
And a sufficiently low resistance value was obtained.

【0060】[0060]

【実施例9】バンプレス半導体チップ1、回路基板2b
は実施例5と同一部材を用いた。
Embodiment 9 Bumpless semiconductor chip 1, circuit board 2b
Used the same members as in Example 5.

【0061】この回路基板2bのチップ接続領域に、実
施例4と同様な直径約0.005mmのプラスチック粒
子の表面に金皮膜およびニッケル皮膜を形成した導電粒
子と未硬化エポキシ樹脂とからなる異方性導電フィルム
を貼り付けた。次に上記バンプレス半導体チップ1を位
置合わせ搭載後該チップを加熱ヘッドで圧着した。圧着
温度は約200℃、圧力は約6kg、時間は約20秒で
行った。接続端子の接続抵抗は平均15mΩ程度であり
十分に低い抵抗値が得られた。
In the chip connection area of this circuit board 2b, anisotropically formed of conductive particles obtained by forming a gold film and a nickel film on the surface of plastic particles having a diameter of about 0.005 mm and an uncured epoxy resin as in Example 4 A conductive film was attached. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 15 mΩ on average, and a sufficiently low resistance value was obtained.

【0062】[0062]

【実施例10】バンプレス半導体チップ1は実施例5と
同一チップを用いた。回路基板2bとして2層配線フレ
キシブルプリント基板を用いた。銅配線厚は約0.03
5mm、チップ接続領域における配線幅は約0.09m
m、配線間隔は約0.04mmとした。この基板のチッ
プ接続パッド部には、さらに金/ニッケル/銅からなる
約0.06mm角、高さ約0.012mmの突起11を
メッキ法で形成した。次に、この回路基板のチップ接続
領域に、実施例1〜3と同様な直径約0.008mmの
金メッキニッケル導電粒子と未硬化エポキシ樹脂とから
なる異方性導電フィルム3を貼り付けた。次に上記バン
プレス半導体チップ1を位置合わせ搭載後該チップを加
熱ヘッドで圧着した。圧着温度は約200℃、圧力は約
6kg、時間は約20秒で行った。接続端子の接続抵抗
は平均10mΩ程度であり十分に低い抵抗値が得られ
た。
[Embodiment 10] The same chip as in Embodiment 5 was used as the bumpless semiconductor chip 1. A two-layer wiring flexible printed board was used as the circuit board 2b. Copper wiring thickness is about 0.03
5mm, wiring width in chip connection area is about 0.09m
m, and the wiring interval was about 0.04 mm. On the chip connection pad portion of this substrate, a protrusion 11 of about 0.06 mm square and about 0.012 mm in height made of gold / nickel / copper was further formed by plating. Next, an anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of about 0.008 mm and an uncured epoxy resin similar to those in Examples 1 to 3 was attached to the chip connection region of the circuit board. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 10 mΩ on average, and a sufficiently low resistance value was obtained.

【0063】[0063]

【実施例11】バンプレス半導体チップ1は実施例5と
同一チップを用いた。回路基板2cとして4層ガラスエ
ポキシ基板(FR4)を用い、チップ電極15に対応す
る接続パッド部12はスルーホール13を介して内層か
ら引き回した(図10、図11に示す。)。接続パッド
部12の表面には、ニッケル及び金メッキを施した。次
に、この回路基板のチップ接続領域に、実施例1〜3と
同様な直径約0.008mmの金メッキニッケル導電粒
子と未硬化エポキシ樹脂とからなる異方性導電フィルム
3を貼り付けた。次に上記バンプレス半導体チップ1を
位置合わせ搭載後チップを加熱ヘッドで圧着した。圧着
温度は約200℃、圧力は約6kg、時間は約20秒で
行った。接続端子の接続抵抗は平均10mΩ程度であり
十分に低い抵抗値が得られた。
Embodiment 11 The same chip as in Embodiment 5 was used as the bumpless semiconductor chip 1. A four-layer glass epoxy substrate (FR4) was used as the circuit board 2c, and the connection pad portions 12 corresponding to the chip electrodes 15 were routed from the inner layer through the through holes 13 (shown in FIGS. 10 and 11). The surface of the connection pad portion 12 was plated with nickel and gold. Next, an anisotropic conductive film 3 made of gold-plated nickel conductive particles having a diameter of about 0.008 mm and an uncured epoxy resin similar to those in Examples 1 to 3 was attached to the chip connection region of the circuit board. Next, after the bumpless semiconductor chip 1 was aligned and mounted, the chip was pressed by a heating head. The pressing temperature was about 200 ° C., the pressure was about 6 kg, and the time was about 20 seconds. The connection resistance of the connection terminal was about 10 mΩ on average, and a sufficiently low resistance value was obtained.

【0064】[0064]

【発明の効果】本発明によれば、極めて低コストで、高
信頼性を有する半導体ベアチップ実装を実現することが
可能となり、工業的効果が大きい。
According to the present invention, it is possible to realize a semiconductor bare chip mounting with extremely low cost and high reliability, which has a great industrial effect.

【0065】また本発明によれば、バンプレス半導体チ
ップを回路基板に異方性導電フィルムを用いて短絡する
ことなく低抵抗で接続して極めて低コストで、高信頼性
を有する半導体ベアチップ実装を実現することができる
効果を奏する。
Further, according to the present invention, a bumpless semiconductor chip is connected to a circuit board with a low resistance without short-circuiting using an anisotropic conductive film, thereby realizing a very low cost and highly reliable semiconductor bare chip mounting. An effect that can be realized is achieved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係るバンプレスのフリップチップアタ
ッチ実装方式の第1の実施の形態を示す断面図である。
FIG. 1 is a cross-sectional view showing a first embodiment of a flip-chip attach mounting method for a bumpless press according to the present invention.

【図2】図1に示す実装方式で実装された半導体素子実
装構造体を示す断面図である。
FIG. 2 is a cross-sectional view showing a semiconductor element mounting structure mounted by the mounting method shown in FIG.

【図3】図1に示す加熱圧着ヘッドを示す斜視図であ
る。
FIG. 3 is a perspective view showing the thermocompression bonding head shown in FIG. 1;

【図4】加熱圧着ヘッドに形成する突起の形状の一実施
の形態を示す拡大図である。
FIG. 4 is an enlarged view showing an embodiment of a shape of a projection formed on a thermocompression bonding head.

【図5】加熱圧着ヘッドに形成する突起の形状の他の実
施の形態を示す拡大図である。
FIG. 5 is an enlarged view showing another embodiment of a shape of a projection formed on a thermocompression bonding head.

【図6】図1に示す第1の実施の形態において異方性導
電フィルムをバンプレス半導体チップに貼り付ける場合
を示した図である。
FIG. 6 is a diagram showing a case where an anisotropic conductive film is attached to a bumpless semiconductor chip in the first embodiment shown in FIG.

【図7】図1に示す第1の実施の形態において異方性導
電フィルムをフレキシ回路基板に貼り付ける場合を示し
た図である。
FIG. 7 is a diagram showing a case where an anisotropic conductive film is attached to a flexi circuit board in the first embodiment shown in FIG.

【図8】本発明に係るバンプレスのフリップチップアタ
ッチ実装方式の第2の実施の形態を説明するための回路
基板に形成した独立した接続パッド部の一実施の形態を
示す斜視図である。
FIG. 8 is a perspective view showing one embodiment of an independent connection pad portion formed on a circuit board for describing a second embodiment of the flip-chip attach mounting method of bumpless according to the present invention.

【図9】図8に示す回路基板上に形成された接続パッド
部を用いて実装した半導体素子実装構造体を示す断面図
である。
FIG. 9 is a cross-sectional view showing a semiconductor element mounting structure mounted using connection pad portions formed on the circuit board shown in FIG. 8;

【図10】本発明に係るバンプレスのフリップチップア
タッチ実装方式の第2の実施の形態を説明するための回
路基板に形成した独立した接続パッド部の他の実施の形
態を示す斜視図である。
FIG. 10 is a perspective view showing another embodiment of an independent connection pad portion formed on a circuit board for describing a second embodiment of the flip-chip attach mounting method of bumpless according to the present invention. .

【図11】図10に示す回路基板上に形成された接続パ
ッド部を用いて実装した半導体素子実装構造体を示す断
面図である。
11 is a cross-sectional view showing a semiconductor element mounting structure mounted using connection pad portions formed on the circuit board shown in FIG.

【図12】従来のワイヤボンド法によるベアチップ実装
構造を示す図である。
FIG. 12 is a diagram illustrating a bare chip mounting structure by a conventional wire bonding method.

【図13】従来の金バンプと半田によるベアチップ実装
構造を示す図である。
FIG. 13 is a diagram showing a conventional bare chip mounting structure using gold bumps and solder.

【図14】従来の金バンプと導電性接着剤によるベアチ
ップ実装構造を示す図である。
FIG. 14 is a diagram showing a conventional bare chip mounting structure using gold bumps and a conductive adhesive.

【図15】従来の金バンプと異方性導電フィルムによる
ベアチップ実装構造を示す図である。
FIG. 15 is a diagram showing a conventional bare chip mounting structure using gold bumps and an anisotropic conductive film.

【図16】従来の金バンプと異方性導電フィルムによる
ベアチップ実装構造組立て法を示す図である。
FIG. 16 is a view showing a conventional method for assembling a bare chip mounting structure using gold bumps and an anisotropic conductive film.

【符号の説明】[Explanation of symbols]

1…バンプレス半導体チップ、 2a…フレキシブルプ
リント基板、 2b…回路基板、 2c…回路基板、
3…異方性導電フィルム、 4…突起、 5…加熱圧着
ヘッド、 8…配線パターン(導体)、 9…エポキシ
樹脂、 10…導電粒子、 11…導体からなる突起
(接続パッド部)、 12…突起(接続パッド部)、
13…突起状の接続パッド部、 15…電極
DESCRIPTION OF SYMBOLS 1 ... Bumpless semiconductor chip, 2a ... Flexible printed board, 2b ... Circuit board, 2c ... Circuit board,
3 ... anisotropic conductive film, 4 ... protrusion, 5 ... thermocompression bonding head, 8 ... wiring pattern (conductor), 9 ... epoxy resin, 10 ... conductive particles, 11 ... protrusion made of conductor (connection pad portion), 12 ... Projection (connection pad),
13: Projecting connection pad portion, 15: Electrode

Claims (12)

【特許請求の範囲】[Claims] 【請求項1】半導体素子を異方性導電フィルムにより回
路基板に実装したフリップチップアタッチ方式の半導体
素子実装構造体において、前記半導体素子をバンプが形
成されていない電極を複数並設して構成し、前記半導体
素子と対向する回路基板上の実装面領域において突起状
の接続パッド部を前記各電極に対向する位置に複数並設
し、該各突起状の接続パッド部と前記各電極の間を前記
異方性導電フィルムに内在する導電粒子で接続して構成
したことを特徴とする半導体素子実装構造体。
In a flip chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, the semiconductor element is formed by arranging a plurality of electrodes on which no bumps are formed. In the mounting surface region on the circuit board facing the semiconductor element, a plurality of projecting connection pad portions are arranged in parallel at positions facing the respective electrodes, and a space between the respective projecting connection pad portions and the respective electrodes is provided. A semiconductor element mounting structure, wherein the semiconductor element mounting structure is formed by connecting conductive particles inherent in the anisotropic conductive film.
【請求項2】半導体素子を異方性導電フィルムにより回
路基板に実装したフリップチップアタッチ方式の半導体
素子実装構造体において、前記半導体素子をバンプが形
成されていない電極を複数並設して構成し、前記半導体
素子と対向する回路基板上の実装面領域において接続パ
ッド部を前記各電極に対する間隙を狭めて対向する位置
に複数並設し、該各接続パッド部と前記各電極の間を前
記異方性導電フィルムに内在する導電粒子で接続して構
成したことを特徴とする半導体素子実装構造体。
2. A flip-chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, wherein the semiconductor element is formed by arranging a plurality of electrodes on which no bumps are formed. A plurality of connection pad portions are arranged in parallel at positions facing each other in the mounting surface region on the circuit board facing the semiconductor element by narrowing a gap with respect to each of the electrodes, and the difference between each connection pad portion and each of the electrodes is reduced. A semiconductor element mounting structure, wherein the semiconductor element mounting structure is formed by connecting conductive particles inherent in an isotropic conductive film.
【請求項3】半導体素子を異方性導電フィルムにより回
路基板に実装したフリップチップアタッチ方式の半導体
素子実装構造体において、前記半導体素子をバンプが形
成されていない電極を複数並設して構成し、前記半導体
素子と対向する回路基板上の実装面領域において複数の
配線パターンの各々に接続された突起状の接続パッド部
を前記各電極に対向する位置に複数並設し、該各突起状
の接続パッド部と前記各電極の間を前記異方性導電フィ
ルムに内在する導電粒子で接続して構成したことを特徴
とする半導体素子実装構造体。
3. A flip chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, wherein the semiconductor element is configured by arranging a plurality of electrodes on which no bumps are formed. In the mounting surface area on the circuit board facing the semiconductor element, a plurality of protruding connection pads connected to each of the plurality of wiring patterns are arranged in parallel at positions facing the respective electrodes, and each of the protruding connection pads is provided. A semiconductor element mounting structure, wherein a connection pad portion and each of the electrodes are connected by conductive particles inherent in the anisotropic conductive film.
【請求項4】半導体素子を異方性導電フィルムにより回
路基板に実装したフリップチップアタッチ方式の半導体
素子実装構造体において、前記半導体素子をバンプが形
成されていない電極を複数並設して構成し、前記半導体
素子と対向する回路基板上の実装領域において複数の配
線パターンの各々に接続され、局部的に変形させること
によって突起した接続パッド部を前記各電極に対向する
位置に複数並設し、該各突起した接続パッド部と前記各
電極の間を前記異方性導電フィルムに内在する導電粒子
で接続して構成したことを特徴とする半導体素子実装構
造体。
4. A flip chip attach type semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, wherein the semiconductor element is configured by arranging a plurality of electrodes on which no bumps are formed. A plurality of connection pad portions connected to each of a plurality of wiring patterns in a mounting region on a circuit board opposed to the semiconductor element and protruded by locally deforming at a position facing each of the electrodes, A semiconductor element mounting structure, wherein each protruding connection pad portion and each of the electrodes are connected by conductive particles inherent in the anisotropic conductive film.
【請求項5】半導体素子を異方性導電フィルムにより回
路基板に実装したフリップチップアタッチ方式の半導体
素子実装構造体において、前記半導体素子をバンプが形
成されていない電極を複数並設して構成し、前記半導体
素子と対向する回路基板上の実装領域において下層につ
ながった接続パッド部のみを前記各電極に対向する位置
に複数並設し、該各接続パッド部と前記各電極の間を前
記異方性導電フィルムに内在する導電粒子で接続して構
成したことを特徴とする半導体素子実装構造体。
5. A flip-chip-attached semiconductor element mounting structure in which a semiconductor element is mounted on a circuit board with an anisotropic conductive film, wherein the semiconductor element is constituted by arranging a plurality of electrodes on which no bumps are formed. In the mounting area on the circuit board facing the semiconductor element, only a plurality of connection pad portions connected to the lower layer are arranged in parallel at positions facing the respective electrodes, and the difference between the respective connection pad portions and the respective electrodes is defined by the difference. A semiconductor element mounting structure, wherein the semiconductor element mounting structure is formed by connecting conductive particles inherent in an isotropic conductive film.
【請求項6】バンプを形成していない電極を複数並設し
た半導体素子と、半導体素子の側に突起状に変形した導
体で形成された接続パッド部を前記各電極と対向するよ
うに複数並設した回路基板とを異方性導電フィルムを介
して接続接着して構成したことを特徴とする半導体素子
実装構造体。
6. A semiconductor device in which a plurality of electrodes on which no bumps are formed are arranged in parallel, and a plurality of connection pads formed of a conductor deformed in a projecting shape on the side of the semiconductor device are arranged in parallel with each of the electrodes. A semiconductor element mounting structure, wherein the mounted circuit board is connected and bonded via an anisotropic conductive film.
【請求項7】フレキシブル回路基板に異方性導電フィル
ムを貼付ける異方性導電フィルム貼付工程と、該異方性
導電フィルムを貼付けたフレキシブル回路基板を、バン
プを形成していない電極を複数並設した半導体素子に対
して位置合わせして搭載する搭載工程と、該搭載工程で
半導体素子に対して搭載されたフレキシブル回路基板に
対して前記各電極の配置に対応して形成された複数の突
起を有する加熱ヘッドを押しつけることによってフレキ
シブル回路基板上に形成された導体を突起状に変形させ
て複数の接続パッド部を形成して該各接続パッド部と前
記各電極との間を異方性導電フィルムに内在する導電粒
子で接続する加熱ヘッド押付工程とを有することを特徴
とする半導体素子実装方法。
7. An anisotropic conductive film adhering step of adhering an anisotropic conductive film to a flexible circuit board; A mounting step of mounting the semiconductor element in alignment with the provided semiconductor element, and a plurality of protrusions formed corresponding to the arrangement of the electrodes on the flexible circuit board mounted on the semiconductor element in the mounting step The conductor formed on the flexible circuit board is deformed into a protruding shape by pressing a heating head having a plurality of connection pad portions, and an anisotropic conductive path is formed between each of the connection pad portions and each of the electrodes. A heating head pressing step of connecting with conductive particles present in the film.
【請求項8】バンプを形成していない電極を複数並設し
た半導体素子に異方性導電フィルムを貼付ける異方性導
電フィルム貼付工程と、フレキシブル回路基板を、前記
異方性導電フィルムを貼付けた半導体素子に対して位置
合わせして搭載する搭載工程と、該搭載工程で半導体素
子に対して搭載されたフレキシブル回路基板に対して前
記各電極の配置に対応して形成された複数の突起を有す
る加熱ヘッドを押しつけることによってフレキシブル回
路基板上に形成された導体を突起状に変形させて複数の
接続パッド部を形成して該各接続パッド部と前記各電極
との間を異方性導電フィルムに内在する導電粒子で接続
する加熱ヘッド押付工程とを有することを特徴とする半
導体素子実装方法。
8. An anisotropic conductive film adhering step of adhering an anisotropic conductive film to a semiconductor element having a plurality of electrodes on which no bumps are formed, and attaching a flexible circuit board to the anisotropic conductive film. A mounting step of aligning and mounting with respect to the semiconductor element, and a plurality of protrusions formed corresponding to the arrangement of the respective electrodes on the flexible circuit board mounted on the semiconductor element in the mounting step. The conductor formed on the flexible circuit board is deformed into a projection shape by pressing a heating head having a plurality of connection pad portions, and an anisotropic conductive film is formed between each of the connection pad portions and each of the electrodes. And a heating head pressing step of connecting with conductive particles existing in the semiconductor device.
【請求項9】バンプを形成していない電極を複数並設し
た半導体素子と、導体からなる突起を有する接続パッド
部を複数並設した回路基板とを、異方性導電フィルムで
接続接着して構成したことを特徴とする半導体素子実装
構造体。
9. An anisotropic conductive film is used to connect and bond a semiconductor element having a plurality of electrodes on which no bumps are formed in parallel and a circuit board having a plurality of connection pads having projections made of conductors. A semiconductor element mounting structure characterized by comprising.
【請求項10】前記導体からなる突起を、導電性接着剤
の硬化物で形成したことを特徴とする請求項9記載の半
導体素子実装構造体。
10. The semiconductor element mounting structure according to claim 9, wherein said projections made of a conductor are formed of a cured product of a conductive adhesive.
【請求項11】前記導体からなる突起を、金属材料で形
成したことを特徴とする請求項9記載の半導体素子実装
構造体。
11. The semiconductor element mounting structure according to claim 9, wherein said projection made of a conductor is formed of a metal material.
【請求項12】バンプを形成していない電極を複数並設
した半導体素子と、ビアホール上に形成された接続パッ
ド部を複数並設した回路基板とを、異方性導電フィルム
で接続接着して構成したことを特徴とする半導体素子実
装構造体。
12. A semiconductor device having a plurality of electrodes on which no bumps are formed and a circuit board having a plurality of connection pads formed on via holes are connected and bonded by an anisotropic conductive film. A semiconductor element mounting structure characterized by comprising.
JP364697A 1997-01-13 1997-01-13 Semiconductor element mounting structure and semiconductor element mounting method Pending JPH10199934A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP364697A JPH10199934A (en) 1997-01-13 1997-01-13 Semiconductor element mounting structure and semiconductor element mounting method

Publications (1)

Publication Number Publication Date
JPH10199934A true JPH10199934A (en) 1998-07-31

Family

ID=11563255

Family Applications (1)

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JP364697A Pending JPH10199934A (en) 1997-01-13 1997-01-13 Semiconductor element mounting structure and semiconductor element mounting method

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