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JP2001223243A - Semiconductor device and its manufacturing method, circuit board, and electronic equipment - Google Patents

Semiconductor device and its manufacturing method, circuit board, and electronic equipment

Info

Publication number
JP2001223243A
JP2001223243A JP2000034501A JP2000034501A JP2001223243A JP 2001223243 A JP2001223243 A JP 2001223243A JP 2000034501 A JP2000034501 A JP 2000034501A JP 2000034501 A JP2000034501 A JP 2000034501A JP 2001223243 A JP2001223243 A JP 2001223243A
Authority
JP
Japan
Prior art keywords
semiconductor device
bump
wiring
substrate
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP2000034501A
Other languages
Japanese (ja)
Inventor
Yohei Kurashima
羊平 倉島
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP2000034501A priority Critical patent/JP2001223243A/en
Publication of JP2001223243A publication Critical patent/JP2001223243A/en
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13018—Shape in side view comprising protrusions or indentations
    • H01L2224/13019—Shape in side view comprising protrusions or indentations at the bonding interface of the bump connector, i.e. on the surface of the bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/14104—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
    • H01L2224/1411—Disposition relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body the bump connectors being bonded to at least one common bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/17104—Disposition relative to the bonding areas, e.g. bond pads
    • H01L2224/17106—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area
    • H01L2224/17107—Disposition relative to the bonding areas, e.g. bond pads the bump connectors being bonded to at least one common bonding area the bump connectors connecting two common bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81194—Lateral distribution of the bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06—Polymers
    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/0781—Adhesive characteristics other than chemical being an ohmic electrical conductor
    • H01L2924/07811—Extrinsic, i.e. with electrical conductive fillers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Multi-Conductor Connections (AREA)
  • Connections Effected By Soldering, Adhesion, Or Permanent Deformation (AREA)
  • Coupling Device And Connection With Printed Circuit (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

(57)【要約】 【課題】 電気的な接続信頼性を確保できる半導体装置
及びその製造方法、回路基板並びに電子機器を提供する
ことにある。 【解決手段】 半導体装置は、複数の電極１２を有し、
各電極１２にバンプ１６が形成されてなる半導体チップ
１０と、半導体チップ１０が搭載され、バンプ１６との
接合部２４を有する配線２２が形成された基板２０と、
を含み、配線２２の接合部２４は、バンプ１６に入り込
んで接合され、接合部２４とバンプ１６との間には導電
粒子２７が介在する。 An object of the present invention is to provide a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device that can secure electrical connection reliability. SOLUTION: The semiconductor device has a plurality of electrodes 12,
A semiconductor chip 10 having a bump 16 formed on each electrode 12, a substrate 20 on which the semiconductor chip 10 is mounted and a wiring 22 having a joint 24 with the bump 16 is formed;
The bonding portion 24 of the wiring 22 enters the bump 16 and is bonded, and the conductive particles 27 are interposed between the bonding portion 24 and the bump 16.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【０００１】[0001]

【発明の属する技術分野】本発明は、半導体装置及びそ
の製造方法、回路基板並びに電子機器に関する。The present invention relates to a semiconductor device and a method of manufacturing the same, a circuit board, and an electronic device.

【０００２】[0002]

【発明の背景】フリップチップ実装では、半導体チップ
に設けられたバンプと、基板に形成された配線パターン
と、を電気的に接続する。例えば、バンプと配線パター
ンとを、圧接させたり、導電粒子を介在させて電気的に
接続する方法が知られている。BACKGROUND OF THE INVENTION In flip-chip mounting, a bump provided on a semiconductor chip is electrically connected to a wiring pattern formed on a substrate. For example, a method is known in which a bump and a wiring pattern are electrically connected to each other by pressing or connecting conductive particles.

【０００３】しかし、例えば基板が変形した場合や、基
板が多層基板である場合には、バンプと配線パターンと
のギャップが均一でないため、電気的な接続信頼性を確
保することが難しかった。また、基板と半導体チップの
熱膨張率が異なるため、接続部が横方向にずれると、電
気的な接続信頼性を確保することが難しかった。However, for example, when the substrate is deformed or when the substrate is a multilayer substrate, it is difficult to ensure electrical connection reliability because the gap between the bump and the wiring pattern is not uniform. In addition, since the thermal expansion coefficients of the substrate and the semiconductor chip are different, it is difficult to secure electrical connection reliability when the connection portion is shifted in the lateral direction.

【０００４】本発明は、この問題点を解決するものであ
り、その目的は、電気的な接続信頼性を確保できる半導
体装置及びその製造方法、回路基板並びに電子機器を提
供することにある。An object of the present invention is to solve this problem, and an object of the present invention is to provide a semiconductor device which can ensure electrical connection reliability, a method of manufacturing the same, a circuit board, and an electronic device.

【０００５】[0005]

【課題を解決するための手段】（１）本発明に係る半導
体装置は、複数の電極を有し、各電極にバンプが形成さ
れてなる半導体チップと、前記半導体チップが搭載さ
れ、前記バンプとの少なくとも１つの接合部を有する配
線が形成された基板と、導電粒子を含有して、前記半導
体チップと前記基板とを接着する接着剤と、を含み、前
記接合部は、前記バンプに入り込み、前記導電粒子は、
前記接合部とバンプとの間に介在してなる。(1) A semiconductor device according to the present invention has a plurality of electrodes, a semiconductor chip having a bump formed on each electrode, and a semiconductor chip having the semiconductor chip mounted thereon. A substrate on which a wiring having at least one junction is formed, and an adhesive containing conductive particles and bonding the semiconductor chip and the substrate, wherein the junction enters the bump, The conductive particles,
It is interposed between the joint and the bump.

【０００６】本発明によれば、配線の接合部がバンプに
入り込むので、複数のバンプと配線とのギャップが均一
でなくても、信頼性の高い電気的接続及び強固な接合が
可能になる。また、接合部とバンプとが横方向にずれる
力が加えられても、電気的な接続状態が維持される。さ
らに、バンプに接合部が入り込むことで、接合部とバン
プとの間に導電粒子が介在しやすい。According to the present invention, since the bonding portion of the wiring enters the bump, highly reliable electrical connection and strong bonding can be achieved even if the gap between the plurality of bumps and the wiring is not uniform. Further, even if a force is applied to shift the bonding portion and the bump in the horizontal direction, the electrical connection state is maintained. Furthermore, since the bonding portion enters the bump, conductive particles are likely to intervene between the bonding portion and the bump.

【０００７】（２）この半導体装置において、前記配線
は、複数の前記接合部を有し、いずれか１つの前記バン
プに、前記接合部のうちの複数が入り込んでいてもよ
い。(2) In this semiconductor device, the wiring may have a plurality of the joints, and a plurality of the joints may enter one of the bumps.

【０００８】これによれば、バンプに食い込む部分が増
えるので、より強固な接続が得られる。また、複数の接
合部によって凹凸ができるので、導電粒子の逃げが防止
され、介在する導電粒子数を増やすことができる。[0010] According to this, a portion that bites into the bump increases, so that a stronger connection can be obtained. In addition, since unevenness is formed by the plurality of joints, escape of the conductive particles is prevented, and the number of conductive particles interposed can be increased.

【０００９】（３）本発明に係る半導体装置は、複数の
電極を有し、各電極にバンプが形成されてなる半導体チ
ップと、前記半導体チップが搭載され、前記バンプとの
接合部を複数有する配線が形成された基板と、を含み、
前記配線は、いずれか一つの前記バンプに、前記接合部
のうちの複数が入り込んでなる。(3) A semiconductor device according to the present invention has a plurality of electrodes, a semiconductor chip having bumps formed on each of the electrodes, and a plurality of joints on which the semiconductor chip is mounted and the bumps. A substrate on which wiring is formed,
In the wiring, a plurality of the bonding portions enter one of the bumps.

【００１０】本発明によれば、配線の接合部がバンプに
入り込むので、複数のバンプと配線とのギャップが均一
でなくても、信頼性の高い電気的接続及び強固な接合が
可能になる。また、接合部とバンプとが横方向にずれる
力が加えられても、電気的な接続状態が維持される。さ
らに、バンプに接合部が入り込むことで、接合部とバン
プとの間に導電粒子が介在しやすい。According to the present invention, since the bonding portion of the wiring enters the bump, highly reliable electrical connection and strong bonding can be achieved even if the gap between the plurality of bumps and the wiring is not uniform. Further, even if a force is applied to shift the bonding portion and the bump in the horizontal direction, the electrical connection state is maintained. Furthermore, since the bonding portion enters the bump, conductive particles are likely to intervene between the bonding portion and the bump.

【００１１】さらに、複数の接合部がバンプに食い込む
ので、より強固な接続が得られる。また、複数の接合部
によって凹凸ができるので、導電粒子の逃げが防止さ
れ、介在する導電粒子数を増やすことができる。Further, since a plurality of joints cut into the bump, a stronger connection can be obtained. In addition, since unevenness is formed by the plurality of joints, escape of the conductive particles is prevented, and the number of conductive particles interposed can be increased.

【００１２】（４）この半導体装置において、前記接合
部の表面は、ニッケルメッキ層で形成されていてもよ
い。(4) In this semiconductor device, the surface of the joint may be formed of a nickel plating layer.

【００１３】ニッケルは硬いので、接合部を硬く形成す
ることができる。[0013] Since nickel is hard, the joint can be formed hard.

【００１４】（５）この半導体装置において、前記接合
部は、ほぼ同一の縦断面が連続する線状をなし、前記基
板側の基端部よりも上端部が細く形成されてもよい。(5) In this semiconductor device, the bonding portion may be formed in a linear shape having substantially the same vertical cross section, and an upper end portion may be formed thinner than a base end portion on the substrate side.

【００１５】これによれば、接合部の上端部が細いの
で、バンプに接合部を入り込ませやすくなっている。According to this, since the upper end of the joint is thin, it is easy for the joint to enter the bump.

【００１６】（６）この半導体装置において、前記接合
部は、前記基板側の基端部よりも上端部が小さく形成さ
れたランド部であってもよい。(6) In this semiconductor device, the bonding portion may be a land portion having an upper end portion smaller than a base end portion on the substrate side.

【００１７】（７）この半導体装置において、前記接合
部は、複数段を有する形状であってもよい。(7) In this semiconductor device, the joint may have a shape having a plurality of steps.

【００１８】（８）この半導体装置において、前記接着
剤の収縮力によって、前記接合部の側面と前記バンプと
が圧接していてもよい。(8) In this semiconductor device, the side surface of the joint and the bump may be in pressure contact with each other due to the contraction force of the adhesive.

【００１９】これによれば、接合部の側面とバンプとが
圧接するので、電気的な接続信頼性が向上する。According to this, since the side surface of the bonding portion is pressed against the bump, the electrical connection reliability is improved.

【００２０】（９）この半導体装置は、ＩＣカードとし
て構成されてもよい。(9) The semiconductor device may be configured as an IC card.

【００２１】（１０）この半導体装置は、外部端子をさ
らに有してもよい。(10) The semiconductor device may further have an external terminal.

【００２２】（１１）本発明に係る回路基板は、上記半
導体装置が実装されたものである。(11) A circuit board according to the present invention has the above-described semiconductor device mounted thereon.

【００２３】（１２）本発明に係る電子機器は、上記半
導体装置を有する。(12) An electronic apparatus according to the present invention includes the above semiconductor device.

【００２４】（１３）本発明に係る半導体装置の製造方
法は、複数の電極を有して各電極にバンプが形成されて
なる半導体チップを、導電粒子を含有する接着剤を使用
して、配線が形成された基板に実装する工程を含み、前
記配線は、前記バンプとの接合部を有し、前記接合部
を、前記バンプに入り込ませ、前記導電粒子を前記接合
部とバンプとの間に介在させる。(13) In the method of manufacturing a semiconductor device according to the present invention, a semiconductor chip having a plurality of electrodes and bumps formed on each of the electrodes is formed by using an adhesive containing conductive particles. Including the step of mounting on the substrate on which the wiring is formed, the wiring has a joint with the bump, the joint is inserted into the bump, the conductive particles between the joint and the bump Intervene.

【００２５】本発明によれば、配線の接合部をバンプに
入り込ませるので、複数のバンプと配線とのギャップが
均一でなくても、信頼性の高い電気的接続及び強固な接
合が可能になる。また、接合部とバンプとが横方向にず
れる力が加えられても、電気的な接続状態が維持され
る。さらに、バンプに接合部が入り込むことで、接合部
とバンプとの間に導電粒子が介在しやすい。According to the present invention, since the bonding portion of the wiring is inserted into the bump, highly reliable electrical connection and strong bonding can be achieved even if the gap between the plurality of bumps and the wiring is not uniform. . Further, even if a force is applied to shift the bonding portion and the bump in the horizontal direction, the electrical connection state is maintained. Furthermore, since the bonding portion enters the bump, conductive particles are likely to intervene between the bonding portion and the bump.

【００２６】（１４）この半導体装置の製造方法におい
て、前記配線は、複数の前記接合部を有し、いずれか１
つの前記バンプに、前記接合部のうちの複数を入り込ま
せてもよい。(14) In this method of manufacturing a semiconductor device, the wiring has a plurality of the junctions.
A plurality of the joints may be inserted into one of the bumps.

【００２７】これによれば、バンプに食い込む部分が増
えるので、より強固な接続が得られる。また、複数の接
合部によって凹凸ができるので、導電粒子の逃げが防止
され、介在する導電粒子数を増やすことができる。[0027] According to this, a portion that bites into the bump increases, so that a stronger connection can be obtained. In addition, since unevenness is formed by the plurality of joints, escape of the conductive particles is prevented, and the number of conductive particles interposed can be increased.

【００２８】（１５）この半導体装置の製造方法におい
て、前記接合部の表面を、ニッケルメッキ層で形成して
もよい。(15) In this method of manufacturing a semiconductor device, the surface of the joint may be formed of a nickel plating layer.

【００２９】ニッケルは硬いので、接合部を硬く形成す
ることができる。Since nickel is hard, the joint can be formed hard.

【００３０】（１６）この半導体装置の製造方法におい
て、前記接合部を、ほぼ同一の縦断面が連続する線状に
形成するとともに、前記基板側の基端部よりも上端部を
細く形成してもよい。(16) In this method of manufacturing a semiconductor device, the joining portion is formed in a linear shape having substantially the same vertical cross section and the upper end portion is formed thinner than the base end portion on the substrate side. Is also good.

【００３１】これによれば、接合部の上端部が細いの
で、バンプに接合部を入り込ませやすくなっている。According to this, since the upper end of the joint is thin, it is easy for the joint to enter the bump.

【００３２】（１７）この半導体装置の製造方法におい
て、前記接合部を、前記基板側の基端部よりも上端部が
小さく形成されたランド部として形成してもよい。(17) In this method of manufacturing a semiconductor device, the bonding portion may be formed as a land portion having an upper end portion smaller than a base end portion on the substrate side.

【００３３】（１８）この半導体装置の製造方法におい
て、前記接合部を、複数段を有する形状で形成してもよ
い。(18) In this method of manufacturing a semiconductor device, the joint may be formed in a shape having a plurality of steps.

【００３４】（１９）この半導体装置の製造方法におい
て、前記接着剤の収縮力によって、前記配線の前記接合
部の側面と前記バンプとを圧接させてもよい。(19) In this method of manufacturing a semiconductor device, the side surface of the joint of the wiring and the bump may be pressed against each other by a contraction force of the adhesive.

【００３５】これによれば、接合部の側面とバンプとが
圧接するので、電気的な接続信頼性が向上する。According to this, since the side surface of the bonding portion is pressed against the bump, the electrical connection reliability is improved.

【００３６】[0036]

【発明の実施の形態】以下、本発明の好適な実施の形態
について図面を参照して説明する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings.

【００３７】図１（Ａ）及び図１（Ｂ）は、本発明を適
用した実施の形態に係る半導体装置の製造方法を示す図
である。本実施の形態では、半導体チップ１０と、基板
２０と、が使用される。FIGS. 1A and 1B are diagrams showing a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied. In the present embodiment, a semiconductor chip 10 and a substrate 20 are used.

【００３８】半導体チップ１０の平面形状は一般的には
矩形である。半導体チップ１０の一方の面に、複数の電
極１２が形成されている。電極１２は、半導体チップ１
０の面の少なくとも１辺（多くの場合、平行な２辺又は
４辺）に沿って並んでいる。また、電極１２は、半導体
チップ１０の面の端部に並んでいる場合と、中央部に並
んでいる場合がある。各電極１２は、アルミニウムなど
で薄く平らに形成されたパッドである。電極１２の少な
くとも一部を避けて半導体チップ１０には、パッシベー
ション膜１４が形成されている。パッシベーション膜１
４は、例えば、ＳｉＯ2、ＳｉＮ、ポリイミド樹脂など
で形成することができる。The planar shape of the semiconductor chip 10 is generally rectangular. A plurality of electrodes 12 are formed on one surface of the semiconductor chip 10. The electrode 12 is a semiconductor chip 1
They are arranged along at least one side (often two or four parallel sides) of the 0 plane. The electrodes 12 may be arranged at the end of the surface of the semiconductor chip 10 or may be arranged at the center. Each electrode 12 is a thin and flat pad made of aluminum or the like. A passivation film 14 is formed on the semiconductor chip 10 avoiding at least a part of the electrode 12. Passivation film 1
4 can be formed of, for example, SiO 2 , SiN, polyimide resin, or the like.

【００３９】電極１２には、バンプ１６が設けられてい
る。したがって、半導体チップ１０をフリップチップと
称してもよいが、半導体チップ１０がパッケージ化され
ていてもよい。バンプ１６は、銀ペーストなどの導電ペ
ーストで形成してもよいし、金、銅、銀及び錫などの金
属で形成してもよい。バンプ１６は、無電解メッキで形
成してもよいし、ワイヤボンディングによるバンプであ
ってもよい。バンプ１６は、後述する配線２２の接合部
２４を構成する材料よりも軟らかい材料で形成されてい
ることが好ましい。なお、導電ペーストは、金、銀、銅
及びニッケルよりも軟らかい。ニッケルは、金、銀及び
銅よりも硬い。バンプ１６の形状は特に限定されず、複
数段の形状をなしていてもよい。The electrode 12 is provided with a bump 16. Therefore, the semiconductor chip 10 may be referred to as a flip chip, but the semiconductor chip 10 may be packaged. The bump 16 may be formed of a conductive paste such as a silver paste, or may be formed of a metal such as gold, copper, silver, and tin. The bump 16 may be formed by electroless plating, or may be a bump formed by wire bonding. It is preferable that the bump 16 is formed of a material softer than a material forming a bonding portion 24 of the wiring 22 described later. Note that the conductive paste is softer than gold, silver, copper, and nickel. Nickel is harder than gold, silver and copper. The shape of the bump 16 is not particularly limited, and may be a plurality of steps.

【００４０】基板２０は、本願では、配線２２を支持す
る基材（ベース基板）を指す。基板２０の材料は、有機
系又は無機系のいずれの材料であってもよく、これらの
複合構造からなるものであってもよい。基板２０とし
て、例えば、ポリエチレンテレフタレート（ＰＥＴ）か
らなる基板又はフィルムを使用してもよい。あるいは、
基板２０としてポリイミド樹脂からなるフレキシブル基
板を使用してもよい。フレキシブル基板として、ＦＰＣ
（Flexible Printed Circuit）や、ＴＡＢ（TapeAutoma
ted Bonding）技術で使用されるテープを使用してもよ
い。また、無機系の材料から形成された基板２０とし
て、例えばセラミック基板やガラス基板が挙げられる。
有機系及び無機系の材料の複合構造として、例えばガラ
スエポキシ基板が挙げられる。In the present application, the substrate 20 refers to a base (base substrate) that supports the wiring 22. The material of the substrate 20 may be any of an organic or inorganic material, and may have a composite structure thereof. As the substrate 20, for example, a substrate or a film made of polyethylene terephthalate (PET) may be used. Or,
A flexible substrate made of a polyimide resin may be used as the substrate 20. FPC as flexible substrate
(Flexible Printed Circuit) and TAB (TapeAutoma
Tapes used in ted bonding techniques may be used. Further, as the substrate 20 formed of an inorganic material, for example, a ceramic substrate or a glass substrate can be used.
As a composite structure of an organic material and an inorganic material, for example, a glass epoxy substrate can be given.

【００４１】基板２０の全体形状は特に限定されず、矩
形、多角形、あるいは複数の矩形を組み合わせた形状の
いずれであってもよい。基板２０の厚みも限定されな
い。The overall shape of the substrate 20 is not particularly limited, and may be a rectangle, a polygon, or a combination of a plurality of rectangles. The thickness of the substrate 20 is not limited.

【００４２】図２は、配線を示す斜視図である。配線２
２は、基板２０に支持されており、例えば、基板２０の
少なくとも一方の面に配線２２が形成されている。配線
２２とは、少なくとも２点の電気的な接続を図る部分を
指し、独立して形成された複数の配線２２を配線パター
ンと称してもよい。配線２２は、銅（Ｃｕ）、クローム
（Ｃｒ）、チタン（Ｔｉ）、ニッケル（Ｎｉ）、チタン
タングステン（Ｔｉ−Ｗ）のうちのいずれかを積層し
て、あるいはいずれかの一層で形成してもよい。この場
合、配線２２は、ハンダ、スズ、金、ニッケルなどでメ
ッキされていることが好ましい。FIG. 2 is a perspective view showing the wiring. Wiring 2
2 is supported by the substrate 20, for example, the wiring 22 is formed on at least one surface of the substrate 20. The wiring 22 refers to a portion for electrically connecting at least two points, and a plurality of wirings 22 formed independently may be referred to as a wiring pattern. The wiring 22 is formed by stacking any one of copper (Cu), chromium (Cr), titanium (Ti), nickel (Ni), and titanium tungsten (Ti-W), or by forming any one layer. Is also good. In this case, the wiring 22 is preferably plated with solder, tin, gold, nickel, or the like.

【００４３】配線２２を構成する材料は、バンプ１６を
構成する材料よりも硬いことが好ましい。例えば、図１
に示す配線２２は、パターニング（エッチング）しやす
い材料（例えば銅）からなるコア層と、その表面を覆う
硬度の高い材料（例えばニッケル）からなる中間層と、
さらにその表面を覆う導電性の高い材料（例えば金）か
らなる表面層と、を有する。この構造によれば、バンプ
１６を硬くするとともに、電気的な接続信頼性を高める
ことができる。The material forming the wiring 22 is preferably harder than the material forming the bump 16. For example, FIG.
Are formed of a core layer made of a material (for example, copper) that is easy to be patterned (etched), an intermediate layer made of a material having a high hardness (for example, nickel) covering the surface thereof,
And a surface layer made of a highly conductive material (eg, gold) covering the surface. According to this structure, the bumps 16 can be hardened and the electrical connection reliability can be improved.

【００４４】また、ニッケルは硬い材料であり、ニッケ
ルで接合部２４の表面層を形成すれば、接合部２４をバ
ンプ１６に食い込ませやすい。例えば、基板２０に銅な
どで配線２２の下地を形成し、厚付けの無電解Ｎｉメッ
キ（十数μｍ程度）を行って、ニッケルの表面層を形成
してもよい。無電解Ｎｉメッキは、細線パターンに対し
ても有利であり、細ったパターンに対しても、ある程度
の配線厚を持ったパターンを形成することができる。し
たがって、狭ピッチの配線２２を太らせることができ
る。Nickel is a hard material, and if the surface layer of the joint 24 is formed of nickel, the joint 24 can be easily cut into the bump 16. For example, a base layer of the wiring 22 may be formed on the substrate 20 with copper or the like, and a thick electroless Ni plating (about ten and several μm) may be performed to form a nickel surface layer. Electroless Ni plating is also advantageous for a fine line pattern, and a pattern having a certain wiring thickness can be formed even for a fine pattern. Therefore, the wiring 22 having a narrow pitch can be made thicker.

【００４５】本実施の形態では、配線２２は、ほぼ同一
の縦断面が連続する線状をなし、基板２０側の基端部よ
りも上端部が細く形成されている。配線２２の一部が、
半導体チップ１０に設けられたバンプ１６と接合するた
めの接合部２４となっている。接合部２４は、バンプ１
６と接触する部分（バンプ１６に埋まる部分）と基板２
０側の基端部（基板２０に支持される部分）とを含む。
なお、接合部２４の高さは、少なくとも２０μｍ〜３０
μｍ程度であることが好ましい。配線２２の全体がほぼ
同一の縦断面で同じ高さであってもよいし、接合部２４
とその他の部分とが異なる形状又は高さであってもよ
い。In the present embodiment, the wiring 22 has a linear shape in which substantially the same vertical sections are continuous, and the upper end is formed thinner than the base end on the substrate 20 side. A part of the wiring 22
It serves as a bonding portion 24 for bonding to the bump 16 provided on the semiconductor chip 10. The bonding portion 24 is formed of the bump 1
6 (the portion buried in the bump 16) and the substrate 2
0 base end (portion supported by the substrate 20).
In addition, the height of the joining portion 24 is at least 20 μm to 30 μm.
It is preferably about μm. The entire wiring 22 may have substantially the same vertical cross section and the same height,
And other portions may have different shapes or heights.

【００４６】このような形状の配線２２は、銅箔等の金
属箔を接着材料（図示せず）を介して基板２０に貼り付
けて、フォトリソグラフィを適用した後に、等方性のエ
ッチングを行って形成することができる。また、銅から
なるコア層の表面にメッキ（電解メッキでもよいが好ま
しくは無電解メッキ）によって硬度の高い材料（例えば
ニッケル）で中間層を形成し、同様にして導電性の高い
材料（例えば金）からなる表面層を形成してもよい。For the wiring 22 having such a shape, a metal foil such as a copper foil is attached to the substrate 20 via an adhesive material (not shown), and isotropic etching is performed after applying photolithography. Can be formed. In addition, an intermediate layer is formed on the surface of the core layer made of copper by a material having high hardness (for example, nickel) by plating (electrolytic plating may be used, but preferably electroless plating), and a material having high conductivity (for example, gold) is formed in the same manner. ) May be formed.

【００４７】このような３層基板の他に、接着剤なしで
配線２２を基板２０に形成して２層基板を構成してもよ
い。例えば、スパッタリング等によって金属層を形成
し、これを等方性のエッチングでパターニングして、配
線２２を形成してもよい。また、銅からなるコア層の表
面にメッキ（電解メッキでもよいが好ましくは無電解メ
ッキ）によって硬度の高い材料（例えばニッケル）で中
間層を形成し、同様にして導電性の高い材料（例えば
金）からなる表面層を形成してもよい。In addition to such a three-layer substrate, the wiring 22 may be formed on the substrate 20 without using an adhesive to form a two-layer substrate. For example, the wiring 22 may be formed by forming a metal layer by sputtering or the like and patterning the metal layer by isotropic etching. In addition, an intermediate layer is formed on the surface of the core layer made of copper by a material having high hardness (for example, nickel) by plating (electrolytic plating may be used, but preferably electroless plating), and a material having high conductivity (for example, gold) is formed in the same manner. ) May be formed.

【００４８】本実施の形態では、図１（Ａ）に示すよう
に、配線２２の接合部２４と、バンプ１６とを対向させ
て配置し、図１（Ｂ）に示すように、接合部２４をバン
プ１６に入り込ませる。好ましくは、接合部２４の上端
部をバンプ１６に埋め込む。In this embodiment, as shown in FIG. 1A, the bonding portion 24 of the wiring 22 and the bump 16 are arranged so as to face each other, and as shown in FIG. Into the bump 16. Preferably, the upper end of the joint 24 is embedded in the bump 16.

【００４９】半導体チップ１０と基板２０とは、接着剤
２６によって接着されている。接着剤２６は、被接続体
同士の電気的な接続性能を向上させるために、導電粒子
２７を含んでいる。導電粒子２７は、例えば、ロウ材、
ハンダ等の粒子で構成され、それらが接着材料中に分散
している。こうすることで、バンプ１６と接合部２４と
の間に、導電粒子２７が介在して電気的な接続性能を向
上させることができる。The semiconductor chip 10 and the substrate 20 are adhered by an adhesive 26. The adhesive 26 contains conductive particles 27 in order to improve the electrical connection performance between the objects to be connected. The conductive particles 27 are, for example, brazing material,
It is composed of particles such as solder, which are dispersed in the adhesive material. By doing so, the conductive particles 27 are interposed between the bump 16 and the bonding portion 24, and the electrical connection performance can be improved.

【００５０】接着剤２６は、導電粒子が分散された異方
性導電接着剤（ＡＣＡ）、例えば異方性導電膜（ＡＣ
Ｆ）や異方性導電ペースト（ＡＣＰ）であってもよい。
異方性導電接着剤は、バインダに導電粒子（フィラー）
が分散されたもので、分散剤が添加される場合もある。
異方性導電接着剤のバインダとして、熱硬化性の接着剤
が使用されることが多い。The adhesive 26 is made of an anisotropic conductive adhesive (ACA) in which conductive particles are dispersed, for example, an anisotropic conductive film (AC).
F) or an anisotropic conductive paste (ACP).
Anisotropic conductive adhesive uses conductive particles (filler) as binder
Are dispersed, and a dispersant may be added in some cases.
A thermosetting adhesive is often used as a binder for the anisotropic conductive adhesive.

【００５１】こうして、接合部２４とバンプ１６とが電
気的に接続される。接合部２４とバンプ１６とを接触、
好ましくは面接触させてもよい。なお、接合部２４が平
坦な上端面を有する場合には、接合部２４の側面がバン
プ１６と接触せず、接合部２４の上端面がバンプ１６と
接触していてもよい。本実施の形態によれば、配線２２
の接合部２４をバンプ１６に入り込ませるので、複数の
バンプ１６と配線２２とのギャップが均一でなくても、
信頼性の高い電気的接続が可能になる。また、接合部２
４とバンプ１６とが横方向にずれる力が加えられても、
電気的な接続状態が維持される。In this way, the joint 24 and the bump 16 are electrically connected. A contact between the bonding portion 24 and the bump 16;
Preferably, they may be brought into surface contact. When the joint 24 has a flat upper end surface, the side surface of the joint 24 may not contact the bump 16 and the upper end surface of the joint 24 may contact the bump 16. According to the present embodiment, the wiring 22
Of the bumps 16 and the wirings 22 are not uniform even if the gaps between the plurality of bumps 16 and the wirings 22 are not uniform.
Reliable electrical connection is made possible. Also, joint 2
Even if a force is applied to shift the bumps 4 and the bumps 16 in the lateral direction,
The electrical connection state is maintained.

【００５２】本実施の形態に係る半導体装置の製造方法
では、上記方法を含んで半導体チップ１０を基板２０に
実装する。図３は、本実施の形態に係る半導体チップの
実装方法を示す図である。なお、図３は、図１（Ａ）及
び図１（Ｂ）とは異なる線で切った断面図であり、すな
わち、図２に示す配線２２の長手方向の軸線に沿って断
面図である。In the method of manufacturing a semiconductor device according to the present embodiment, the semiconductor chip 10 is mounted on the substrate 20 including the above method. FIG. 3 is a diagram illustrating a method of mounting a semiconductor chip according to the present embodiment. 3 is a cross-sectional view taken along a line different from FIGS. 1A and 1B, that is, a cross-sectional view along the longitudinal axis of the wiring 22 shown in FIG.

【００５３】半導体チップ１０は、配線２２が形成され
た基板２０上に、フェースダウン実装（フリップチップ
実装）される。図３に示すように、半導体チップ１０と
基板２０との間には、接着剤２６を設ける。接着剤２６
は、液状又はゲル状で用意されるものであってもよい
し、シート状で用意される接着シートであってもよい。
接着剤２６は、エポキシ樹脂を主な材料とするものであ
ってもよい。The semiconductor chip 10 is mounted face-down (flip-chip mounting) on the substrate 20 on which the wiring 22 is formed. As shown in FIG. 3, an adhesive 26 is provided between the semiconductor chip 10 and the substrate 20. Adhesive 26
May be prepared in liquid or gel form, or may be an adhesive sheet prepared in sheet form.
The adhesive 26 may be mainly made of epoxy resin.

【００５４】基板２０における少なくとも接着剤２６を
設ける領域は、粗面となっていてもよい。すなわち、基
板２０の表面をその平坦性をなくすように荒らしてもよ
い。基板２０の表面は、サンドブラストを用いて機械的
に、又はプラズマ、紫外線、オゾン等を用いて物理的
に、エッチング材を用いて化学的に荒らすことができ
る。これらにより、基板２０と半導体チップ１０の接着
面積を増大させたり、物理的、化学的な接着力を増大さ
せたりして、両者をより強く接着することができる。接
着剤２６の収縮力を利用して、接合部２４の側面とバン
プ１６とを圧接させれば、両者の電気的な接続信頼性が
向上する。At least the region of the substrate 20 where the adhesive 26 is provided may be roughened. That is, the surface of the substrate 20 may be roughened so as to lose its flatness. The surface of the substrate 20 can be mechanically roughened using sandblasting, physically roughened using plasma, ultraviolet light, ozone, or the like, or chemically roughened using an etching material. Thus, the bonding area between the substrate 20 and the semiconductor chip 10 can be increased, or the physical and chemical bonding strength can be increased, so that the two can be more strongly bonded. If the side surface of the joint 24 is pressed against the bump 16 by utilizing the contraction force of the adhesive 26, the reliability of the electrical connection between the two is improved.

【００５５】接着剤２６は、半導体チップ１０及び基板
２０のうち、少なくとも一方に設ければよい。例えば、
図３に示す例では、接着剤２６を液状又はゲル状で用意
し、基板２０上にこれを設ける。なお、接着剤２６は、
半導体チップ１０の搭載面の全面に応じて設ける必要は
なく、それより狭い領域に設けてもよい。半導体チップ
１０及び配線２２を対向する方向に加圧すると、接着剤
２６は、外方向に拡がる。さらに、加圧によって、図１
（Ｂ）に示すように、接合部２４をバンプ１６に入り込
ませる。こうして、接合部２４とバンプ１６との電気的
接続を行うことができる。また、接着剤２６を固化させ
て、半導体チップ１０と基板２０との固定を行う。こう
して、半導体装置を得ることができる。The adhesive 26 may be provided on at least one of the semiconductor chip 10 and the substrate 20. For example,
In the example shown in FIG. 3, the adhesive 26 is prepared in a liquid or gel state, and is provided on the substrate 20. The adhesive 26 is
It is not necessary to provide the semiconductor chip 10 on the entire mounting surface, and the semiconductor chip 10 may be provided in a smaller area. When the semiconductor chip 10 and the wiring 22 are pressed in the opposite direction, the adhesive 26 spreads outward. Further, by pressurization, FIG.
As shown in FIG. 2B, the bonding portion 24 is inserted into the bump 16. Thus, the electrical connection between the joint 24 and the bump 16 can be made. Further, the semiconductor chip 10 and the substrate 20 are fixed by solidifying the adhesive 26. Thus, a semiconductor device can be obtained.

【００５６】本実施の形態によれば、半導体チップ１０
と基板２０とを接着する工程で、配線２２の接合部２４
とバンプ１６との電気的接続も図ることができ、工程の
短縮を図ることができる。According to the present embodiment, the semiconductor chip 10
In the step of bonding the wiring 22 and the substrate 20, the bonding portion 24 of the wiring 22
And the bumps 16 can be electrically connected, and the process can be shortened.

【００５７】図４は、上記半導体装置をＩＣカードとし
て構成した例を示す図である。図４に示すＩＣカード
は、上記半導体装置の構成の他に、補強板２８と、ラミ
ネート層３０とを有する。補強板２８は、例えば半導体
チップ１０の裏面（バンプ１６は反対側の面）に設けら
れ、曲げ応力から半導体チップ１０を保護するものであ
る。ラミネート層３０は、ＩＣカードの表裏面となる層
であり、必要に応じて印刷がされてなる。FIG. 4 is a diagram showing an example in which the semiconductor device is configured as an IC card. The IC card shown in FIG. 4 includes a reinforcing plate 28 and a laminate layer 30 in addition to the configuration of the semiconductor device. The reinforcing plate 28 is provided, for example, on the back surface of the semiconductor chip 10 (the surface opposite to the bump 16) and protects the semiconductor chip 10 from bending stress. The laminate layer 30 is a layer to be the front and back surfaces of the IC card, and is printed as necessary.

【００５８】図５は、上記半導体装置に外部端子が設け
られた例を示す図である。すなわち、基板２０にスルー
ホール３２などが形成され、外部端子３４が、配線２２
と電気的に接続されて設けられている。図６には、外部
端子３４を有する半導体装置１を実装した回路基板１０
００が示されている。回路基板１０００には例えばガラ
スエポキシ基板等の有機系基板を用いることが一般的で
ある。回路基板１０００には例えば銅などからなる配線
パターンが所望の回路となるように形成されていて、そ
れらの配線パターンと半導体装置１の外部端子３４とを
機械的に接続することでそれらの電気的導通を図る。FIG. 5 is a diagram showing an example in which external terminals are provided on the semiconductor device. That is, through holes 32 and the like are formed in the substrate 20, and the external terminals 34
Are provided so as to be electrically connected. FIG. 6 shows a circuit board 10 on which the semiconductor device 1 having the external terminals 34 is mounted.
00 is shown. Generally, an organic substrate such as a glass epoxy substrate is used for the circuit board 1000. Wiring patterns made of, for example, copper or the like are formed on the circuit board 1000 so as to form a desired circuit, and these wiring patterns are electrically connected to the external terminals 34 of the semiconductor device 1 so that their electrical Conduct continuity.

【００５９】そして、本発明を適用した半導体装置１を
有する電子機器として、図７にはノート型パーソナルコ
ンピュータ２０００、図８には携帯電話３０００が示さ
れている。FIG. 7 shows a notebook personal computer 2000 and FIG. 8 shows a mobile phone 3000 as an electronic apparatus having the semiconductor device 1 to which the present invention is applied.

【００６０】本発明は、上記実施の形態に限定されるも
のではなく、種々の変形が可能である。例えば、図９に
示すように、配線の接合部４０は、複数段を有する形状
であってもよい。詳しくは、基板２０（図１（Ａ）参
照）側の基端部と、その上に形成される上端部と、が異
なる大きさで接合部４０が形成されていてもよい。この
場合、基端部の上面と、上端部の上面との高さ位置が異
なり、接合部４０は複数の高さ位置の面を持つ。したが
って、接合部４０は、複数段を有する。The present invention is not limited to the above embodiment, but can be variously modified. For example, as shown in FIG. 9, the bonding portion 40 of the wiring may have a shape having a plurality of steps. More specifically, the joint 40 may be formed so that the base end on the substrate 20 (see FIG. 1A) side and the upper end formed thereon have different sizes. In this case, the height positions of the upper surface of the base end portion and the upper surface of the upper end portion are different, and the bonding portion 40 has a surface at a plurality of height positions. Therefore, the joint 40 has a plurality of steps.

【００６１】あるいは、図１０に示すように、配線の接
合部５０は、断面において上端の方向に尖鋭の形状、例
えば三角形であってもよい。この形状の接合部５０は、
バンプ１６が硬い場合に刺しやすい。Alternatively, as shown in FIG. 10, the connecting portion 50 of the wiring may have a sharp cross-section toward the upper end, for example, a triangular shape. This shape of the joint 50
When the bump 16 is hard, it is easy to stab.

【００６２】さらに、図１１に示すように、配線が、他
の部分よりも面積の大きいランド部を有し、ランド部が
接合部６０であってもよい。ランド部は、電気的接続部
を十分に確保する機能を有する。この場合、ランド部と
しての接合部６０は、基板２０側の基端部よりも上端部
が小さく形成されていてもよく、上端部に向けて尖鋭形
状をなしていてもよい。Further, as shown in FIG. 11, the wiring may have a land portion having a larger area than other portions, and the land portion may be the joint portion 60. The land has a function of sufficiently securing an electrical connection. In this case, the joining portion 60 as a land portion may be formed such that the upper end portion is smaller than the base end portion on the substrate 20 side, or may have a sharp shape toward the upper end portion.

【００６３】また、図１２に示すように、配線１２２が
複数の接合部１２４を有し、１つのバンプ１６に複数の
接合部１２４が入り込んでもよい。複数の接合部１２４
は、並列して形成されてもよい。これによれば、バンプ
１６に食い込む部分が増えるので、より強固な接続が得
られる。また、複数の接合部１２４によって凹凸ができ
るので、導電粒子２７の逃げが防止され、介在する導電
粒子２７の数を増やすことができる。Further, as shown in FIG. 12, the wiring 122 may have a plurality of joints 124 and the plurality of joints 124 may enter one bump 16. Multiple joints 124
May be formed in parallel. According to this, a portion that bites into the bump 16 increases, so that a stronger connection can be obtained. In addition, since the plurality of joints 124 form irregularities, escape of the conductive particles 27 is prevented, and the number of conductive particles 27 interposed can be increased.

【００６４】以上の変形例で、具体的に説明した内容以
外の点については、上述した実施の形態と同じ内容が当
てはまり、同じ効果を達成することができる。In the above modification, the same contents as those of the above-described embodiment apply to points other than the contents specifically described, and the same effects can be achieved.

【００６５】なお、上述した実施の形態の「半導体チッ
プ」を「電子素子」に置き換えて、電子部品を製造する
こともできる。このような電子素子を使用して製造され
る電子部品として、例えば、光素子、抵抗器、コンデン
サ、コイル、発振器、フィルタ、温度センサ、サーミス
タ、バリスタ、ボリューム又はヒューズなどがある。Note that an electronic component can be manufactured by replacing the “semiconductor chip” in the above embodiment with an “electronic element”. Electronic components manufactured using such electronic devices include, for example, optical devices, resistors, capacitors, coils, oscillators, filters, temperature sensors, thermistors, varistors, volumes or fuses.

【図面の簡単な説明】[Brief description of the drawings]

【図１】図１（Ａ）及び図１（Ｂ）は、本発明を適用し
た実施の形態に係る半導体装置の製造方法を示す図であ
る。FIGS. 1A and 1B are views showing a method for manufacturing a semiconductor device according to an embodiment to which the present invention is applied; FIGS.

【図２】図２は、本発明を適用した実施の形態に係る配
線を示す図である。FIG. 2 is a diagram illustrating a wiring according to an embodiment to which the present invention is applied;

【図３】図３は、本発明を適用した実施の形態に係る半
導体装置の製造方法を示す図である。FIG. 3 is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment to which the present invention is applied.

【図４】図４は、本実施の形態に係る半導体装置を示す
図である。FIG. 4 is a diagram showing a semiconductor device according to the present embodiment;

【図５】図５は、本実施の形態に係る半導体装置を示す
図である。FIG. 5 is a diagram showing a semiconductor device according to the present embodiment;

【図６】図６は、本実施の形態に係る半導体装置が実装
された回路基板を示す図である。FIG. 6 is a diagram illustrating a circuit board on which the semiconductor device according to the present embodiment is mounted;

【図７】図７は、本実施の形態に係る半導体装置を有す
る電子機器を示す図である。FIG. 7 is a diagram illustrating an electronic device including the semiconductor device according to the embodiment;

【図８】図８は、本実施の形態に係る半導体装置を有す
る電子機器を示す図である。FIG. 8 is a diagram illustrating an electronic device including the semiconductor device according to the embodiment;

【図９】図９は、本発明を適用した実施の形態に係る半
導体装置の変形例を示す図である。FIG. 9 is a diagram showing a modification of the semiconductor device according to the embodiment to which the present invention is applied;

【図１０】図１０は、本発明を適用した実施の形態に係
る半導体装置の変形例を示す図である。FIG. 10 is a view showing a modification of the semiconductor device according to the embodiment to which the present invention is applied;

【図１１】図１１は、本発明を適用した実施の形態に係
る半導体装置の変形例を示す図である。FIG. 11 is a diagram showing a modification of the semiconductor device according to the embodiment to which the present invention is applied;

【図１２】図１２は、本発明を適用した実施の形態に係
る半導体装置の変形例を示す図である。FIG. 12 is a diagram showing a modification of the semiconductor device according to the embodiment to which the present invention is applied;

【符号の説明】[Explanation of symbols]

１０ 半導体チップ １２ 電極 １６ バンプ ２０ 基板 ２２ 配線 ２４ 接合部 ２６ 接着剤 ２７ 導電粒子 ３４ 外部端子 ４０、５０、６０ 接合部 DESCRIPTION OF SYMBOLS 10 Semiconductor chip 12 Electrode 16 Bump 20 Substrate 22 Wiring 24 Joint 26 Adhesive 27 Conductive particle 34 External terminal 40, 50, 60 Joint

───────────────────────────────────────────────────── フロントページの続き Ｆターム(参考） 5E077 BB28 BB31 BB38 CC26 DD04 HH07 HH09 JJ11 JJ21 JJ30 5E085 BB08 BB28 CC03 DD06 EE02 EE23 EE34 FF11 JJ06 JJ31 5E319 AA03 AB05 AC01 BB11 CC02 CC61 5F044 KK02 KK04 KK17 LL07 LL09 LL11 LL15 QQ02 RR19  ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5E077 BB28 BB31 BB38 CC26 DD04 HH07 HH09 JJ11 JJ21 JJ30 5E085 BB08 BB28 CC03 DD06 EE02 EE23 EE34 FF11 JJ06 JJ31 5E319 AA03 AB05 AC01 BB11 CC02 KK17 LL04 KK04 RR19

Claims (19)

【特許請求の範囲】[Claims] 【請求項１】 複数の電極を有し、各電極にバンプが形
成されてなる半導体チップと、 前記半導体チップが搭載され、前記バンプとの少なくと
も１つの接合部を有する配線が形成された基板と、 導電粒子を含有して、前記半導体チップと前記基板とを
接着する接着剤と、を含み、 前記接合部は、前記バンプに入り込み、前記導電粒子
は、前記接合部とバンプとの間に介在してなる半導体装
置。A semiconductor chip having a plurality of electrodes and bumps formed on each electrode; and a substrate on which the semiconductor chip is mounted and on which a wiring having at least one junction with the bump is formed. An adhesive containing conductive particles and bonding the semiconductor chip and the substrate, wherein the bonding portion enters the bump, and the conductive particles are interposed between the bonding portion and the bump. Semiconductor device. 【請求項２】 請求項１記載の半導体装置において、 前記配線は、複数の前記接合部を有し、 いずれか１つの前記バンプに、前記接合部のうちの複数
が入り込んでなる半導体装置。2. The semiconductor device according to claim 1, wherein the wiring has a plurality of the joining portions, and a plurality of the joining portions enter one of the bumps. 【請求項３】 複数の電極を有し、各電極にバンプが形
成されてなる半導体チップと、 前記半導体チップが搭載され、前記バンプとの接合部を
複数有する配線が形成された基板と、 を含み、 前記配線は、いずれか一つの前記バンプに、前記接合部
のうちの複数が入り込んでなる半導体装置。3. A semiconductor chip having a plurality of electrodes and a bump formed on each electrode, and a substrate on which the semiconductor chip is mounted and a wiring having a plurality of joints with the bumps is formed. The semiconductor device according to claim 1, wherein the wiring includes a plurality of the bonding portions in any one of the bumps. 【請求項４】 請求項１から請求項３のいずれかに記載
の半導体装置において、 前記接合部の表面は、ニッケルメッキ層で形成されてな
る半導体装置。4. The semiconductor device according to claim 1, wherein a surface of said joint is formed of a nickel plating layer. 【請求項５】 請求項１から請求項４のいずれかに記載
の半導体装置において、 前記接合部は、ほぼ同一の縦断面が連続する線状をな
し、前記基板側の基端部よりも上端部が細く形成されて
なる半導体装置。5. The semiconductor device according to claim 1, wherein the joining portion has a linear shape in which substantially the same vertical cross section is continuous, and is upper end than a base end on the substrate side. A semiconductor device having a thin portion. 【請求項６】 請求項１から請求項４のいずれかに記載
の半導体装置において、 前記接合部は、前記基板側の基端部よりも上端部が小さ
く形成されたランド部である半導体装置。6. The semiconductor device according to claim 1, wherein the bonding portion is a land portion having an upper end portion smaller than a base end portion on the substrate side. 【請求項７】 請求項１から請求項６のいずれかに記載
の半導体装置において、 前記接合部は、複数段を有する形状である半導体装置。7. The semiconductor device according to claim 1, wherein said junction has a shape having a plurality of steps. 【請求項８】 請求項１から請求項７のいずれかに記載
の半導体装置において、 前記接着剤の収縮力によって、前記接合部の側面と前記
バンプとが圧接してなる半導体装置。8. The semiconductor device according to claim 1, wherein a side surface of the joint and the bump are pressed against each other by a contraction force of the adhesive. 【請求項９】 請求項１から請求項８のいずれかに記載
の半導体装置において、ＩＣカードとして構成された半
導体装置。9. The semiconductor device according to claim 1, wherein the semiconductor device is configured as an IC card. 【請求項１０】 請求項１から請求項８のいずれかに記
載の半導体装置において、 外部端子をさらに有する半導体装置。10. The semiconductor device according to claim 1, further comprising an external terminal. 【請求項１１】 請求項１０記載の半導体装置が実装さ
れた回路基板。11. A circuit board on which the semiconductor device according to claim 10 is mounted. 【請求項１２】 請求項１０記載の半導体装置を有する
電子機器。12. Electronic equipment having the semiconductor device according to claim 10. 【請求項１３】 複数の電極を有して各電極にバンプが
形成されてなる半導体チップを、導電粒子を含有する接
着剤を使用して、配線が形成された基板に実装する工程
を含み、 前記配線は、前記バンプとの接合部を有し、 前記接合部を、前記バンプに入り込ませ、前記導電粒子
を前記接合部とバンプとの間に介在させる半導体装置の
製造方法。13. A step of mounting a semiconductor chip having a plurality of electrodes and having bumps formed on each electrode on a substrate on which wiring is formed, using an adhesive containing conductive particles, The method of manufacturing a semiconductor device, wherein the wiring has a bonding portion with the bump, the bonding portion enters the bump, and the conductive particles are interposed between the bonding portion and the bump. 【請求項１４】 請求項１３記載の半導体装置の製造方
法において、 前記配線は、複数の前記接合部を有し、 いずれか１つの前記バンプに、前記接合部のうちの複数
を入り込ませる半導体装置の製造方法。14. The semiconductor device manufacturing method according to claim 13, wherein the wiring has a plurality of the joints, and a plurality of the joints are inserted into any one of the bumps. Manufacturing method. 【請求項１５】 請求項１３又は請求項１４記載の半導
体装置の製造方法において、 前記接合部の表面を、ニッケルメッキ層で形成する半導
体装置の製造方法。15. The method of manufacturing a semiconductor device according to claim 13, wherein the surface of the joint is formed of a nickel plating layer. 【請求項１６】 請求項１３から請求項１５のいずれか
に記載の半導体装置の製造方法において、 前記接合部を、ほぼ同一の縦断面が連続する線状に形成
するとともに、前記基板側の基端部よりも上端部を細く
形成する半導体装置の製造方法。16. The method for manufacturing a semiconductor device according to claim 13, wherein said bonding portion is formed in a linear shape having substantially the same vertical cross section, and said base portion on said substrate side. A method for manufacturing a semiconductor device in which an upper end portion is formed thinner than an end portion. 【請求項１７】 請求項１３から請求項１５のいずれか
に記載の半導体装置の製造方法において、 前記接合部を、前記基板側の基端部よりも上端部が小さ
く形成されたランド部として形成する半導体装置の製造
方法。17. The method for manufacturing a semiconductor device according to claim 13, wherein the bonding portion is formed as a land portion having an upper end portion smaller than a base end portion on the substrate side. Semiconductor device manufacturing method. 【請求項１８】 請求項１３から請求項１７のいずれか
に記載の半導体装置の製造方法において、 前記接合部を、複数段を有する形状で形成する半導体装
置の製造方法。18. The method of manufacturing a semiconductor device according to claim 13, wherein the bonding portion is formed in a shape having a plurality of steps. 【請求項１９】 請求項１３から請求項１８のいずれか
に記載の半導体装置の製造方法において、 前記接着剤の収縮力によって、前記配線の前記接合部の
側面と前記バンプとを圧接させる半導体装置の製造方
法。19. The method of manufacturing a semiconductor device according to claim 13, wherein a side surface of the joint of the wiring and the bump are pressed against each other by a contraction force of the adhesive. Manufacturing method.
JP2000034501A 2000-02-14 2000-02-14 Semiconductor device and its manufacturing method, circuit board, and electronic equipment Withdrawn JP2001223243A (en)

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