JPH10191389A - Data write method to image memory and write device of image data to image memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the number of memories and the capacity by providing a process where luminance data are written to part of areas of a memory map by one image pattern and converted color difference data are written to part of the remaining areas by one image pattern so as to store the digital image data to the memory efficiently. SOLUTION: When image data of 4:2:2 configuration are given to a buffer device 1, image data of two interleaved color difference data with respect to 4-picture element of luminance data of 4:2:2 configuration are serially outputted from an output of a selector 17. Then image data outputted from the buffer device 1 are written in an address of a DRAM 2 designated by an address designation circuit 3. The address designation circuit 3 controls addresses such that luminance data Y are stored to part of area of the DRAM 2 and two interleaved color difference signals C are stored to part of the remaining areas. In this case, two consecutive picture elements are packed in addresses as 16-bit in the depth direction of the addresses.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a memory access method and a data writing device capable of efficiently using a data storage area of a memory by controlling a writing process of digital image data to a memory device.

[0002]

2. Description of the Related Art A method of writing digital image data into a memory according to a conventional technique will be described with reference to FIG.

In FIG. 4, luminance data Y and color difference data C (Cr and Cb) of image data are input to a buffer device 41 in an 8-bit parallel configuration from a signal source (not shown). Although not shown, the buffer device 41 includes two buffer memories for Y data and C data. The horizontal synchronization signal H and the vertical synchronization signal V of the image data are further input to the buffer device 41. The luminance data Y and the chrominance data C once stored in the buffer device 41 are synchronized with the horizontal synchronizing signal H and stored in the DRAM 42a and the DR 42a every line.
The data is written to the AM 42b.

[0004] JPEG (joint photographic expert gr)
Oup), the signal format of digital image data is as shown in FIG. 5, as shown in FIG.
, Y2, Y3), two red difference signals (Cr0, Cr).
2) and two blue difference signals (Cb0, Cb2) as a unit.

FIG. 6 shows a configuration of a memory map of a general DRAM. This DRAM has 1024 × 512
By specifying a row address and a column address in the matrix arrangement described above, data of 8 bits per pixel is stored at each address.

As digital image data for one screen,
Although there is a configuration of 640 × 480, 1024 × 768, 800 × 600, or 1280 × 1024 pixels, the data configuration of one screen that can be stored in the DRAM of FIG. 6 is 640 × 480 image data. The range indicated by the dotted line in FIG. 6 shows a case where image data of 640 × 480 pixels per screen is stored in the DRAM without changing the pixel arrangement.
In the case of 4: 2: 2 format image data, a dotted line 640 × 48 of one DRAM is used for luminance data Y.
0 is occupied, and another 640 × 480 area indicated by a dotted line of another DRAM is divided into two pieces of color difference data Cr and Cb.
Occupy two DRAs as shown in FIG.
M is required.

[0007]

In the case of such a method of writing data to a DRAM, an empty area in which image data is not written, such as an area shown by hatching in FIG. 6, occurs. Normally, a DRAM has a storage capacity of only a discrete standard specification value in units of powers of 2, and the data amount of one image data and the memory capacity often do not match. Therefore, the DR has a size equal to or larger than the size of each row and column of the amount of image data for one sheet, and moreover as close as possible to the capacity of image data.
AM needs to be selected. However, even if such a selection is made, it is inevitable that a considerable wasteful space area is generated in each of the two DRAMs, as shown by hatching in FIG.

An object of the present invention is to provide a method of writing data to an image memory and a method of writing image data to the image memory, which can efficiently store digital image data in the memory and reduce the number and capacity of the memories. A writing device is provided.

[0009]

According to the present invention, there is provided a method of writing data to an image memory for storing digital image data, comprising the steps of: transmitting digital image data including luminance data and two kinds of color difference data from a signal source to a predetermined number of bits; A step of sequentially taking in data in units and holding data of a predetermined pixel in a buffer means; a step of reading the luminance data from the buffer means; and a step of reading two adjacent color difference data in each of the two types of color difference data read from the buffer means. Converting the color difference data for one pixel into color difference data for one pixel; and converting the read luminance data into n for each address.
A step of writing one screen in a partial area of the memory map of the memory in units of the predetermined number of bits (n is an integer of 2 or more), and the conversion into a part of the remaining area of the memory map of the memory Writing color difference data for one screen.

Further, the apparatus for writing digital image data to a memory according to the present invention sequentially reads digital image data including luminance data and two kinds of color difference data from a signal source in units of a predetermined number of bits, and stores data for predetermined pixels. Buffer means for holding, means for reading the luminance data from the buffer means, and for each of the two types of color difference data read from the buffer means, the color difference data for two adjacent pixels is converted to color difference data for one pixel. A data compression means for converting the luminance data into a specified address of the memory; a means for writing data from the buffer means and the data compression means to a specified address of the memory; Unit (n is 2
The above-mentioned integer) is used to write one screen in a part of the memory map of the memory and to write one screen of color difference data converted by the data compression means in a part of the remaining area of the memory map. Addressing means for designating write addresses for luminance data and color difference data;

[0011]

FIG. 1 shows a system for implementing a method for writing digital image data to a memory according to an embodiment of the present invention. In FIG. 1, 1 is a buffer device, and 2 is a DRAM.

Luminance data Y and chrominance data C of image data are input to the buffer device 1 from a signal source (not shown) in an 8-bit parallel configuration. The horizontal synchronization signal and the vertical synchronization signal are omitted. The luminance data Y and the chrominance data C having a 4: 2: 2 configuration and input to the buffer device 1 shown in FIG. 5 are buffer memories 11 and 12 for two luminance data Y and buffer memories for four chrominance data C, respectively. 13 to 16 are stored. When the data is stored in all the buffer memories 11 to 16, the data is read from the buffer memories. Reference numeral 17 denotes a selector, which synchronizes with a clock signal (not shown) to output terminals a, b,
The output of c is sequentially selected and the data is supplied to the DRAM 2. In addition, from the terminal a, two buffer memories 11, 1
2 is read out continuously.

Buffer memories 13 and 14 for color difference data
, 15 and 16 are connected to the data processing circuit 18.
And 19 are combined. Data processing circuits 18 and 19
Has a logic circuit that outputs either one of two pieces of color difference data read from two buffer memories or outputs an average value of two pieces of color difference data. For example, one color difference data Cr0 'is generated from two adjacent color difference data Cr0 and Cr2, and one color difference data Cb0' is generated from two adjacent color difference data Cb0 and Cb2.

Therefore, the buffer device 1 has 4: 2: 2
When the image data having the configuration is input, the output of the selector 17 serially outputs image data composed of two pieces of color difference data thinned out from luminance data for four pixels, that is, a so-called 4: 2: 0 configuration. You. Then, the image data output from the buffer device 1 is written to the address of the DRAM 2 specified by the address specifying circuit 3.
The address designating circuit 3 controls the address so that the luminance data Y is stored in a part of the DRAM 1 as shown in FIG. 1 and two thinned color difference signals C are stored in a part of the remaining area. In this case, the memory map configuration of the DRAM 2 packs the luminance data of two consecutive pixels as 16 bits in the depth direction of the same address. The same applies to the color difference data.

Conventionally, to store a luminance signal Y and a chrominance signal C in 4: 2: 2 format, as shown in FIG. 6, the address occupies 8 bits per address and 640 areas per line for data. However, in the present embodiment, as shown in FIG. 2, 16 bits per address, luminance data Y for one line occupies an area of 320, and color difference data C occupies an area of 80 × 2, as shown in FIG. Image data for one image is stored in a 480 × 480 area. 512x
Image data for one image can be stored in one 512 DRAM, and the capacity and number of DRAMs can be reduced.

Next, the write operation of the embodiment will be further described with reference to the signal diagram of FIG. 3A shows a horizontal synchronization signal input to the buffer device 1, FIG. 3B shows luminance data Y, FIG. 3C shows chrominance data C, and FIGS. A RAS signal and a CAS signal output from the circuit 3;
(F) is a write address (one line), and (g)
Indicates data corresponding to the address.

The addressing circuit 3 has three counters, one for luminance data and two for color data. The luminance data counter starts counting from zero with the horizontal synchronization signal as a timing reference, and resets to 319 after 319 counts. The color difference signal Cr counter is reset when it counts up to 399 with 320 as an initial value. The color difference signal Cb counter is reset when it counts up to 479 with 400 as an initial value.
The address specifying circuit 3 selectively outputs any one of the three counters. The order of selection is as follows, as shown in FIG.

(1) Luminance data Y, (2) Luminance data Y, (3) Red difference data Cr, (4) Empty, (5) Luminance data Y, (6) Luminance data Y, (7) Blue difference data C
b, (8) available

The address specifying circuit 3 repeats the above sequence to select and output a count value. The count value becomes the address signal in FIG. The data and address in the empty cases (4) and (8) may be arbitrary, and no writing is performed. When CAS falls in FIG. 3E, writing is performed, but in cases (4) and (8), CAS falls are not performed.

The present invention is not limited to the embodiments described above, and it is needless to say that various improvements and modifications can be made by those skilled in the art based on the above disclosure.

[0021]

According to the present invention, since the image data can be efficiently stored in the memory, the number and capacity of the memory can be reduced, and the cost of the device using the memory can be reduced. In addition, since the area occupied by the memory of the device using the memory can be reduced, the size of the device can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram of a system for writing image data to a memory according to an embodiment of the present invention.

FIG. 2 is a layout diagram of image data on a memory map of a DRAM according to an embodiment of the present invention.

FIG. 3 is a timing chart of the system of FIG. 1;

FIG. 4 is a block diagram of a system for writing image data to a memory according to a conventional technique.

FIG. 5 is a data configuration diagram of a 4: 2: 2 format of luminance data and color difference data.

FIG. 6 is an arrangement diagram of image data on a memory map of a DRAM according to a conventional technique.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Buffer device 2 DRAM 3 Address designating circuit 11-16 Buffer memory 17 Selector 18, 19 Data processing circuit

Claims (2)

[Claims] 1. A method for writing data to an image memory for storing digital image data, wherein digital image data including luminance data and two kinds of color difference data are sequentially fetched from a signal source in units of a predetermined number of bits. A step of holding data of a predetermined pixel in a buffer unit; a step of reading the luminance data from the buffer unit; and a step of reading the luminance data from the buffer unit. Converting the data into color difference data for one pixel; and converting the read luminance data into a part of the memory map of the memory in units of n × the predetermined number of bits (n is an integer of 2 or more) for each address. Writing one screen in the area; and storing the converted color difference data in a part of the remaining area of the memory map of the memory for one screen. Image data writing method of a memory and having a gradually crowded can process. 2. An apparatus for writing digital image data to a memory, wherein digital image data including luminance data and two types of color difference data are sequentially fetched from a signal source in units of a predetermined number of bits, and data of a predetermined pixel is retained. Buffer means for reading the luminance data from the buffer means; and in each of the two types of color difference data read from the buffer means, the color difference data of two adjacent pixels is converted into color difference data of one pixel. A data compression unit for converting; a unit for writing data from the buffer unit and the data compression unit to a designated address in the memory; and a unit of n × the predetermined number of bits for the read luminance data for each address. (N is an integer of 2 or more) and writes one screen to a part of the memory map of the memory. Addressing means for designating a write address of the luminance data and the chrominance data so as to write the chrominance data converted by the data compression means for one screen in a part of the remaining area of the remap. A device that writes image data to memory.